FPGA: Reduce UltraRAM FIFO (a bit)

2023-05-17 21:55:41 +02:00
parent 33b70551c5
commit 97bf8f7e4a
1 changed files with 1 additions and 1 deletions
@@ -65,7 +65,7 @@ proc create_hier_cell_mac_100g { parentCell nameHier } {
  # Create instance: axis_data_fifo_rx_1, and set properties
  set axis_data_fifo_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_1 ]
  set_property -dict [ list \
-   CONFIG.FIFO_DEPTH {32768} \
+   CONFIG.FIFO_DEPTH {16384} \
   CONFIG.FIFO_MEMORY_TYPE {ultra} \
   CONFIG.ENABLE_ECC {1} \
 ] $axis_data_fifo_rx_1