From 97bf8f7e4a2877c045e9499d6a60cf6e785705e6 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Wed, 17 May 2023 21:55:41 +0200 Subject: [PATCH] FPGA: Reduce UltraRAM FIFO (a bit) --- receiver/scripts/mac_100g_pcie.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/receiver/scripts/mac_100g_pcie.tcl b/receiver/scripts/mac_100g_pcie.tcl index 4188b7827..0a1573940 100644 --- a/receiver/scripts/mac_100g_pcie.tcl +++ b/receiver/scripts/mac_100g_pcie.tcl @@ -65,7 +65,7 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { # Create instance: axis_data_fifo_rx_1, and set properties set axis_data_fifo_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_1 ] set_property -dict [ list \ - CONFIG.FIFO_DEPTH {32768} \ + CONFIG.FIFO_DEPTH {16384} \ CONFIG.FIFO_MEMORY_TYPE {ultra} \ CONFIG.ENABLE_ECC {1} \ ] $axis_data_fifo_rx_1