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FPGA: Add host_writer idle marker

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This commit is contained in:
leonarski_f
2023-05-27 21:45:21 +02:00
parent 19753c697b
commit 72cdb88c0c
10 changed files with 70 additions and 51 deletions
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grpc/jfjoch.proto
+1
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@@ -381,6 +381,7 @@ message FPGAStatus {
uint32 error_packet_len = 39;
uint32 data_collection_counter = 40;
bool host_writer_idle = 41;
}
message DataProcessingSettings {
python/jfjoch_pb2.py
+48 -48
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File diff suppressed because one or more lines are too long
receiver/hdl/action_config.v
+2
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@@ -96,6 +96,7 @@ module action_config
input [0:31] data_collection_counter ,
input data_collection_counter_valid,
input host_writer_idle ,
input calib_data_fifo_empty ,
input calib_data_fifo_full ,
input calib_addr_fifo_empty ,
@@ -389,6 +390,7 @@ always @(posedge clk) begin
reg_ctrl[1] <= reg_data_collection_idle;
reg_ctrl[2] <= data_collection_cancel;
reg_ctrl[3] <= clear_counters;
reg_ctrl[4] <= host_writer_idle;
reg_ctrl[7] <= DESIGN_NUMBER;
reg_ctrl[16] <= mailbox_interrupt_0;
reg_ctrl[17] <= mailbox_interrupt_1;
receiver/hls/hls_jfjoch.h
+1
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@@ -108,6 +108,7 @@ void host_writer(STREAM_512 &data_in,
hls::stream<ap_uint<32> > &s_axis_work_request,
hls::stream<ap_uint<32> > &m_axis_completion,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,
ap_uint<8> &err_reg);
void timer_hbm(STREAM_512 &in, STREAM_512 &data_out, uint64_t &counter);
receiver/hls/host_writer.cpp
+6
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@@ -83,6 +83,7 @@ void host_writer(STREAM_512 &data_in,
hls::stream<ap_uint<32> > &s_axis_work_request,
hls::stream<ap_uint<32> > &m_axis_completion,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,
ap_uint<8> &err_reg) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
@@ -93,6 +94,7 @@ void host_writer(STREAM_512 &data_in,
#pragma HLS INTERFACE register both axis port=s_axis_work_request
#pragma HLS INTERFACE register ap_vld port=packets_processed
#pragma HLS INTERFACE register ap_vld port=err_reg
#pragma HLS INTERFACE register ap_none port=idle
ap_uint<128> packet_mask[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=packet_mask core=RAM_1P
@@ -113,6 +115,8 @@ void host_writer(STREAM_512 &data_in,
ap_uint<64> curr_offset[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=curr_offset core=RAM_1P
idle = 1;
for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
#pragma HLS UNROLL
curr_frame[i] = UINT64_MAX;
@@ -149,6 +153,7 @@ void host_writer(STREAM_512 &data_in,
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_counter);
idle = 0;
uint64_t total_counter = 0;
packets_processed = 0;
addr_in >> addr;
@@ -258,4 +263,5 @@ void host_writer(STREAM_512 &data_in,
data_in >> packet_in;
write_completion(m_axis_completion, HANDLE_END, 0, total_counter, 0, 0, 0, 0, 0, 0, data_collection_counter);
idle = 1;
}
receiver/host/AcquisitionDevice.cpp
+1
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@@ -369,6 +369,7 @@ JFJochProtoBuf::FPGAStatus AcquisitionDevice::GetStatus() const {
ret.set_error_packet_len(status.udp_err_len);
ret.set_data_collection_counter(status.data_collection_counter);
ret.set_host_writer_idle(full_status_register & (1<<4));
ret.set_frame_statistics_alignment_err(full_status_register & (1 << 24));
ret.set_frame_statistics_tlast_err(full_status_register & (1 << 25));
ret.set_frame_statistics_work_req_err(full_status_register & (1 << 26));
receiver/host/HLSSimulatedDevice.cpp
+3 -2
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@@ -194,7 +194,6 @@ void HLSSimulatedDevice::HLSMainThread() {
uint64_t sls_packets;
uint32_t udp_len_err;
uint32_t udp_eth_err;
uint32_t data_collection_counter;
ap_uint<1> clear_counters = 0;
@@ -311,7 +310,7 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] {
host_writer(converted_2, addr3, datamover_out.GetDataStream(),
datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
packets_processed, err_reg); });
packets_processed, host_writer_idle, err_reg); });
for (auto &i : hls_cores)
i.join();
@@ -372,6 +371,8 @@ uint64_t HLSSimulatedDevice::HW_GetMACAddress() const {
void HLSSimulatedDevice::HW_GetStatus(ActionStatus *status) const {
memset(status, 0, sizeof(ActionStatus));
status->ctrl_reg = ap_uint<1>(host_writer_idle) ? (1 << 4) : 0;
status->modules_internal_packet_generator = 1;
status->max_modules = max_modules;
status->data_collection_counter = data_collection_counter;
}
receiver/host/HLSSimulatedDevice.h
+3
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@@ -32,6 +32,9 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice {
Datamover<512> datamover_out;
ap_uint<1> run_data_collection;
ap_uint<1> cancel_data_collection;
volatile ap_uint<1> host_writer_idle;
uint32_t data_collection_counter;
uint64_t in_mem_location[LOAD_CALIBRATION_BRAM_SIZE];
static const uint64_t fpga_mac_addr = 0xCCAA11223344;
static const uint32_t fpga_ipv4_addr = 0x0132010A;
receiver/host/jfjoch_pcie_status.cpp
+3 -1
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@@ -33,8 +33,10 @@ int main(int argc, char **argv) {
std::cout << "FPGA temperature " << status.fpga_temp_degc() << std::endl;
std::cout << "HBM temperature #0 " << status.hbm_temp_0_degc() << std::endl;
std::cout << "HBM temperature #1 " << status.hbm_temp_1_degc() << std::endl;
std::cout << "Idle " << status.fpga_idle() << std::endl;
std::cout << "Data collection idle " << status.fpga_idle() << std::endl;
std::cout << "Data collection counter " << status.data_collection_counter() << std::endl;
std::cout << "Host writer idle " << status.host_writer_idle() << std::endl;
std::cout << "Full status register " << std::bitset<32>(status.full_status_register()) << std::endl;
std::cout << "Stalls HBM " << status.stalls_hbm() << std::endl;
receiver/scripts/jfjoch.tcl
+2
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@@ -432,6 +432,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net data_collection_fsm_0_out_idle_V [get_bd_pins action_config_0/data_collection_idle] [get_bd_pins data_collection_fsm_0/out_idle]
connect_bd_net -net host_writer_0_err_reg_V [get_bd_pins action_config_0/host_writer_err] [get_bd_pins host_writer_0/err_reg]
connect_bd_net -net host_writer_0_err_reg_V_ap_vld [get_bd_pins action_config_0/host_writer_err_valid] [get_bd_pins host_writer_0/err_reg_ap_vld]
connect_bd_net -net host_writer_0_idle [get_bd_pins action_config_0/host_writer_idle] [get_bd_pins host_writer_0/idle]
connect_bd_net -net host_writer_0_packets_processed [get_bd_pins action_config_0/packets_processed] [get_bd_pins host_writer_0/packets_processed]
connect_bd_net -net host_writer_0_packets_processed_ap_vld [get_bd_pins action_config_0/packets_processed_valid] [get_bd_pins host_writer_0/packets_processed_ap_vld]
connect_bd_net -net mailbox_0_Interrupt_0 [get_bd_pins action_config_0/mailbox_interrupt_0] [get_bd_pins mailbox_0/Interrupt_0]