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mx/Jungfraujoch
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Code Issues Pull Requests Actions Packages Projects Releases 42 Wiki Activity
396 Commits 49 Branches 127 Tags
5d8a85071ee3537011fd0e211ccbf28a59fd00a3
Commit Graph

7 Commits

Author SHA1 Message Date
Filip Leonarski
8626195091 FPGA: fix to deadlock 2023-09-12 20:09:11 +02:00
Filip Leonarski
9d01630cfc FPGA: load calibration works as dedicated function of the card 2023-09-12 14:34:42 +02:00
Filip Leonarski
7a635f1ee8 FPGA: load_calibration clean-up + simplification 2023-09-12 09:16:45 +02:00
Filip Leonarski
8c3a25a8ad FPGA: load calibration operates directly on HBM 2023-09-11 21:47:29 +02:00
Filip Leonarski
1333ce9b29 FPGA: trigger synthesis 2023-09-06 12:36:14 +02:00
Filip Leonarski
3aeb3e09ee FPGA: Do not load internal packet generator frame via DMA 2023-09-06 11:57:16 +02:00
Filip Leonarski
7a98766304 FPGA: Split receiver and FPGA design directories 2023-06-07 21:21:22 +02:00
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