FPGA: trigger synthesis

2023-09-06 12:36:14 +02:00
parent da045c023b
commit 1333ce9b29
1 changed files with 1 additions and 1 deletions
@@ -80,4 +80,4 @@ void load_calibration(STREAM_512 &data_in, STREAM_512 &data_out,
        data_in >> packet_in;
    }
    data_out << packet_in;
-}
+}