maliakal_d
85aca0ffad
moench: insignficant dac naming fix
2020-03-03 16:21:45 +01:00
maliakal_d
fac95516cf
moench: insignficant naming fix
2020-03-03 16:07:37 +01:00
maliakal_d
8abc32e7f1
moench: default pattern file in server, settings, tests
2020-03-03 16:00:01 +01:00
maliakal_d
6bbcf6173d
moench: first version
2020-03-02 18:34:10 +01:00
maliakal_d
a769f7515c
gotthard2 bug fix: fixed pll freq was incorrect when 0 in front
2020-02-28 16:03:15 +01:00
Dhanya Thattil and GitHub
11e7737a2f
gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test ( #80 )
2020-02-28 12:45:02 +01:00
maliakal_d
2e2e91b219
ctb adc: get in uV and print in client in mV to get decimals
2020-02-27 15:43:42 +01:00
maliakal_d
8c8032dc69
ctb bug fix: slow adcs incorrect mv read out, needed clk down and usleep before reading
2020-02-27 09:16:22 +01:00
maliakal_d
90acd51389
server api changes: for mythen3, jungfrau, eiger as well
2020-02-26 17:52:35 +01:00
maliakal_d
fe3a7b0faf
gotthard2: removed unnecessary casting
2020-02-26 11:02:28 +01:00
maliakal_d
6a0a931e3e
gotthard2: bursts and burst period, written to same register as triggers and delay (kept in server as variables) and set if conditions meet. bursts and burst period only in auto timing and burst mode. Also updating theses registers when switching between timing modes or burst modes
2020-02-25 15:45:40 +01:00
maliakal_d
c03bc4a6b4
gotthard2: copy #frames and period when switching between continuous and burst mode
2020-02-24 17:20:51 +01:00
maliakal_d
02b367ffe8
mythen3 and gotthard2: updated clocks
2020-02-24 16:50:47 +01:00
Erik Frojdh
f1bce15a57
replaced udp socket
2020-02-17 17:43:14 +01:00
maliakal_d
dfb1b9ad69
Revert "gotthard2: burst mode check"
...
This reverts commit 4d6996bd55
2020-02-04 15:29:43 +01:00
maliakal_d
4d6996bd55
gotthard2: burst mode check
2020-02-04 15:28:24 +01:00
maliakal_d
0ac28c0208
gotthard2: burst mode check for #frames
2020-02-04 15:27:18 +01:00
maliakal_d
37c3048c2a
gotthard2: bug fix from previosu commit
2020-02-04 12:32:37 +01:00
maliakal_d
d3dc9a7690
gotthard2: disentangled burst mode #frames, exptime, period from start of acquisition, order dependent now for debugging
2020-02-04 12:23:58 +01:00
maliakal_d
806a2736c1
gotthard2: longer wait for startup, period 0
2020-02-04 12:00:07 +01:00
maliakal_d
36bd91daa3
gotthard2: sleep before configuring on chip dacs, default exptime 0 and default period to 1ms
2020-02-04 10:50:01 +01:00
maliakal_d
89c774dbf7
nios programming: check file size first
2020-01-31 11:24:48 +01:00
Dhanya Thattil and GitHub
5ca3a1b685
gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming ( #74 )
2020-01-30 19:52:35 -08:00
maliakal_d
2314fdabd1
merge from mythen3, and jungfrau fix
2020-01-23 16:44:01 +01:00
maliakal_d
abe63acc79
jungfrau fix: wait for acquisition to be done before sending stop receiver
2020-01-23 16:41:09 +01:00
maliakal_d
a9e375ed34
gotthard2: bursttype to burstmode
2020-01-23 11:03:14 +01:00
maliakal_d
f881133795
get/set timing, generate data for gotthard2, vref_rstore instead of restore for gotthard2
2020-01-22 18:18:56 +01:00
maliakal_d
8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
maliakal_d
3ea2520615
PR minor changes
2020-01-22 13:55:10 +01:00
Dhanya Thattil and GitHub
d8fccdcefa
Merge branch 'developer' into gotthard2
2020-01-21 18:18:57 +01:00
maliakal_d
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
maliakal_d
7131f77a3a
eiger: vcal set to 0
2020-01-21 16:10:15 +01:00
maliakal_d
f08d430d16
eiger: vcal set to 0
2020-01-21 16:09:39 +01:00
maliakal_d
e746256653
gotthard2: gain updated
2020-01-21 16:01:38 +01:00
maliakal_d
2e78484b61
gotthard2 virtual server sends data
2020-01-21 14:50:31 +01:00
maliakal_d
c4137dc309
gotthard2: works
2020-01-20 17:03:11 +01:00
maliakal_d
23dffa47df
gotthard2 bug fix: no module attached
2020-01-20 14:42:06 +01:00
maliakal_d
6cfd0f8962
gotthard2: first edit
2020-01-20 12:13:23 +01:00
maliakal_d
6e47f0b7f7
merge resolved
2020-01-20 11:36:35 +01:00
maliakal_d
3c891495db
mythen3: bug fix detector type
2020-01-20 11:32:02 +01:00
maliakal_d
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
Dhanya Thattil and Erik Fröjdh
de53747ddd
Counters ( #71 )
...
* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com >
2020-01-14 17:40:46 +01:00
maliakal_d
7b31fbc002
eiger virtual server bug fix: increasing subdeadtime
2020-01-13 14:18:43 +01:00
maliakal_d
28f8a76dcc
updated binaries
2020-01-10 09:05:26 +01:00
maliakal_d
086cbacd84
mythen3: connected busy signal insttead of timer
2019-12-10 11:03:27 +01:00
maliakal_d
af9b25fd67
eiger: validate trimval range
2019-12-10 10:32:28 +01:00
maliakal_d
504fc2d095
ctb: validate asampes and dsamples > 0 for romode; client: exception caught in acquire to stop receiver and clear busy flag
2019-12-10 10:25:14 +01:00
maliakal_d
5cf1502287
ctb bug fix: 10g adc enable mask
2019-12-09 11:30:54 +01:00
maliakal_d
2ece6b945e
rxr: warnings shouldnt throw exception
2019-11-29 11:09:41 +01:00
maliakal_d
3486137de3
bfin warnings fixed
2019-11-27 18:22:33 +01:00
maliakal_d
