detectors/slsDetectorPackage
24
1
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2026-01-16 22:13:23 +01:00
Code Issues Actions Packages Releases Activity

merge from developer

Browse Source
This commit is contained in:
maliakal_d
2020-01-22 17:30:13 +01:00
parent 981b13494c ffc09ed19c
commit 8cbf3c62a9
36 changed files with 1260 additions and 404 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
View File

Binary file not shown.

8
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
View File

@@ -56,9 +56,9 @@ uint32_t adcEnableMask_1g = 0;
uint8_t adcEnableMask_10g = 0;
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0};
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
int dacValues[NDAC] = {0};
int dacValues[NDAC] = {};
// software limit that depends on the current chip on the ctb
int vLimit = 0;
int highvoltage = 0;
@@ -1420,7 +1420,7 @@ int setHighVoltage(int val){
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch((int)arg){
switch(arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
@@ -2559,7 +2559,7 @@ int calculateDataBytes(){
return dataBytes;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}

BIN
slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
View File

Binary file not shown.

4
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
View File

@@ -1108,7 +1108,7 @@ int setHighVoltage(int val) {
void setTiming( enum timingMode arg) {
enum timingMode ret=GET_TIMING_MODE;
if (arg != GET_TIMING_MODE) {
switch((int)arg) {
switch(arg) {
case AUTO_TIMING: ret = 0; break;
case TRIGGER_EXPOSURE: ret = 2; break;
case BURST_TRIGGER: ret = 1; break;
@@ -2041,7 +2041,7 @@ int calculateDataBytes() {
int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}

2
slsDetectorServers/gotthard2DetectorServer/CMakeLists.txt
View File

@@ -22,7 +22,7 @@ target_include_directories(gotthard2DetectorServer_virtual
)
target_compile_definitions(gotthard2DetectorServer_virtual
PUBLIC GOTTHARD2D VIRTUAL STOP_SERVER
PUBLIC GOTTHARD2D VIRTUAL STOP_SERVER DEBUG1
)
target_link_libraries(gotthard2DetectorServer_virtual

175
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@@ -14,13 +14,33 @@
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
#define BASE_CONTROL (0x0000)
/* Acquisition? TODO */
#define BASE_ACQUISITION (0x0200)
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
/* ASIC Control */
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/asic/asic_ctrl.vhd
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/adif/adif_ctrl.vhd
/* Formatting of data core */
#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
/* Packetizer */
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
/* Flow control and status registers */
#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/f37608230b4721661f29aacc20124555705ee705/flow/flow_ctrl.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
@@ -30,6 +50,7 @@
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number register */
@@ -61,11 +82,6 @@
/* Status register */
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
#ifdef VIRTUAL
#define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#endif
/* Look at me read only register */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
@@ -88,43 +104,144 @@
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Pattern IO Control 64 bit register */
#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL)
#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
/** DTA Offset Register */
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* ASIC registers --------------------------------------------------*/
/* ASIC Config register */
#define ASIC_CONFIG_REG (0x00 * REG_OFFSET + BASE_ASIC)
#define ASIC_CONFIG_RUN_MODE_OFST (0)
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_GAIN_OFST (4)
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
/* ASIC Internal Frames Register */
#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_FRAMES_OFST (0)
#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
/* ASIC Period 64bit Register */
#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
/* ASIC Exptime 64bit Register */
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
#define PKT_CONFIG_NRXR_MAX_OFST (0)
#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
#define PKT_CONFIG_RXR_START_ID_OFST (8)
#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
/* Module Coordinates Register */
#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
#define COORD_ROW_OFST (0)
#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
#define COORD_COL_OFST (16)
#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
/* Module ID Register */
#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Flow control registers --------------------------------------------------*/
/* Flow status Register*/
#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
#define FLOW_STATUS_RUN_BUSY_OFST (0)
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_FIFO_FULL_OFST (5)
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_CSM_BUSY_OFST (17)
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Acquisition registers --------------------------------------------------*/
//TODO
/* Triggers left 64bit Register */
#define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION)
#define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION)
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x18 + BASE_ACQUISITION)
#define GET_FRAMES_MSB_REG (0x1C + BASE_ACQUISITION)
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Period left 64bit Register */
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
/* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x88 + BASE_ACQUISITION)
#define SET_DELAY_MSB_REG (0x8C + BASE_ACQUISITION)
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Cylces 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x90 + BASE_ACQUISITION)
#define SET_CYCLES_MSB_REG (0x94 + BASE_ACQUISITION)
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x98 + BASE_ACQUISITION)
#define SET_FRAMES_MSB_REG (0x9C + BASE_ACQUISITION)
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Period 64bit Write-register */
#define SET_PERIOD_LSB_REG (0xA0 + BASE_ACQUISITION)
#define SET_PERIOD_MSB_REG (0xA4 + BASE_ACQUISITION)
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Exptime 64bit Write-register */
#define SET_EXPTIME_LSB_REG (0xA8 + BASE_ACQUISITION)
#define SET_EXPTIME_MSB_REG (0xBC + BASE_ACQUISITION)
/* External Signal register */
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
/* Trigger Delay 64 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)

BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
View File

Binary file not shown.

701
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
View File

@@ -22,7 +22,9 @@
// Global variable from slsDetectorServer_funcs
extern int debugflag;
extern int checkModuleFlag;
extern udpStruct udpDetails;
extern const enum detectorType myDetectorType;
int initError = OK;
int initCheckDone = 0;
@@ -34,19 +36,22 @@ int virtual_status = 0;
int virtual_stop = 0;
#endif
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
enum detectorSettings thisSettings = UNINITIALIZED;
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {};
int highvoltage = 0;
int dacValues[NDAC] = {0};
int onChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
int defaultDacValues[NDAC] = {0};
int defaultOnChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
int injectedChannelsOffset = 0;
int injectedChannelsIncrement = 0;
int vetoReference[NCHIP][NCHAN];
uint8_t adcConfiguration[NCHIP][NADC];
int burstMode = 0;
int detPos[2] = {0, 0};
enum burstModeType burstType = INTERNAL;
int64_t exptime_ns = 0;
int64_t period_ns = 0;
int64_t nframes = 0;
int detPos[2] = {};
int isInitCheckDone() {
return initCheckDone;
@@ -72,6 +77,7 @@ void basictests() {
}
return;
#else
FILE_LOG(logINFOBLUE, ("************ Gotthard2 Server *********************\n"));
if (mapCSP0() == FAIL) {
strcpy(initErrorMessage,
"Could not map to memory. Dangerous to continue.\n");
@@ -97,7 +103,7 @@ void basictests() {
int64_t client_sw_apiversion = getClientServerAPIVersion();
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
FILE_LOG(logINFOBLUE, ("************ Gotthard2 Server *********************\n"
FILE_LOG(logINFOBLUE, ("*************************************************\n"
"Hardware Version:\t\t 0x%x\n"
"Detector IP Addr:\t\t 0x%x\n"
@@ -158,7 +164,6 @@ void basictests() {
return;
}
FILE_LOG(logINFO, ("Compatibility - success\n"));
#endif
}
@@ -166,7 +171,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type != GOTTHARD2){
FILE_LOG(logERROR, ("This is not a Gotthard2 Server (read %d, expected %d)\n", type, GOTTHARD2));
return FAIL;
@@ -340,11 +345,15 @@ void setupDetector() {
detPos[0] = 0;
detPos[1] = 0;
thisSettings = UNINITIALIZED;
highvoltage = 0;
injectedChannelsOffset = 0;
injectedChannelsIncrement = 0;
burstMode = 0;
burstType = INTERNAL;
exptime_ns = 0;
period_ns = 0;
nframes = 0;
{
int i, j;
for (i = 0; i < NUM_CLOCKS; ++i) {
@@ -352,12 +361,10 @@ void setupDetector() {
}
for (i = 0; i < NDAC; ++i) {
dacValues[i] = 0;
defaultDacValues[i] = 0;
}
for (i = 0; i < ONCHIP_NDAC; ++i) {
for (j = 0; j < NCHIP; ++j) {
onChipdacValues[i][j] = -1;
defaultOnChipdacValues[i][j] = -1;
}
}
for (i = 0; i < NCHIP; ++i) {
@@ -386,52 +393,68 @@ void setupDetector() {
// Default values
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
// also sets default dac and on chip dac values
// check module type attached if not in debug mode
{
int ret = checkDetectorType();
if (checkModuleFlag) {
switch (ret) {
case -1:
sprintf(initErrorMessage, "Could not get the module type attached.\n");
initError = FAIL;
FILE_LOG(logERROR, ("Aborting startup!\n\n", initErrorMessage));
return;
case -2:
sprintf(initErrorMessage, "No Module attached! Run server with -nomodule.\n");
initError = FAIL;
FILE_LOG(logERROR, ("Aborting startup!\n\n", initErrorMessage));
return;
case FAIL:
sprintf(initErrorMessage, "Wrong Module (Not Gotthard2) attached!\n");
initError = FAIL;
FILE_LOG(logERROR, ("Aborting startup!\n\n", initErrorMessage));
return;
default:
break;
}
} else {
FILE_LOG(logINFOBLUE, ("In No-Module mode: Ignoring module type. Continuing.\n"));
}
}
// power on chip
powerChip(1);
#ifndef VIRTUAL
// also sets default dac and on chip dac values
if (readConfigFile() == FAIL) {
return;
}
setBurstMode(1);
#endif
// set burst mode will take in burstType and also set it
burstType = DEFAULT_BURST_TYPE;
setBurstMode(DEFAULT_BURST_MODE);
setSettings(DEFAULT_SETTINGS);
// Initialization of acquistion parameters
setNumFrames(DEFAULT_NUM_FRAMES);
setNumTriggers(DEFAULT_NUM_CYCLES);
setExpTime(DEFAULT_EXPTIME);
setPeriod(DEFAULT_PERIOD);
setDelayAfterTrigger(DEFAULT_DELAY_AFTER_TRIGGER);
setTiming(DEFAULT_TIMING_MODE);
}
int setDefaultDacs() {
int ret = OK;
FILE_LOG(logINFOBLUE, ("Setting Default Dac values\n"));
{
int idac = 0;
for(idac = 0; idac < NDAC; ++idac) {
setDAC((enum DACINDEX)idac, defaultDacValues[idac], 0);
}
}
return ret;
}
int setDefaultOnChipDacs() {
int ret = OK;
FILE_LOG(logINFOBLUE, ("Setting Default On chip Dac values\n"));
{
int idac = 0, ichip = 0;
for(idac = 0; idac < ONCHIP_NDAC; ++idac) {
for(ichip = 0; ichip < NCHIP; ++ichip) {
setOnChipDAC((enum ONCHIP_DACINDEX)idac, ichip, defaultOnChipdacValues[idac][ichip]);
}
}
}
return ret;
}
int readConfigFile() {
if (initError == FAIL) {
return initError;
}
// inform FPGA that onchip dacs will be configured soon
FILE_LOG(logINFO, ("Setting configuration starting bit\n"));
bus_w(ASIC_CONFIG_REG, bus_r(ASIC_CONFIG_REG) | ASIC_CONFIG_RST_DAC_MSK);
FILE* fd = fopen(CONFIG_FILE, "r");
if(fd == NULL) {
sprintf(initErrorMessage, "Could not open on-board detector server config file [%s].\n", CONFIG_FILE);
@@ -649,7 +672,7 @@ int readConfigFile() {
int i = 0, j = 0;
for (i = 0; i < NCHIP; ++i) {
for (j = 0; j < NADC; ++j) {
FILE_LOG(logDEBUG1, ("adc read %d %d: 0x%02hhx\n", i, j, adcConfiguration[i][j]));
FILE_LOG(logDEBUG2, ("adc read %d %d: 0x%02hhx\n", i, j, adcConfiguration[i][j]));
}
}
}
@@ -659,10 +682,39 @@ int readConfigFile() {
FILE_LOG(logERROR, ("%s\n\n", initErrorMessage));
} else {
FILE_LOG(logINFOBLUE, ("Successfully read config file\n"));
// inform FPGA that onchip dacs will be configured soon
FILE_LOG(logINFO, ("Setting configuration done bit\n"));
bus_w(ASIC_CONFIG_REG, bus_r(ASIC_CONFIG_REG) | ASIC_CONFIG_DONE_MSK);
}
return initError;
}
/* firmware functions (resets) */
void cleanFifos() {
#ifdef VIRTUAL
return;
#endif
FILE_LOG(logINFO, ("Clearing Acquisition Fifos\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CLR_ACQSTN_FIFO_MSK);
}
void resetCore() {
#ifdef VIRTUAL
return;
#endif
FILE_LOG(logINFO, ("Resetting Core\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK);
}
void resetPeripheral() {
#ifdef VIRTUAL
return;
#endif
FILE_LOG(logINFO, ("Resetting Peripheral\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_PRPHRL_RST_MSK);
}
/* set parameters - dr, roi */
@@ -671,16 +723,16 @@ int setDynamicRange(int dr){
}
/* parameters */
/* parameters - timer */
void setNumFrames(int64_t val) {
if (val > 0) {
FILE_LOG(logINFO, ("Setting number of frames %lld\n", (long long int)val));
set64BitReg(val, SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
FILE_LOG(logINFO, ("Setting number of frames %lld [local]\n", (long long int)val));
nframes = val;
}
}
int64_t getNumFrames() {
return get64BitReg(SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
return nframes;
}
void setNumTriggers(int64_t val) {
@@ -699,21 +751,13 @@ int setExpTime(int64_t val) {
FILE_LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
return FAIL;
}
FILE_LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val));
val *= (1E-9 * READOUT_C0);
set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG);
// validate for tolerance
int64_t retval = getExpTime();
val /= (1E-9 * READOUT_C0);
if (val != retval) {
return FAIL;
}
FILE_LOG(logINFO, ("Setting exptime %lld ns [local]\n", (long long int)val));
exptime_ns = val;
return OK;
}
int64_t getExpTime() {
return get64BitReg(SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-9 * READOUT_C0);
return exptime_ns;
}
int setPeriod(int64_t val) {
@@ -721,21 +765,118 @@ int setPeriod(int64_t val) {
FILE_LOG(logERROR, ("Invalid period: %lld ns\n", (long long int)val));
return FAIL;
}
FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
val *= (1E-9 * SYSTEM_C0);
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
FILE_LOG(logINFO, ("Setting period %lld ns [local]\n", (long long int)val));
period_ns = val;
return OK;
}
int64_t getPeriod() {
return period_ns;
}
void setNumFramesBurst(int64_t val) {
FILE_LOG(logINFO, ("Setting number of frames %d [Burst mode]\n", (int)val));
bus_w(ASIC_INT_FRAMES_REG, bus_r(ASIC_INT_FRAMES_REG) &~ ASIC_INT_FRAMES_MSK);
bus_w(ASIC_INT_FRAMES_REG, bus_r(ASIC_INT_FRAMES_REG) | (((int)val << ASIC_INT_FRAMES_OFST) & ASIC_INT_FRAMES_MSK));
}
int64_t getNumFramesBurst() {
return ((bus_r(ASIC_INT_FRAMES_REG) & ASIC_INT_FRAMES_MSK) >> ASIC_INT_FRAMES_OFST);
}
void setNumFramesCont(int64_t val) {
FILE_LOG(logINFO, ("Setting number of frames %lld [Continuous mode]\n", (long long int)val));
set64BitReg(val, SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
}
int64_t getNumFramesCont() {
return get64BitReg(SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
}
int setExptimeBurst(int64_t val) {
FILE_LOG(logINFO, ("Setting exptime %lld ns [Burst mode]\n", (long long int)val));
return setExptimeBoth(val);
}
int setExptimeCont(int64_t val) {
FILE_LOG(logINFO, ("Setting exptime %lld ns [Continuous mode]\n", (long long int)val));
return setExptimeBoth(val);
}
int setExptimeBoth(int64_t val) {
val *= (1E-9 * clkFrequency[SYSTEM_C0]);
set64BitReg(val, ASIC_INT_EXPTIME_LSB_REG, ASIC_INT_EXPTIME_MSB_REG);
// validate for tolerance
int64_t retval = getPeriod();
val /= (1E-9 * SYSTEM_C0);
int64_t retval = getExptimeBoth();
val /= (1E-9 * clkFrequency[SYSTEM_C0]);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getPeriod() {
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * SYSTEM_C0);
int64_t getExptimeBoth() {
return get64BitReg(ASIC_INT_EXPTIME_LSB_REG, ASIC_INT_EXPTIME_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C0]);
}
int setPeriodBurst(int64_t val) {
FILE_LOG(logINFO, ("Setting period %lld ns [Burst mode]\n", (long long int)val));
val *= (1E-9 * clkFrequency[SYSTEM_C0]);
set64BitReg(val, ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG);
// validate for tolerance
int64_t retval = getPeriodBurst();
val /= (1E-9 * clkFrequency[SYSTEM_C0]);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getPeriodBurst() {
return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C0]);
}
int setPeriodCont(int64_t val) {
FILE_LOG(logINFO, ("Setting period %lld ns [Continuous mode]\n", (long long int)val));
val *= (1E-9 * FIXED_PLL_FREQUENCY);
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
// validate for tolerance
int64_t retval = getPeriodCont();
val /= (1E-9 * FIXED_PLL_FREQUENCY);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getPeriodCont() {
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
}
int setDelayAfterTrigger(int64_t val) {
if (val < 0) {
FILE_LOG(logERROR, ("Invalid delay after trigger: %lld ns\n", (long long int)val));
return FAIL;
}
FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
val *= (1E-9 * FIXED_PLL_FREQUENCY);
set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
// validate for tolerance
int64_t retval = getDelayAfterTrigger();
val /= (1E-9 * FIXED_PLL_FREQUENCY);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getNumFramesLeft() {
@@ -746,6 +887,88 @@ int64_t getNumTriggersLeft() {
return get64BitReg(GET_CYCLES_LSB_REG, GET_CYCLES_MSB_REG);
}
int64_t getDelayAfterTriggerLeft() {
return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getPeriodLeft() {
return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getFramesFromStart() {
return get64BitReg(FRAMES_FROM_START_LSB_REG, FRAMES_FROM_START_MSB_REG);
}
int64_t getActualTime() {
return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY * 2);
}
int64_t getMeasurementTime() {
return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
/* parameters - module, settings */
enum detectorSettings setSettings(enum detectorSettings sett){
if(sett == UNINITIALIZED)
return thisSettings;
// set settings
uint32_t addr = ASIC_CONFIG_REG;
uint32_t mask = ASIC_CONFIG_GAIN_MSK;
if(sett != GET_SETTINGS) {
switch (sett) {
case DYNAMICGAIN:
bus_w(addr, bus_r(addr) & ~mask);
bus_w(addr, bus_r(addr) | ASIC_CONFIG_DYNAMIC_GAIN_VAL);
FILE_LOG(logINFO, ("Set settings - Dyanmic Gain, val: 0x%x\n", bus_r(addr) & mask));
break;
case FIXGAIN1:
bus_w(addr, bus_r(addr) & ~mask);
bus_w(addr, bus_r(addr) | ASIC_CONFIG_FIX_GAIN_1_VAL);
FILE_LOG(logINFO, ("Set settings - Fix Gain 1, val: 0x%x\n", bus_r(addr) & mask));
break;
case FIXGAIN2:
bus_w(addr, bus_r(addr) & ~mask);
bus_w(addr, bus_r(addr) | ASIC_CONFIG_FIX_GAIN_2_VAL);
FILE_LOG(logINFO, ("Set settings - Fix Gain 2, val: 0x%x\n", bus_r(addr) & mask));
break;
default:
FILE_LOG(logERROR, ("This settings is not defined for this detector %d\n", (int)sett));
return -1;
}
thisSettings = sett;
}
return getSettings();
}
enum detectorSettings getSettings(){
uint32_t regval = bus_r(ASIC_CONFIG_REG);
uint32_t val = regval & ASIC_CONFIG_GAIN_MSK;
FILE_LOG(logDEBUG1, ("Getting Settings\n Reading val :0x%x\n", val));
switch(val) {
case ASIC_CONFIG_RESERVED_VAL:
case ASIC_CONFIG_DYNAMIC_GAIN_VAL:
thisSettings = DYNAMICGAIN;
FILE_LOG(logDEBUG1, ("Settings read: Dynamic Gain. val: 0x%x\n", val));
break;
case ASIC_CONFIG_FIX_GAIN_1_VAL:
thisSettings = FIXGAIN1;
FILE_LOG(logDEBUG1, ("Settings read: Fix Gain 1. val: 0x%x\n", val));
break;
case ASIC_CONFIG_FIX_GAIN_2_VAL:
thisSettings = FIXGAIN2;
FILE_LOG(logDEBUG1, ("Settings read: Fix Gain 2. val: 0x%x\n", val));
break;
default:
thisSettings = UNDEFINED;
FILE_LOG(logERROR, ("Settings read: Undefined. val: 0x%x\n", val));
}
return thisSettings;
}
/* parameters - dac, hv */
@@ -866,6 +1089,31 @@ int setHighVoltage(int val){
return highvoltage;
}
/* parameters - timing */
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch(arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
break;
case TRIGGER_EXPOSURE:
FILE_LOG(logINFO, ("Set Timing: Trigger\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
break;
default:
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
return;
}
}
}
enum timingMode getTiming() {
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
}
int configureMAC() {
@@ -888,7 +1136,7 @@ int configureMAC() {
return OK;
#endif
FILE_LOG(logINFOBLUE, ("Configuring MAC\n"));
FILE_LOG(logINFO, ("\tSource IP : %d.%d.%d.%d \t\t(0x%08x)\n",
(srcip>>24)&0xff,(srcip>>16)&0xff,(srcip>>8)&0xff,(srcip)&0xff, srcip));
FILE_LOG(logINFO, ("\tSource MAC : %02x:%02x:%02x:%02x:%02x:%02x \t(0x%010llx)\n",
@@ -951,9 +1199,9 @@ int configureMAC() {
calcChecksum(udp);
//TODO?
//cleanFifos();
//resetCore();
cleanFifos();
resetCore();
//alignDeserializer();
return OK;
}
@@ -989,8 +1237,86 @@ void calcChecksum(udp_header* udp) {
udp->ip_checksum = checksum;
}
int setDetectorPosition(int pos[]) {
memcpy(detPos, pos, sizeof(detPos));
uint32_t addr = COORD_0_REG;
int value = 0;
int valueRead = 0;
int ret = OK;
// row
value = detPos[X];
bus_w(addr, (bus_r(addr) &~COORD_ROW_MSK) | ((value << COORD_ROW_OFST) & COORD_ROW_MSK));
valueRead = ((bus_r(addr) & COORD_ROW_MSK) >> COORD_ROW_OFST);
if (valueRead != value) {
FILE_LOG(logERROR, ("Could not set row. Set %d, read %d\n", value, valueRead));
ret = FAIL;
}
// col
value = detPos[Y];
bus_w(addr, (bus_r(addr) &~COORD_COL_MSK) | ((value << COORD_COL_OFST) & COORD_COL_MSK));
valueRead = ((bus_r(addr) & COORD_COL_MSK) >> COORD_COL_OFST);
if (valueRead != value) {
FILE_LOG(logERROR, ("Could not set column. Set %d, read %d\n", value, valueRead));
ret = FAIL;
}
if (ret == OK) {
FILE_LOG(logINFO, ("\tPosition set to [%d, %d]\n", detPos[X], detPos[Y]));
}
return ret;
}
int* getDetectorPosition() {
return detPos;
}
// Detector Specific
int checkDetectorType() {
FILE_LOG(logINFO, ("Checking type of module\n"));
FILE* fd = fopen(TYPE_FILE_NAME, "r");
if (fd == NULL) {
FILE_LOG(logERROR, ("Could not open file %s to get type of the module attached\n", TYPE_FILE_NAME));
return -1;
}
char buffer[MAX_STR_LENGTH];
memset(buffer, 0, sizeof(buffer));
fread (buffer, MAX_STR_LENGTH, sizeof(char), fd);
if (strlen(buffer) == 0) {
FILE_LOG(logERROR, ("Could not read file %s to get type of the module attached\n", TYPE_FILE_NAME));
return -1;
}
int type = atoi(buffer);
if (type > TYPE_NO_MODULE_STARTING_VAL) {
FILE_LOG(logERROR, ("No Module attached! Expected %d for Gotthard2, got %d\n", TYPE_GOTTHARD2_MODULE_VAL, type));
return -2;
}
if (abs(type - TYPE_GOTTHARD2_MODULE_VAL) > TYPE_TOLERANCE) {
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Gotthard2, got %d\n", TYPE_GOTTHARD2_MODULE_VAL, type));
return FAIL;
}
return OK;
}
int powerChip (int on){
if(on != -1){
if(on){
FILE_LOG(logINFO, ("Powering chip: on\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_PWR_CHIP_MSK);
}
else{
FILE_LOG(logINFO, ("Powering chip: off\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_PWR_CHIP_MSK);
}
}
return ((bus_r(CONTROL_REG) & CONTROL_PWR_CHIP_MSK) >> CONTROL_PWR_CHIP_OFST);
}
int setPhase(enum CLKINDEX ind, int val, int degrees) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
@@ -1030,8 +1356,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
clkPhase[ind] = valShift;
@@ -1103,7 +1429,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
@@ -1121,7 +1447,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
char* clock_names[] = {CLK_NAMES};
int vcofreq = getVCOFrequency(ind);
int currentdiv = vcofreq / clkFrequency[ind];
int currentdiv = vcofreq / (int)clkFrequency[ind];
int newfreq = vcofreq / val;
FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
@@ -1137,8 +1463,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
// Calculate and set output frequency
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
clkFrequency[ind] = newfreq;
FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
@@ -1173,7 +1499,7 @@ int getClockDivider(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
return -1;
}
return (getVCOFrequency(ind) / clkFrequency[ind]);
return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
}
int setInjectChannel(int offset, int increment) {
@@ -1244,11 +1570,11 @@ int setVetoPhoton(int chipIndex, int gainIndex, int* values) {
FILE_LOG(logERROR, ("Unknown gain index %d\n", gainIndex));
return FAIL;
}
FILE_LOG(logDEBUG1, ("Adding gain bits\n"));
FILE_LOG(logDEBUG2, ("Adding gain bits\n"));
int i = 0;
for (i = 0; i < NCHAN; ++i) {
values[i] |= gainValue;
FILE_LOG(logDEBUG1, ("Value %d: 0x%x\n", i, values[i]));
FILE_LOG(logDEBUG2, ("Value %d: 0x%x\n", i, values[i]));
}
}
@@ -1426,6 +1752,10 @@ int configureADC() {
int setBurstMode(int burst) {
FILE_LOG(logINFO, ("Setting %s Mode\n", burst == 1 ? "Burst" : "Continuous"));
burstMode = burst;
setBurstType(burstType);
FILE_LOG(logINFO, ("\tSetting %s Mode in Chip\n", burst == 1 ? "Burst" : "Continuous"));
int value = burst ? ASIC_GLOBAL_BURST_VALUE : ASIC_GLOBAL_CONT_VALUE;
const int padding = 6; // due to address (4) to make it byte aligned
@@ -1464,28 +1794,123 @@ int setBurstMode(int burst) {
return FAIL;
}
burstMode = burst;
return configureADC();
}
int getBurstMode() {
return burstMode;
uint32_t addr = ASIC_CONFIG_REG;
int runmode = bus_r (addr) & ASIC_CONFIG_RUN_MODE_MSK;
switch (runmode) {
case ASIC_CONFIG_RUN_MODE_INT_BURST_VAL:
case ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL:
return 1;
default:
return 0;
}
}
void setBurstType(enum burstModeType val) {
uint32_t addr = ASIC_CONFIG_REG;
uint32_t runmode = ASIC_CONFIG_RUN_MODE_CONT_VAL;
if (burstMode) {
switch (val) {
case INTERNAL:
runmode = ASIC_CONFIG_RUN_MODE_INT_BURST_VAL;
break;
case EXTERNAL:
runmode = ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL;
break;
default:
FILE_LOG(logERROR, ("Unknown burst type %d\n", val));
return;
}
FILE_LOG(logDEBUG1, ("Run mode: %d\n", runmode));
bus_w(addr, bus_r(addr) &~ ASIC_CONFIG_RUN_MODE_MSK);
bus_w(addr, bus_r(addr) | ((runmode << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK));
}
}
enum burstModeType getBurstType() {
uint32_t addr = ASIC_CONFIG_REG;
int runmode = bus_r (addr) & ASIC_CONFIG_RUN_MODE_MSK;
switch (runmode) {
case ASIC_CONFIG_RUN_MODE_INT_BURST_VAL:
return INTERNAL;
case ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL:
return EXTERNAL;
default:
FILE_LOG(logERROR, ("Unknown burst type read from FPGA: %d\n", runmode));
return -1;
}
}
/* aquisition */
int setDetectorPosition(int pos[]) {
memcpy(detPos, pos, sizeof(detPos));
int updateAcquisitionRegisters(char* mess) {
// burst mode
if (burstMode) {
// validate #frames in burst mode
if (nframes > MAX_FRAMES_IN_BURST_MODE) {
sprintf(mess, "Could not start acquisition because number of frames %lld must be <= %d in burst mode.\n", (long long unsigned int)nframes, MAX_FRAMES_IN_BURST_MODE);
FILE_LOG(logERROR,(mess));
return FAIL;
}
setNumFramesBurst(nframes);
// exptime
if (setExptimeBurst(exptime_ns) == FAIL) {
sprintf(mess, "Could not start acquisition because exptime could not be set in burst mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)exptime_ns, getExptimeBoth());
FILE_LOG(logERROR,(mess));
return FAIL;
}
// period
if (setPeriodBurst(period_ns) == FAIL) {
sprintf(mess, "Could not start acquisition because period could not be set in burst mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)period_ns, getPeriodBurst());
FILE_LOG(logERROR,(mess));
return FAIL;
}
// set continuous values to default (exptime same register)
FILE_LOG(logINFO, ("Setting continuous mode registers to defaults\n"));
// frames
setNumFramesCont(1);
// period
if (setPeriodCont(0) == FAIL) {
sprintf(mess, "Could not start acquisition because period could not be set in continuous mode. Set 0 ns, got %lld ns.\n", getPeriodCont());
FILE_LOG(logERROR,(mess));
return FAIL;
}
}
// continuous
else {
// frames
setNumFramesCont(nframes);
// exptime
if (setExptimeCont(exptime_ns) == FAIL) {
sprintf(mess, "Could not start acquisition because exptime could not be set in continuous mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)exptime_ns, getExptimeBoth());
FILE_LOG(logERROR,(mess));
return FAIL;
}
// period
if (setPeriodCont(period_ns) == FAIL) {
sprintf(mess, "Could not start acquisition because period could not be set in continuous mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)period_ns, getPeriodCont());
FILE_LOG(logERROR,(mess));
return FAIL;
}
// set burst values to default (exptime same register)
FILE_LOG(logINFO, ("Setting burst mode registers to defaults\n"));
setNumFramesBurst(1);
// period
if (setPeriodBurst(0) == FAIL) {
sprintf(mess, "Could not start acquisition because period could not be set in burst mode. Set 0 ns, got %lld ns.\n", getPeriodBurst());
FILE_LOG(logERROR,(mess));
return FAIL;
}
}
return OK;
}
int* getDetectorPosition() {
return detPos;
}
int startStateMachine(){
if (burstMode && getNumFrames() > MAX_FRAMES_IN_BURST_MODE) {
return FAIL;
}
#ifdef VIRTUAL
// create udp socket
if(createUDPSocket(0) != OK) {
@@ -1503,6 +1928,13 @@ int startStateMachine(){
FILE_LOG(logINFOGREEN, ("Virtual Acquisition started\n"));
return OK;
#endif
FILE_LOG(logINFOBLUE, ("Starting State Machine\n"));
cleanFifos();
//start state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK);
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
return OK;
}
@@ -1513,6 +1945,8 @@ void* start_timer(void* arg) {
int numFrames = (getNumFrames() *
getNumTriggers() );
int64_t exp_ns = getExpTime();
int datasize = 2560;
int packetsize = datasize + sizeof(sls_detector_header);
int frameNr = 0;
@@ -1530,6 +1964,22 @@ void* start_timer(void* arg) {
usleep(exp_ns / 1000);
clock_gettime(CLOCK_REALTIME, &end);
char packetData[packetsize];
memset(packetData, 0, packetsize);
// set header
sls_detector_header* header = (sls_detector_header*)(packetData);
header->frameNumber = frameNr;
header->packetNumber = 0;
header->modId = 0;
header->row = detPos[X];
header->column = detPos[Y];
header->detType = (uint16_t)myDetectorType;
header->version = SLS_DETECTOR_HEADER_VERSION - 1;
// send 1 packet = 1 frame
sendUDPPacket(0, packetData, packetsize);
FILE_LOG(logINFO, ("Sent frame: %d\n", frameNr));
// calculate time left in period
int64_t time_ns = ((end.tv_sec - begin.tv_sec) * 1E9 +
(end.tv_nsec - begin.tv_nsec));
@@ -1544,6 +1994,7 @@ void* start_timer(void* arg) {
// set register frames left
}
closeUDPSocket(0);
// set status to idle
virtual_status = 0;
FILE_LOG(logINFOBLUE, ("Finished Acquiring\n"));
@@ -1558,6 +2009,9 @@ int stopStateMachine(){
virtual_stop = 0;
return OK;
#endif
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
return OK;
}
@@ -1571,10 +2025,50 @@ enum runStatus getRunStatus(){
return RUNNING;
}
#endif
return IDLE;
FILE_LOG(logDEBUG1, ("Getting status\n"));
uint32_t retval = bus_r(FLOW_STATUS_REG);
FILE_LOG(logINFO, ("Status Register: %08x\n",retval));
enum runStatus s;
//running
if (retval & FLOW_STATUS_RUN_BUSY_MSK) {
if (retval & FLOW_STATUS_WAIT_FOR_TRGGR_MSK) {
FILE_LOG(logINFOBLUE, ("Status: WAITING\n"));
s = WAITING;
} else {
if (retval & FLOW_STATUS_DLY_BFRE_TRGGR_MSK) {
FILE_LOG(logINFO, ("Status: Delay before Trigger\n"));
} else if (retval & FLOW_STATUS_DLY_AFTR_TRGGR_MSK) {
FILE_LOG(logINFO, ("Status: Delay after Trigger\n"));
}
FILE_LOG(logINFOBLUE, ("Status: RUNNING\n"));
s = RUNNING;
}
}
//not running
else {
// stopped or error
if (retval & FLOW_STATUS_FIFO_FULL_MSK) {
FILE_LOG(logINFOBLUE, ("Status: STOPPED\n")); //FIFO FULL??
s = STOPPED;
} else if (retval & FLOW_STATUS_CSM_BUSY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: READ MACHINE BUSY\n"));
s = TRANSMITTING;
} else if (!retval) {
FILE_LOG(logINFOBLUE, ("Status: IDLE\n"));
s = IDLE;
} else {
FILE_LOG(logERROR, ("Status: Unknown status %08x\n", retval));
s = ERROR;
}
}
return s;
}
void readFrame(int *ret, char *mess){
void readFrame(int *ret, char *mess) {
// wait for status to be done
while(runBusy()){
usleep(500);
@@ -1583,29 +2077,36 @@ void readFrame(int *ret, char *mess){
FILE_LOG(logINFOGREEN, ("acquisition successfully finished\n"));
return;
#endif
*ret = (int)OK;
// frames left to give status
int64_t retval = getNumFramesLeft() + 1;
if ( retval > 0) {
FILE_LOG(logERROR, ("No data and run stopped: %lld frames left\n",(long long int)retval));
} else {
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
}
u_int32_t runBusy() {
#ifdef VIRTUAL
return virtual_status;
#endif
#ifdef VIRTUAL
u_int32_t s = (bus_r(STATUS_REG) & RUN_BUSY_MSK);
FILE_LOG(logDEBUG1, ("Status Register: %08x\n", s));
u_int32_t s = (bus_r(FLOW_STATUS_REG) & FLOW_STATUS_RUN_BUSY_MSK);
//FILE_LOG(logDEBUG1, ("Status Register: %08x\n", s));
return s;
#endif
return -1;
}
/* common */
int calculateDataBytes(){
int calculateDataBytes() {
return getTotalNumberOfChannels() * DYNAMIC_RANGE;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}

13
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@@ -17,22 +17,30 @@
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
#define ONCHIP_DAC_DRIVER_FILE_NAME ("/etc/devlinks/chipdac")
#define TYPE_FILE_NAME ("/etc/devlinks/type")
#define CONFIG_FILE ("config.txt")
#define DAC_MAX_MV (2048)
#define ONCHIP_DAC_MAX_VAL (0x3FF)
#define ADU_MAX_VAL (0xFFF)
#define ADU_MAX_BITS (12)
#define MAX_FRAMES_IN_BURST_MODE (2720)
#define TYPE_GOTTHARD2_MODULE_VAL (512)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
/** Default Parameters */
#define DEFAULT_BURST_MODE (1)
#define DEFAULT_BURST_TYPE (INTERNAL)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (288888896) // rdo_x2_clk, 288 MHz
#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
@@ -40,6 +48,7 @@
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // Hz
#define SYSTEM_PLL_VCO_FREQ_HZ (722222240) // Hz

BIN
slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServer_developer
View File

Binary file not shown.

10
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
View File

@@ -30,10 +30,10 @@ int virtual_status = 0;
int virtual_stop = 0;
int highvoltage = 0;
#endif
int detPos[2] = {0, 0};
int detPos[2] = {};
int detectorFirstServer = 1;
int dacValues[NDAC] = {0};
int dacValues[NDAC] = {};
enum detectorSettings thisSettings = UNINITIALIZED;
enum externalSignalFlag signalMode = 0;
@@ -128,7 +128,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type == DETECTOR_TYPE_MOENCH_VAL){
FILE_LOG(logERROR, ("This is not a Gotthard Server (read %d, expected ?)\n", type));
return FAIL;
@@ -1180,7 +1180,7 @@ void setTiming( enum timingMode arg){
u_int32_t addr = EXT_SIGNAL_REG;
if (arg != GET_TIMING_MODE){
switch((int)arg){
switch(arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(addr, EXT_SIGNAL_OFF_VAL);
@@ -1680,7 +1680,7 @@ int calculateDataBytes(){
return DATA_BYTES;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}

BIN
slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
View File

Binary file not shown.

18
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
View File

@@ -24,6 +24,7 @@
// Global variable from slsDetectorServer_funcs
extern int debugflag;
extern udpStruct udpDetails;
extern const enum detectorType myDetectorType;
int initError = OK;
int initCheckDone = 0;
@@ -37,9 +38,9 @@ int virtual_stop = 0;
enum detectorSettings thisSettings = UNINITIALIZED;
int highvoltage = 0;
int dacValues[NDAC] = {0};
int dacValues[NDAC] = {};
int adcPhase = 0;
int detPos[4] = {0, 0, 0, 0};
int detPos[4] = {};
int numUDPInterfaces = 1;
@@ -170,7 +171,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type != JUNGFRAU){
FILE_LOG(logERROR, ("This is not a Jungfrau Server (read %d, expected %d)\n", type, JUNGFRAU));
return FAIL;
@@ -920,7 +921,7 @@ int setHighVoltage(int val){
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch((int)arg){
switch(arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
@@ -1667,7 +1668,7 @@ void* start_timer(void* arg) {
usleep(exp_us);
const int size = datasize + 112;
const int size = datasize + sizeof(sls_detector_header);
char packetData[size];
memset(packetData, 0, sizeof(sls_detector_header));
@@ -1679,6 +1680,11 @@ void* start_timer(void* arg) {
sls_detector_header* header = (sls_detector_header*)(packetData);
header->frameNumber = frameNr;
header->packetNumber = i;
header->modId = 0;
header->row = detPos[X];
header->column = detPos[Y];
header->detType = (uint16_t)myDetectorType;
header->version = SLS_DETECTOR_HEADER_VERSION - 1;
// fill data
memcpy(packetData + sizeof(sls_detector_header), imageData + srcOffset, datasize);
srcOffset += datasize;
@@ -1826,7 +1832,7 @@ int calculateDataBytes(){
return DATA_BYTES;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}

13
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@@ -4,10 +4,13 @@
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
@@ -160,15 +163,15 @@
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (0)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (0)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (0)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (0)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (0)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
View File

Binary file not shown.

50
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@@ -33,12 +33,12 @@ int virtual_status = 0;
int virtual_stop = 0;
#endif
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {};
int highvoltage = 0;
int dacValues[NDAC] = {0};
int detPos[2] = {0, 0};
int detPos[2] = {};
uint32_t countermask = 0; // will be removed later when in firmware converted to mask
int isInitCheckDone() {
@@ -85,13 +85,10 @@ void basictests() {
uint64_t macadd = getDetectorMAC();
int64_t fwversion = getFirmwareVersion();
int64_t swversion = getServerVersion();
int64_t sw_fw_apiversion = 0;
int64_t sw_fw_apiversion = getFirmwareAPIVersion();;
int64_t client_sw_apiversion = getClientServerAPIVersion();
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
sw_fw_apiversion = getFirmwareAPIVersion();
FILE_LOG(logINFOBLUE, ("*************************************************\n"
"Hardware Version:\t\t 0x%x\n"
@@ -162,7 +159,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type != MYTHEN3){
FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
return FAIL;
@@ -610,7 +607,6 @@ int setDelayAfterTrigger(int64_t val) {
int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getNumFramesLeft() {
@@ -708,7 +704,7 @@ int setHighVoltage(int val){
/* parameters - timing */
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch((int)arg){
switch (arg) {
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
@@ -719,7 +715,6 @@ void setTiming( enum timingMode arg){
break;
default:
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
return;
}
}
}
@@ -727,7 +722,7 @@ void setTiming( enum timingMode arg){
enum timingMode getTiming() {
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
return AUTO_TIMING;
}
@@ -1143,7 +1138,7 @@ int checkDetectorType() {
}
if (abs(type - TYPE_MYTHEN3_MODULE_VAL) > TYPE_TOLERANCE) {
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
return FAIL;
}
return OK;
@@ -1204,8 +1199,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
clkPhase[ind] = valShift;
@@ -1277,7 +1272,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
@@ -1295,7 +1290,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
char* clock_names[] = {CLK_NAMES};
int vcofreq = getVCOFrequency(ind);
int currentdiv = vcofreq / clkFrequency[ind];
int currentdiv = vcofreq / (int)clkFrequency[ind];
int newfreq = vcofreq / val;
FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
@@ -1310,8 +1305,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
// Calculate and set output frequency
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
clkFrequency[ind] = newfreq;
FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
@@ -1345,7 +1340,7 @@ int getClockDivider(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
return -1;
}
return (getVCOFrequency(ind) / clkFrequency[ind]);
return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
}
/* aquisition */
@@ -1482,7 +1477,7 @@ int stopStateMachine(){
#endif
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
return OK;
}
@@ -1539,7 +1534,7 @@ enum runStatus getRunStatus(){
return s;
}
void readFrame(int *ret, char *mess){
void readFrame(int *ret, char *mess) {
// wait for status to be done
while(runBusy()){
usleep(500);
@@ -1559,7 +1554,6 @@ void readFrame(int *ret, char *mess){
} else {
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
}
u_int32_t runBusy() {
@@ -1573,11 +1567,11 @@ u_int32_t runBusy() {
/* common */
int calculateDataBytes(){
int calculateDataBytes() {
return 0;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}

4
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@@ -2,7 +2,6 @@
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN 0x190000
#define MIN_REQRD_VRSN_T_RD_API 0x190000
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@@ -46,7 +45,6 @@
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define WAIT_TIME_US_STP_ACQ (100)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
@@ -99,4 +97,4 @@ typedef struct udp_header_struct {
uint16_t udp_destport;
} udp_header;
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define PACKETS_PER_FRAME (2)
#define PACKETS_PER_FRAME (2)

45
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
View File

@@ -84,11 +84,10 @@ int updateDatabytesandAllocateRAM();
void updateDataBytes();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || GOTTHARD2D
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D)
int setDefaultDacs();
#endif
#ifdef GOTTHARD2D
int setDefaultOnChipDacs();
int readConfigFile();
#endif
@@ -101,13 +100,13 @@ int readRegister(uint32_t offset, uint32_t* retval);
uint32_t writeRegister16And32(uint32_t offset, uint32_t data); //FIXME its not there in ctb or moench?
uint32_t readRegister16And32(uint32_t offset);
#else
extern u_int32_t writeRegister(u_int32_t offset, u_int32_t data); // blackfin.h
extern u_int32_t readRegister(u_int32_t offset); // blackfin.h
extern u_int32_t writeRegister(u_int32_t offset, u_int32_t data); // blackfin.h or nios.h
extern u_int32_t readRegister(u_int32_t offset); // blackfin.h or nios.h
#endif
// firmware functions (resets)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
@@ -178,6 +177,20 @@ int setExpTime(int64_t val);
int64_t getExpTime();
int setPeriod(int64_t val);
int64_t getPeriod();
#ifdef GOTTHARD2D
void setNumFramesBurst(int64_t val);
int64_t getNumFramesBurst();
void setNumFramesCont(int64_t val);
int64_t getNumFramesCont();
int setExptimeBurst(int64_t val);
int setExptimeCont(int64_t val);
int setExptimeBoth(int64_t val);
int64_t getExptimeBoth();
int setPeriodBurst(int64_t val);
int64_t getPeriodBurst();
int setPeriodCont(int64_t val);
int64_t getPeriodCont();
#endif
#ifdef EIGERD
int setSubExpTime(int64_t val);
int64_t getSubExpTime();
@@ -203,22 +216,18 @@ void setCounterMask(uint32_t arg);
uint32_t getCounterMask();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getNumFramesLeft();
int64_t getNumTriggersLeft();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
int64_t getDelayAfterTriggerLeft();
int64_t getPeriodLeft();
#endif
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getFramesFromStart();
int64_t getActualTime();
int64_t getMeasurementTime();
@@ -230,9 +239,11 @@ int64_t getMeasurementTime();
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char* mess);
int getModule(sls_detector_module *myMod);
#endif
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D))
enum detectorSettings setSettings(enum detectorSettings sett);
#endif
#if !defined(MYTHEN3D) && !defined(GOTTHARD2D)
#if !defined(MYTHEN3D)
enum detectorSettings getSettings();
#endif
@@ -293,10 +304,8 @@ int setHighVoltage(int val);
// parameters - timing, extsig
#if !defined(GOTTHARD2D)
void setTiming( enum timingMode arg);
enum timingMode getTiming();
#endif
#ifdef GOTTHARDD
void setExtSignal(enum externalSignalFlag mode);
int getExtSignal();
@@ -324,7 +333,6 @@ int getAdcConfigured();
int configureMAC();
int setDetectorPosition(int pos[]);
int* getDetectorPosition();
int isConfigurable();
#ifdef EIGERD
@@ -447,6 +455,8 @@ int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
#elif GOTTHARD2D
int checkDetectorType();
int powerChip (int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
@@ -466,6 +476,8 @@ int configureSingleADCDriver(int chipIndex);
int configureADC();
int setBurstMode(int burst);
int getBurstMode();
void setBurstType(enum burstModeType val);
enum burstModeType getBurstType();
#endif
@@ -489,6 +501,9 @@ int setTransmissionDelayRight(int value);
// aquisition
#ifdef GOTTHARD2D
int updateAcquisitionRegisters(char* mess);
#endif
#ifdef EIGERD
int prepareAcquisition();
#endif

6
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h
View File

@@ -199,10 +199,12 @@ int set_inject_channel(int);
int get_inject_channel(int);
int set_veto_photon(int);
int get_veto_photon(int);
int set_veto_refernce(int);
int set_veto_reference(int);
int get_burst_mode(int);
int set_burst_mode(int);
int set_adc_enable_mask_10g(int);
int get_adc_enable_mask_10g(int);
int set_counter_mask(int);
int get_counter_mask(int);
int get_counter_mask(int);
int set_burst_type(int);
int get_burst_type(int);

6
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c
View File

@@ -87,13 +87,9 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex) {
void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
#ifdef MYTHEN3D
FILE_LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
#else
FILE_LOG(logWARNING, ("Resetting PLL %d not implemented!\n", pllIndex));
#endif
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}

3
slsDetectorServers/slsDetectorServer/src/ASIC_Driver.c
View File

@@ -38,6 +38,9 @@ int ASIC_Driver_Set (int index, int length, char* buffer) {
FILE_LOG(logDEBUG1, ("\t]\n"));
}
#ifdef VIRTUAL
return OK;
#endif
int fd=open(fname, O_RDWR);
if (fd == -1) {
FILE_LOG(logERROR, ("Could not open file %s for writing to control ASIC (%d)\n", fname, index));

10
slsDetectorServers/slsDetectorServer/src/slsDetectorServer.c
View File

@@ -19,6 +19,8 @@ extern int ret;
// Global variables from slsDetectorServer_funcs
extern int sockfd;
extern int debugflag;
extern int checkModuleFlag;
// Global variables from slsDetectorFunctionList
#ifdef GOTTHARDD
@@ -67,7 +69,11 @@ int main(int argc, char *argv[]){
FILE_LOG(logINFO, ("Detected developer mode\n"));
debugflag = 1;
}
else if(!strcasecmp(argv[i],"--port")){
else if(!strcasecmp(argv[i],"-nomodule")){
FILE_LOG(logINFO, ("Detected No Module mode\n"));
checkModuleFlag = 0;
}
else if(!strcasecmp(argv[i],"-port")){
if ((i + 1) >= argc) {
FILE_LOG(logERROR, ("no port value given. Exiting.\n"));
return -1;
@@ -105,7 +111,7 @@ int main(int argc, char *argv[]){
int i;
for (i = 0; i < argc; ++i)
sprintf(cmd, "%s %s", cmd, argv[i]);
sprintf(cmd,"%s -stopserver --port %d &", cmd, portno + 1);
sprintf(cmd,"%s -stopserver -port %d &", cmd, portno + 1);
FILE_LOG(logDEBUG1, ("Command to start stop server:%s\n", cmd));
system(cmd);
}

148
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@@ -39,6 +39,7 @@ extern char mess[MAX_STR_LENGTH];
// Variables that will be exported
int sockfd = 0;
int debugflag = 0;
int checkModuleFlag = 1;
udpStruct udpDetails = {32410, 32411, 50001, 50002, 0, 0, 0, 0, 0, 0, 0, 0};
int configured = FAIL;
char configureMessage[MAX_STR_LENGTH]="udp parameters not configured yet";
@@ -307,6 +308,8 @@ const char* getFunctionName(enum detFuncs func) {
case F_GET_ADC_ENABLE_MASK_10G: return "F_GET_ADC_ENABLE_MASK_10G";
case F_SET_COUNTER_MASK: return "F_SET_COUNTER_MASK";
case F_GET_COUNTER_MASK: return "F_GET_COUNTER_MASK";
case F_SET_BURST_TYPE: return "F_SET_BURST_TYPE";
case F_GET_BURST_TYPE: return "F_GET_BURST_TYPE";
default: return "Unknown Function";
}
@@ -484,13 +487,15 @@ void function_table() {
flist[F_GET_INJECT_CHANNEL] = &get_inject_channel;
flist[F_SET_VETO_PHOTON] = &set_veto_photon;
flist[F_GET_VETO_PHOTON] = &get_veto_photon;
flist[F_SET_VETO_REFERENCE] = &set_veto_refernce;
flist[F_SET_VETO_REFERENCE] = &set_veto_reference;
flist[F_GET_BURST_MODE] = &get_burst_mode;
flist[F_SET_BURST_MODE] = &set_burst_mode;
flist[F_SET_ADC_ENABLE_MASK_10G] = &set_adc_enable_mask_10g;
flist[F_GET_ADC_ENABLE_MASK_10G] = &get_adc_enable_mask_10g;
flist[F_SET_COUNTER_MASK] = &set_counter_mask;
flist[F_GET_COUNTER_MASK] = &get_counter_mask;
flist[F_SET_BURST_TYPE] = &set_burst_type;
flist[F_GET_BURST_TYPE] = &get_burst_type;
// check
if (NUM_DET_FUNCTIONS >= RECEIVER_ENUM_START) {
@@ -685,10 +690,6 @@ int set_timing_mode(int file_des) {
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Setting external communication mode to %d\n", arg));
#ifdef GOTTHARD2D
functionNotImplemented();
#else
// set
if ((arg != GET_TIMING_MODE) && (Server_VerifyLock() == OK)) {
switch (arg) {
@@ -709,7 +710,6 @@ int set_timing_mode(int file_des) {
retval = getTiming();
validate((int)arg, (int)retval, "set timing mode", DEC);
FILE_LOG(logDEBUG1, ("Timing Mode: %d\n",retval));
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
@@ -1658,7 +1658,7 @@ int set_settings(int file_des) {
if (receiveData(file_des, &isett, sizeof(isett), INT32) < 0)
return printSocketReadError();
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
functionNotImplemented();
#else
FILE_LOG(logDEBUG1, ("Setting settings %d\n", isett));
@@ -1682,12 +1682,16 @@ int set_settings(int file_des) {
case LOWGAIN:
case MEDIUMGAIN:
case VERYHIGHGAIN:
#elif GOTTHARD2D
case DYNAMICGAIN:
case FIXGAIN1:
case FIXGAIN2:
#endif
break;
default:
if (myDetectorType == EIGER) {
ret = FAIL;
sprintf(mess, "Cannot set settings via SET_SETTINGS, use SET_MODULE\n");
sprintf(mess, "Cannot set settings via SET_SETTINGS, use SET_MODULE (set threshold)\n");
FILE_LOG(logERROR,(mess));
} else
modeNotImplemented("Settings Index", (int)isett);
@@ -1700,6 +1704,7 @@ int set_settings(int file_des) {
FILE_LOG(logDEBUG1, ("Settings: %d\n", retval));
validate((int)isett, (int)retval, "set settings", DEC);
#if defined(JUNGFRAUD) || defined (GOTTHARDD)
// gotthard2 does not set default dacs
if (ret == OK && isett >= 0) {
ret = setDefaultDacs();
if (ret == FAIL) {
@@ -1782,6 +1787,12 @@ int start_acquisition(int file_des) {
FILE_LOG(logERROR,(mess));
}
else
#endif
#ifdef GOTTHARD2D
if (updateAcquisitionRegisters(mess) == FAIL) {
ret = FAIL;
}
else
#endif
if (configured == FAIL) {
ret = FAIL;
@@ -1792,12 +1803,8 @@ int start_acquisition(int file_des) {
if (ret == FAIL) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(VIRTUAL)
sprintf(mess, "Could not start acquisition. Could not create udp socket in server. Check udp_dstip & udp_dstport.\n");
#else
#if defined(GOTTHARD2D)
sprintf(mess, "Could not start acquisition due to #frames > %d in burst mode\n", MAX_FRAMES_IN_BURST_MODE);
#else
sprintf(mess, "Could not start acquisition\n");
#endif
#endif
FILE_LOG(logERROR,(mess));
}
@@ -1916,6 +1923,12 @@ int start_and_read_all(int file_des) {
FILE_LOG(logERROR,(mess));
}
else
#endif
#ifdef GOTTHARD2D
if (updateAcquisitionRegisters(mess) == FAIL) {
ret = FAIL;
}
else
#endif
if (configured == FAIL) {
ret = FAIL;
@@ -1926,12 +1939,8 @@ int start_and_read_all(int file_des) {
if (ret == FAIL) {
#if defined(VIRTUAL) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
sprintf(mess, "Could not start acquisition. Could not create udp socket in server. Check udp_dstip & udp_dstport.\n");
#else
#if defined(GOTTHARD2D)
sprintf(mess, "Could not start acquisition due to #frames > %d in burst mode\n", MAX_FRAMES_IN_BURST_MODE);
#else
sprintf(mess, "Could not start acquisition\n");
#endif
#endif
FILE_LOG(logERROR,(mess));
}
@@ -2225,7 +2234,7 @@ int get_delay_after_trigger(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -2244,7 +2253,7 @@ int set_delay_after_trigger(int file_des) {
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Setting delay after trigger %lld ns\n", (long long int)arg));
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// only set
@@ -2458,7 +2467,7 @@ int get_period_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -2473,7 +2482,7 @@ int get_delay_after_trigger_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -2518,7 +2527,7 @@ int get_frames_from_start(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -2533,7 +2542,7 @@ int get_actual_time(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -2548,7 +2557,7 @@ int get_measurement_time(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
@@ -3836,27 +3845,31 @@ int power_chip(int file_des) {
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Powering chip to %d\n", arg));
#if (!defined(JUNGFRAUD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D))
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// set & get
if ((arg == -1) || (Server_VerifyLock() == OK)) {
#ifdef MYTHEN3D
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
// check only when powering on
if (arg != -1 && arg != 0) {
int type_ret = checkDetectorType();
if (type_ret == -1) {
ret = FAIL;
sprintf(mess, "Could not power on chip. Could not open file to get type of module attached.\n");
FILE_LOG(logERROR,(mess));
} else if (type_ret == -2) {
ret = FAIL;
sprintf(mess, "Could not power on chip. No module attached!\n");
FILE_LOG(logERROR,(mess));
} else if (type_ret == FAIL) {
ret = FAIL;
sprintf(mess, "Could not power on chip. Wrong module attached!\n");
FILE_LOG(logERROR,(mess));
if (checkModuleFlag) {
int type_ret = checkDetectorType();
if (type_ret == -1) {
ret = FAIL;
sprintf(mess, "Could not power on chip. Could not open file to get type of module attached.\n");
FILE_LOG(logERROR,(mess));
} else if (type_ret == -2) {
ret = FAIL;
sprintf(mess, "Could not power on chip. No module attached!\n");
FILE_LOG(logERROR,(mess));
} else if (type_ret == FAIL) {
ret = FAIL;
sprintf(mess, "Could not power on chip. Wrong module attached!\n");
FILE_LOG(logERROR,(mess));
}
} else {
FILE_LOG(logINFOBLUE, ("In No-Module mode: Ignoring module type. Continuing.\n"));
}
}
#endif
@@ -6446,7 +6459,7 @@ int get_veto_photon(int file_des) {
}
int set_veto_refernce(int file_des) {
int set_veto_reference(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int args[2] = {-1, -1};
@@ -6580,4 +6593,61 @@ int get_counter_mask(int file_des) {
FILE_LOG(logDEBUG, ("counter mask retval: 0x%x\n", retval));
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
int set_burst_type(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
enum burstModeType arg = 0;
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
FILE_LOG(logINFO, ("Setting burst type: %d\n", arg));
#ifndef GOTTHARD2D
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
switch (arg) {
case INTERNAL:
case EXTERNAL:
break;
default:
modeNotImplemented("Burst type", (int)arg);
break;
}
if (ret == OK) {
setBurstType(arg);
enum burstModeType retval = getBurstType();
FILE_LOG(logDEBUG, ("burst type retval: %d\n", retval));
if (retval != arg) {
ret = FAIL;
sprintf(mess, "Could not set burst type. Set %s, got %s\n", (arg == 0 ? "internal" : "external"), (retval == 0 ? "internal" : "external"));
FILE_LOG(logERROR, (mess));
}
}
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
}
int get_burst_type(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
enum burstModeType retval = 0;
FILE_LOG(logDEBUG1, ("Getting burst type\n"));
#ifndef GOTTHARD2D
functionNotImplemented();
#else
// get only
retval = getBurstType();
FILE_LOG(logDEBUG, ("burst type retval: %d\n", retval));
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}