mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
moench: first version
This commit is contained in:
@ -515,7 +515,7 @@ void setupDetector() {
|
||||
// altera pll
|
||||
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
|
||||
|
||||
bus_w(ADC_PORT_INVERT_REG, 0);// depends on chip
|
||||
setADCInvertRegister(0);// depends on chip
|
||||
|
||||
FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
|
||||
cleanFifos(); // FIXME: why twice?
|
||||
|
||||
@ -107,7 +107,6 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2593)
|
||||
#define MAXIMUM_ADC_CLK (65)
|
||||
#define PLL_VCO_FREQ_MHZ (800)
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#include "slsDetectorFunctionList.h"
|
||||
#include "versionAPI.h"
|
||||
#include "clogger.h"
|
||||
#include <sys/select.h>
|
||||
|
||||
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
|
||||
#include "LTC2620.h" // dacs
|
||||
#include "MAX1932.h" // hv
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
#include <string.h>
|
||||
#include <unistd.h> // usleep
|
||||
#include <sys/select.h>
|
||||
#ifdef VIRTUAL
|
||||
#include <pthread.h>
|
||||
#include <time.h>
|
||||
|
||||
@ -34,6 +34,7 @@ $(PROGS): $(OBJS)
|
||||
mv $(PROGS) $(DESTDIR)
|
||||
rm *.gdb
|
||||
rm $(main_src)*.o
|
||||
rm *.o
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
/* Fix pattern RO register */
|
||||
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
|
||||
|
||||
#define FIX_PATT_VAL (0xACDC2014)
|
||||
#define FIX_PATT_VAL (0xACDC2016)
|
||||
|
||||
/* Status RO register */
|
||||
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
|
||||
@ -289,7 +289,7 @@
|
||||
/* Configuration RW register */
|
||||
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
|
||||
|
||||
#define CONFIG_LED_DSBL_OFST (0)
|
||||
#define CONFIG_LED_DSBL_OFST (0) // Not used in firmware or software
|
||||
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
|
||||
@ -365,23 +365,23 @@
|
||||
#define PATTERN_CNTRL_RD_OFST (1)
|
||||
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_OFST (16)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
|
||||
|
||||
/* Pattern Limit RW regiser */
|
||||
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LIMIT_STRT_OFST (0)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x0000FFFF << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STP_OFST (16)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x0000FFFF << PATTERN_LIMIT_STP_OFST)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
|
||||
|
||||
/* Pattern Loop 0 Address RW regiser */
|
||||
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 0 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
|
||||
@ -390,9 +390,9 @@
|
||||
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 1 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
|
||||
@ -401,9 +401,9 @@
|
||||
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 2 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
|
||||
@ -412,31 +412,36 @@
|
||||
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
|
||||
//FIXME: is mask 3FF
|
||||
|
||||
/* Pattern Wait 1 RW regiser */
|
||||
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
|
||||
|
||||
/* Pattern Wait 2 RW regiser */
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
|
||||
|
||||
/* Samples RW register */
|
||||
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
|
||||
|
||||
#define SAMPLES_DIGITAL_OFST (0)
|
||||
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
|
||||
#define SAMPLES_ANALOG_OFST (16)
|
||||
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
|
||||
|
||||
/** Power RW register */
|
||||
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
|
||||
|
||||
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
|
||||
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
|
||||
#define POWER_HV_SLCT_OFST (31)
|
||||
#define POWER_HV_SLCT_MSK (0x00000001 << POWER_HV_SLCT_OFST)
|
||||
#define POWER_CHIP_OFST (16)
|
||||
#define POWER_CHIP_MSK (0x00000001 << POWER_CHIP_OFST)
|
||||
#define POWER_HV_INTERNAL_SLCT_OFST (31)
|
||||
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
|
||||
|
||||
/* Number of Words RW register TODO */
|
||||
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
|
||||
@ -493,17 +498,16 @@
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
|
||||
|
||||
/* ADC Disable RW register TODO */
|
||||
#define ADC_DISABLE_REG (0x78 << MEM_MAP_SHIFT)
|
||||
/* Readout enable RW register */
|
||||
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
|
||||
|
||||
/* DAC Value RW register TODO */
|
||||
//#define DAC_VALUE_REG (0x79 << MEM_MAP_SHIFT)
|
||||
|
||||
/* DAC Number RW register TODO */
|
||||
//#define DAC_NUMBER_REG (0x7A << MEM_MAP_SHIFT)
|
||||
#define READOUT_10G_ENABLE_ANLG_OFST (0)
|
||||
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
|
||||
#define READOUT_10G_ENABLE_DGTL_OFST (8)
|
||||
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
|
||||
|
||||
/* Digital Bit External Trigger RW register */
|
||||
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
|
||||
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
|
||||
|
||||
#define DBIT_EXT_TRG_SRC_OFST (0)
|
||||
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
|
||||
@ -511,7 +515,8 @@
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
|
||||
|
||||
/* Pin Delay 0 RW register */
|
||||
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
|
||||
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
|
||||
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
|
||||
@ -523,7 +528,7 @@
|
||||
|
||||
/* Pin Delay 1 RW register
|
||||
* Each bit configured as enable for dynamic output delay configuration */
|
||||
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
|
||||
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
|
||||
|
||||
/** Pattern Mask 64 bit RW regiser */
|
||||
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
|
||||
@ -533,7 +538,7 @@
|
||||
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
|
||||
|
||||
|
||||
|
||||
/* Round Robin */
|
||||
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
|
||||
|
||||
|
||||
|
||||
BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
Executable file
BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
Executable file
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -4,27 +4,51 @@
|
||||
|
||||
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x180314
|
||||
#define REQRD_FRMWR_VRSN 0x180314
|
||||
#define REQRD_FRMWR_VRSN 0x200302
|
||||
|
||||
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct ip_header_struct {
|
||||
uint16_t ip_len;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl:4 ,ip_ver:4;
|
||||
uint16_t ip_offset:13,ip_flag:3;
|
||||
uint16_t ip_ident;
|
||||
uint16_t ip_chksum;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint32_t ip_sourceip;
|
||||
uint32_t ip_destip;
|
||||
} ip_header;
|
||||
typedef struct udp_header_struct {
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl: 4, ip_ver: 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
|
||||
/* Enums */
|
||||
enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
|
||||
#define DEFAULT_DAC_VALS { 1300, /* MO_VBP_COLBUF */ \
|
||||
1000, /* MO_VIPRE */ \
|
||||
1400, /* MO_VIN_CM */ \
|
||||
680, /* MO_VB_SDA */ \
|
||||
1428, /* MO_VCASC_SFP */ \
|
||||
1200, /* MO_VOUT_CM */ \
|
||||
800, /* MO_VIPRE_CDS */ \
|
||||
900 /* MO_IBIAS_SFP */ \
|
||||
};
|
||||
|
||||
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
|
||||
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
|
||||
#define CLK_NAMES "run", "adc", "sync", "dbit"
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NCHAN (32)
|
||||
@ -33,12 +57,13 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
#define CLK_FREQ (156.25) /* MHz */
|
||||
#define NSAMPLES_PER_ROW (25)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
|
||||
#define DEFAULT_NUM_SAMPLES (1)
|
||||
#define DEFAULT_NUM_SAMPLES (5000)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
@ -46,35 +71,37 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
|
||||
#define DEFAULT_VLIMIT (-100)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
#define DEFAULT_RUN_CLK (40)
|
||||
#define DEFAULT_ADC_CLK (20)
|
||||
#define DEFAULT_SYNC_CLK (20)
|
||||
#define DEFAULT_DBIT_CLK (200)
|
||||
#define DEFAULT_RUN_CLK (40)
|
||||
#define DEFAULT_ADC_CLK (20)
|
||||
#define DEFAULT_SYNC_CLK (20)
|
||||
#define DEFAULT_DBIT_CLK (20)
|
||||
#define DEFAULT_ADC_PHASE_DEG (30)
|
||||
#define DEFAULT_PIPELINE (14)
|
||||
|
||||
#define HIGHVOLTAGE_MIN (60)
|
||||
#define HIGHVOLTAGE_MAX (200)
|
||||
#define HIGHVOLTAGE_MAX (200) // min dac val
|
||||
#define DAC_MIN_MV (0)
|
||||
#define DAC_MAX_MV (2500)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define MAX_PATTERN_LENGTH (0x7FFF)
|
||||
#define MAX_PATTERN_LENGTH (0x2000)
|
||||
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
|
||||
#define MAX_PHASE_SHIFTS_STEPS (8)
|
||||
|
||||
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
|
||||
#define WAIT_TIME_US_PLL (10 * 1000)
|
||||
#define WAIT_TIME_US_STP_ACQ (100)
|
||||
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
|
||||
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_FIFO_RD_STROBE (10)
|
||||
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
|
||||
|
||||
/* MSB & LSB DEFINES */
|
||||
#define MSB_OF_64_BIT_REG_OFST (32)
|
||||
#define LSB_OF_64_BIT_REG_OFST (0)
|
||||
#define BIT_32_MSK (0xFFFFFFFF)
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define IP_PACKETSIZE (0x2032)
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2593) //FIXME: a default value?
|
||||
#define MAXIMUM_ADC_CLK (40)
|
||||
#define ADC_PORT_INVERT_VAL (0x4a342593)
|
||||
#define MAXIMUM_ADC_CLK (20)
|
||||
#define PLL_VCO_FREQ_MHZ (800)
|
||||
|
||||
|
||||
@ -3,6 +3,14 @@
|
||||
#ifdef GOTTHARDD
|
||||
#include "clogger.h" // runState(enum TLogLevel)
|
||||
#endif
|
||||
#ifndef VIRTUAL
|
||||
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
#include "programFpgaNios.h"
|
||||
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
|
||||
#include "programFpgaBlackfin.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h> // FILE
|
||||
#include <sys/types.h>
|
||||
@ -84,7 +92,7 @@ int updateDatabytesandAllocateRAM();
|
||||
void updateDataBytes();
|
||||
#endif
|
||||
|
||||
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D)
|
||||
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || defined(MOENCHD)
|
||||
int setDefaultDacs();
|
||||
#endif
|
||||
#ifdef GOTTHARD2D
|
||||
@ -141,6 +149,8 @@ void setADCEnableMask_10G(uint32_t mask);
|
||||
uint32_t getADCEnableMask_10G();
|
||||
void setADCInvertRegister(uint32_t val);
|
||||
uint32_t getADCInvertRegister();
|
||||
#endif
|
||||
#if defined(CHIPTESTBOARDD)
|
||||
int setExternalSamplingSource(int val);
|
||||
int setExternalSampling(int val);
|
||||
#endif
|
||||
@ -213,6 +223,8 @@ int64_t getStorageCellDelay();
|
||||
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
|
||||
int setNumAnalogSamples(int val);
|
||||
int getNumAnalogSamples();
|
||||
#endif
|
||||
#ifdef CHIPTESTBOARDD
|
||||
int setNumDigitalSamples(int val);
|
||||
int getNumDigitalSamples();
|
||||
#endif
|
||||
@ -298,11 +310,9 @@ void setPower(enum DACINDEX ind, int val);
|
||||
void powerOff();
|
||||
#endif
|
||||
|
||||
#ifndef MOENCHD
|
||||
#if !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
#if !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
int getADC(enum ADCINDEX ind);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int setHighVoltage(int val);
|
||||
|
||||
@ -358,6 +368,7 @@ int enableTenGigabitEthernet(int val);
|
||||
// moench specific - powerchip
|
||||
#ifdef MOENCHD
|
||||
int powerChip (int on);
|
||||
int setAnalogOnlyReadout();
|
||||
#endif
|
||||
|
||||
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
|
||||
@ -383,8 +394,10 @@ uint64_t writePatternWord(int addr, uint64_t word);
|
||||
int setPatternWaitAddress(int level, int addr);
|
||||
uint64_t setPatternWaitTime(int level, uint64_t t);
|
||||
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
|
||||
#ifdef CHIPTESTBOARDD
|
||||
int setLEDEnable(int enable);
|
||||
void setDigitalIODelay(uint64_t pinMask, int delay);
|
||||
#endif
|
||||
void setPatternMask(uint64_t mask);
|
||||
uint64_t getPatternMask();
|
||||
void setPatternBitMask(uint64_t mask);
|
||||
|
||||
@ -2,13 +2,6 @@
|
||||
#include "slsDetectorFunctionList.h"
|
||||
#include "communication_funcs.h"
|
||||
#include "clogger.h"
|
||||
#ifndef VIRTUAL
|
||||
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
#include "programFpgaNios.h"
|
||||
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
|
||||
#include "programFpgaBlackfin.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <string.h>
|
||||
#include <arpa/inet.h>
|
||||
@ -928,10 +921,35 @@ int set_dac(int file_des) {
|
||||
case V_LIMIT:
|
||||
break;
|
||||
#elif MOENCHD
|
||||
case VBP_COLBUF:
|
||||
serverDacIndex = MO_VBP_COLBUF;
|
||||
break;
|
||||
case VIPRE:
|
||||
serverDacIndex = MO_VIPRE;
|
||||
break;
|
||||
case VIN_CM:
|
||||
serverDacIndex = MO_VIN_CM;
|
||||
break;
|
||||
case VB_SDA:
|
||||
serverDacIndex = MO_VB_SDA;
|
||||
break;
|
||||
case VCASC_SFP:
|
||||
serverDacIndex = MO_VCASC_SFP;
|
||||
break;
|
||||
case VOUT_CM:
|
||||
serverDacIndex = MO_VOUT_CM;
|
||||
break;
|
||||
case VIPRE_CDS:
|
||||
serverDacIndex = MO_VIPRE_CDS;
|
||||
break;
|
||||
case IBIAS_SFP:
|
||||
serverDacIndex = MO_IBIAS_SFP;
|
||||
break;
|
||||
case ADC_VPP:
|
||||
case HIGH_VOLTAGE:
|
||||
case V_LIMIT:
|
||||
break;
|
||||
|
||||
#elif MYTHEN3D
|
||||
case HIGH_VOLTAGE:
|
||||
break;
|
||||
@ -1056,17 +1074,13 @@ int set_dac(int file_des) {
|
||||
serverDacIndex = J_VREF_COMP;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
#ifdef CHIPTESTBOARDD
|
||||
if (ind < NDAC_ONLY) {
|
||||
serverDacIndex = ind;
|
||||
break;
|
||||
}
|
||||
#elif MOENCHD
|
||||
if (ind < NDAC) {
|
||||
serverDacIndex = ind;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
modeNotImplemented("Dac Index", (int)ind);
|
||||
break;
|
||||
@ -1750,18 +1764,23 @@ int start_acquisition(int file_des) {
|
||||
FILE_LOG(logDEBUG1, ("Starting Acquisition\n"));
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
|
||||
int mode = getReadoutMode();
|
||||
int asamples = getNumAnalogSamples();
|
||||
int dsamples = getNumDigitalSamples();
|
||||
if ((mode == ANALOG_AND_DIGITAL || mode == ANALOG_ONLY) && (asamples <= 0)) {
|
||||
#if defined(MOENCHD)
|
||||
if (getNumAnalogSamples() <= 0) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", asamples);
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", getNumAnalogSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else if ((mode == ANALOG_AND_DIGITAL || mode == DIGITAL_ONLY) && (dsamples <= 0)) {
|
||||
else
|
||||
#endif
|
||||
#if defined(CHIPTESTBOARDD)
|
||||
if ((getReadoutMode() == ANALOG_AND_DIGITAL || mode == ANALOG_ONLY) && (getNumAnalogSamples() <= 0)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of digital samples: %d.\n", dsamples);
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", getNumAnalogSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else if ((getReadoutMode() == ANALOG_AND_DIGITAL || mode == DIGITAL_ONLY) && (getNumDigitalSamples() <= 0)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of digital samples: %d.\n", getNumDigitalSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else
|
||||
@ -1880,18 +1899,23 @@ int start_and_read_all(int file_des) {
|
||||
FILE_LOG(logDEBUG1, ("Starting Acquisition\n"));
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
|
||||
int mode = getReadoutMode();
|
||||
int asamples = getNumAnalogSamples();
|
||||
int dsamples = getNumDigitalSamples();
|
||||
if ((mode == ANALOG_AND_DIGITAL || mode == ANALOG_ONLY) && (asamples <= 0)) {
|
||||
#if defined(MOENCHD)
|
||||
if (getNumAnalogSamples() <= 0) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", asamples);
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", getNumAnalogSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else if ((mode == ANALOG_AND_DIGITAL || mode == DIGITAL_ONLY) && (dsamples <= 0)) {
|
||||
else
|
||||
#endif
|
||||
#if defined(CHIPTESTBOARDD)
|
||||
if ((getReadoutMode() == ANALOG_AND_DIGITAL || mode == ANALOG_ONLY) && (getNumAnalogSamples() <= 0)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of digital samples: %d.\n", dsamples);
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of analog samples: %d.\n", getNumAnalogSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else if ((getReadoutMode() == ANALOG_AND_DIGITAL || mode == DIGITAL_ONLY) && (getNumDigitalSamples() <= 0)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not start acquisition. Invalid number of digital samples: %d.\n", getNumDigitalSamples());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else
|
||||
@ -2102,14 +2126,23 @@ int set_num_analog_samples(int file_des) {
|
||||
#else
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
ret = setNumAnalogSamples(arg);
|
||||
if (ret == FAIL) {
|
||||
sprintf(mess, "Could not set number of analog samples to %d. Could not allocate RAM\n", arg);
|
||||
FILE_LOG(logERROR,(mess));
|
||||
} else {
|
||||
int retval = getNumAnalogSamples();
|
||||
FILE_LOG(logDEBUG1, ("retval num analog samples %d\n", retval));
|
||||
validate(arg, retval, "set number of analog samples", DEC);
|
||||
#ifdef MOENCHD
|
||||
if (arg % NSAMPLES_PER_ROW != 0) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Could not set number of analog samples to %d. Must be divisible by %d\n", arg, NSAMPLES_PER_ROW);
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
#endif
|
||||
if (ret == OK) {
|
||||
ret = setNumAnalogSamples(arg);
|
||||
if (ret == FAIL) {
|
||||
sprintf(mess, "Could not set number of analog samples to %d. Could not allocate RAM\n", arg);
|
||||
FILE_LOG(logERROR,(mess));
|
||||
} else {
|
||||
int retval = getNumAnalogSamples();
|
||||
FILE_LOG(logDEBUG1, ("retval num analog samples %d\n", retval));
|
||||
validate(arg, retval, "set number of analog samples", DEC);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -2121,7 +2154,7 @@ int get_num_digital_samples(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int retval = -1;
|
||||
|
||||
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
|
||||
#if !defined(CHIPTESTBOARDD)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2140,7 +2173,7 @@ int set_num_digital_samples(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Setting number of digital samples %d\n", arg));
|
||||
|
||||
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
|
||||
#if !defined(CHIPTESTBOARDD)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// only set
|
||||
@ -2856,10 +2889,16 @@ int send_update(int file_des) {
|
||||
#endif
|
||||
|
||||
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
|
||||
// analog samples
|
||||
i32 = getNumAnalogSamples();
|
||||
n = sendData(file_des,&i32,sizeof(i32),INT32);
|
||||
if (n < 0) return printSocketReadError();
|
||||
|
||||
// 1g adcmask
|
||||
i32 = getADCEnableMask();
|
||||
n = sendData(file_des,&i32,sizeof(i32),INT32);
|
||||
if (n < 0) return printSocketReadError();
|
||||
|
||||
// 10g adc mask
|
||||
i32 = getADCEnableMask_10G();
|
||||
n = sendData(file_des,&i32,sizeof(i32),INT32);
|
||||
@ -4237,7 +4276,7 @@ int led(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Setting led enable to %d\n", arg));
|
||||
|
||||
#if (!defined(MOENCHD)) && (!defined(CHIPTESTBOARDD))
|
||||
#if (!defined(CHIPTESTBOARDD))
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// set & get
|
||||
@ -4262,7 +4301,7 @@ int digital_io_delay(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Digital IO Delay, pinMask: 0x%llx, delay:%d ps\n", args[0], (int)args[1]));
|
||||
|
||||
#if (!defined(MOENCHD)) && (!defined(CHIPTESTBOARDD))
|
||||
#if (!defined(CHIPTESTBOARDD))
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// only set
|
||||
@ -6169,9 +6208,11 @@ int set_pipeline(int file_des) {
|
||||
case ADC_CLOCK:
|
||||
c = ADC_CLK;
|
||||
break;
|
||||
#ifdef CHIPTESTBOARDD
|
||||
case DBIT_CLOCK:
|
||||
c = DBIT_CLK;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
modeNotImplemented("clock index (pipeline set)", ind);
|
||||
break;
|
||||
|
||||
Reference in New Issue
Block a user