mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-24 23:30:03 +02:00
PR minor changes
This commit is contained in:
parent
d8fccdcefa
commit
3ea2520615
Binary file not shown.
@ -56,9 +56,9 @@ uint32_t adcEnableMask_1g = 0;
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uint8_t adcEnableMask_10g = 0;
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0};
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
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int dacValues[NDAC] = {0};
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int dacValues[NDAC] = {};
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// software limit that depends on the current chip on the ctb
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int vLimit = 0;
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int highvoltage = 0;
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@ -1420,7 +1420,7 @@ int setHighVoltage(int val){
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void setTiming( enum timingMode arg){
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if(arg != GET_TIMING_MODE){
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switch((int)arg){
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switch(arg){
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
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@ -2559,7 +2559,7 @@ int calculateDataBytes(){
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return dataBytes;
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}
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int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips(){return NCHIP;}
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int getNumberOfDACs(){return NDAC;}
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int getNumberOfChannelsPerChip(){return NCHAN;}
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@ -1108,7 +1108,7 @@ int setHighVoltage(int val) {
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void setTiming( enum timingMode arg) {
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enum timingMode ret=GET_TIMING_MODE;
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if (arg != GET_TIMING_MODE) {
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switch((int)arg) {
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switch(arg) {
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case AUTO_TIMING: ret = 0; break;
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case TRIGGER_EXPOSURE: ret = 2; break;
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case BURST_TRIGGER: ret = 1; break;
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@ -2041,7 +2041,7 @@ int calculateDataBytes() {
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int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips() {return NCHIP;}
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int getNumberOfDACs() {return NDAC;}
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int getNumberOfChannelsPerChip() {return NCHAN;}
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@ -37,8 +37,8 @@ int virtual_stop = 0;
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#endif
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enum detectorSettings thisSettings = UNINITIALIZED;
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
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uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {};
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int onChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
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@ -51,7 +51,7 @@ enum burstModeType burstType = INTERNAL;
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int64_t exptime_ns = 0;
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int64_t period_ns = 0;
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int64_t nframes = 0;
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int detPos[2] = {0, 0};
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int detPos[2] = {};
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int isInitCheckDone() {
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return initCheckDone;
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@ -171,7 +171,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type != GOTTHARD2){
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FILE_LOG(logERROR, ("This is not a Gotthard2 Server (read %d, expected %d)\n", type, GOTTHARD2));
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return FAIL;
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@ -1092,7 +1092,7 @@ int setHighVoltage(int val){
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/* parameters - timing */
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void setTiming( enum timingMode arg){
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if(arg != GET_TIMING_MODE){
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switch((int)arg){
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switch(arg){
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
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@ -1356,8 +1356,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
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relativePhase *= -1;
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direction = 0;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
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clkPhase[ind] = valShift;
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@ -1429,7 +1429,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
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return -1;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
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}
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@ -1447,7 +1447,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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char* clock_names[] = {CLK_NAMES};
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int vcofreq = getVCOFrequency(ind);
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int currentdiv = vcofreq / clkFrequency[ind];
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int currentdiv = vcofreq / (int)clkFrequency[ind];
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int newfreq = vcofreq / val;
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FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
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@ -1463,8 +1463,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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// Calculate and set output frequency
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
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clkFrequency[ind] = newfreq;
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FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
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@ -1499,7 +1499,7 @@ int getClockDivider(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
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return -1;
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}
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return (getVCOFrequency(ind) / clkFrequency[ind]);
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return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
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}
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int setInjectChannel(int offset, int increment) {
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@ -2106,7 +2106,7 @@ int calculateDataBytes() {
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return getTotalNumberOfChannels() * DYNAMIC_RANGE;
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}
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int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips() {return NCHIP;}
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int getNumberOfDACs() {return NDAC;}
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int getNumberOfChannelsPerChip() {return NCHAN;}
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@ -30,10 +30,10 @@ int virtual_status = 0;
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int virtual_stop = 0;
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int highvoltage = 0;
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#endif
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int detPos[2] = {0, 0};
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int detPos[2] = {};
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int detectorFirstServer = 1;
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int dacValues[NDAC] = {0};
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int dacValues[NDAC] = {};
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enum detectorSettings thisSettings = UNINITIALIZED;
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enum externalSignalFlag signalMode = 0;
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@ -128,7 +128,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type == DETECTOR_TYPE_MOENCH_VAL){
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FILE_LOG(logERROR, ("This is not a Gotthard Server (read %d, expected ?)\n", type));
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return FAIL;
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@ -1180,7 +1180,7 @@ void setTiming( enum timingMode arg){
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u_int32_t addr = EXT_SIGNAL_REG;
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if (arg != GET_TIMING_MODE){
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switch((int)arg){
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switch(arg){
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(addr, EXT_SIGNAL_OFF_VAL);
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@ -1680,7 +1680,7 @@ int calculateDataBytes(){
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return DATA_BYTES;
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}
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int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips(){return NCHIP;}
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int getNumberOfDACs(){return NDAC;}
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int getNumberOfChannelsPerChip(){return NCHAN;}
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@ -38,9 +38,9 @@ int virtual_stop = 0;
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enum detectorSettings thisSettings = UNINITIALIZED;
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int dacValues[NDAC] = {};
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int adcPhase = 0;
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int detPos[4] = {0, 0, 0, 0};
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int detPos[4] = {};
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int numUDPInterfaces = 1;
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@ -171,7 +171,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type != JUNGFRAU){
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FILE_LOG(logERROR, ("This is not a Jungfrau Server (read %d, expected %d)\n", type, JUNGFRAU));
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return FAIL;
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@ -921,7 +921,7 @@ int setHighVoltage(int val){
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void setTiming( enum timingMode arg){
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if(arg != GET_TIMING_MODE){
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switch((int)arg){
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switch(arg){
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
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@ -1832,7 +1832,7 @@ int calculateDataBytes(){
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return DATA_BYTES;
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}
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int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips(){return NCHIP;}
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int getNumberOfDACs(){return NDAC;}
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int getNumberOfChannelsPerChip(){return NCHAN;}
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@ -32,12 +32,12 @@ int virtual_status = 0;
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int virtual_stop = 0;
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#endif
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {};
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int detPos[2] = {0, 0};
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int detPos[2] = {};
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uint32_t countermask = 0; // will be removed later when in firmware converted to mask
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int isInitCheckDone() {
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@ -158,7 +158,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type != MYTHEN3){
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FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
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return FAIL;
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@ -703,7 +703,7 @@ int setHighVoltage(int val){
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/* parameters - timing */
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void setTiming( enum timingMode arg){
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if(arg != GET_TIMING_MODE){
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switch((int)arg){
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switch (arg) {
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
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@ -714,7 +714,6 @@ void setTiming( enum timingMode arg){
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break;
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default:
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FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
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return;
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}
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}
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}
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@ -1146,8 +1145,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
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relativePhase *= -1;
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direction = 0;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
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clkPhase[ind] = valShift;
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@ -1219,7 +1218,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
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return -1;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
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}
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@ -1237,7 +1236,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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char* clock_names[] = {CLK_NAMES};
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int vcofreq = getVCOFrequency(ind);
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int currentdiv = vcofreq / clkFrequency[ind];
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int currentdiv = vcofreq / (int)clkFrequency[ind];
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int newfreq = vcofreq / val;
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FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
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@ -1252,8 +1251,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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// Calculate and set output frequency
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
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clkFrequency[ind] = newfreq;
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FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
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@ -1287,7 +1286,7 @@ int getClockDivider(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
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return -1;
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}
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return (getVCOFrequency(ind) / clkFrequency[ind]);
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return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
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}
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/* aquisition */
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@ -1479,7 +1478,7 @@ int calculateDataBytes() {
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return 0;
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}
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int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips() {return NCHIP;}
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int getNumberOfDACs() {return NDAC;}
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int getNumberOfChannelsPerChip() {return NCHAN;}
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@ -1483,12 +1483,12 @@ int64_t slsDetector::getMeasurementTime() const {
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return retval;
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}
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slsDetectorDefs::timingMode slsDetector::setTimingMode(timingMode pol) {
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slsDetectorDefs::timingMode slsDetector::setTimingMode(timingMode value) {
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int fnum = F_SET_TIMING_MODE;
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auto arg = static_cast<int>(pol);
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//auto arg = static_cast<int>(pol);
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timingMode retval = GET_TIMING_MODE;
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FILE_LOG(logDEBUG1) << "Setting communication to mode " << pol;
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sendToDetector(fnum, arg, retval);
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FILE_LOG(logDEBUG1) << "Setting communication to mode " << value;
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sendToDetector(fnum, static_cast<int>(value), retval);
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FILE_LOG(logDEBUG1) << "Timing Mode: " << retval;
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return retval;
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}
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@ -626,10 +626,10 @@ class slsDetector : public virtual slsDetectorDefs {
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/**
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* Set/get timing mode
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* @param pol timing mode (-1 gets)
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* @param value timing mode (-1 gets)
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* @returns current timing mode
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*/
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timingMode setTimingMode(timingMode pol = GET_TIMING_MODE);
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timingMode setTimingMode(timingMode value = GET_TIMING_MODE);
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/**
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* Set/get dynamic range
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@ -4,9 +4,9 @@
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#define APIRECEIVER 0x190722
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#define APIGUI 0x190723
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#define APIMOENCH 0x190820
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#define APIGOTTHARD 0x191127
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#define APIJUNGFRAU 0x191127
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#define APICTB 0x191210
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#define APIMYTHEN3 0x200120
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#define APIGOTTHARD2 0x200121
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#define APIEIGER 0x200121
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#define APICTB 0x200122
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#define APIGOTTHARD 0x200122
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#define APIGOTTHARD2 0x200122
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#define APIEIGER 0x200122
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#define APIJUNGFRAU 0x200122
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#define APIMYTHEN3 0x200122
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Block a user