* slsSupportLib done, at receiver rooting out in implementation
* removed from receiver and client
* removed everywhere except gui, python and client(commands.yaml and Detector.h)
* updated python
* fixed autocomplete to print what the issue is if there is one with ToString when running the autocomplete script to generate fixed.json. updated readme.md in generator folder
* formatting
* removed enums for dacs
* udpating autocomplete and generating commands
* removed gotthard from docs and release notes
* removed dac test
* bug from removing g1
* fixed virtual test for xilinx, was minor. so in this PR
* gui done
* binary in merge fix
* formatting and removing enums
* updated fixed and dump.json
* bash autocomplete
* updated doc on command line generation
* removing increments in dac enums for backward compatibility. Not required
* removed ROI from rxParameters (only in g1), not needed to be backward compatible
* removed the phase shift option from det server staruip
* updated RegisterDefs.h from firmware update
* Revert "updated RegisterDefs.h from firmware update"
This reverts commit 64f1b2546e742f0b0513124a599cd9bcde11760c.
* updated registers and had it formatted
* Revert "updated registers and had it formatted"
This reverts commit 1641b705b0d8616bcff4a5cd796d8796d09391f2.
* udpated registers from firmware, reading config file in server (chip config, reset chip, enable_clock_pattern) specific for matterhorn,this is done when powering on chip, removed startreadout, fixed status register bits, updated firmware version
* fix for patioctrl allowed for zxilinx and adding readout pattern for scientists that like to push the acquire button
* fixing default enable clock and readout pattern for xilinx (patioctrl has to be 32 bit)
* Xilinxctb/first image (#1094)
* reduce xilinxCTB readout done checks to single register, increased clockEna pattern limits, clear FPGA FiFos and counters on powerchip, disable counters 1-3 in matterhorn configuration
* change print of xilinxctb server
* remove acquisition done check
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* binary xilinx in
* formatting
* added reset of udp buffer FIFO to xilinxCTB
---------
Co-authored-by: Martin Mueller <72937414+mmarti04@users.noreply.github.com>
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* jf wip: bunch id decoder only in pcb v2.0 check and comments
* auto comp disable the same way for both chip versions. compdisabletime also available for 1.1 now
* fixed tests
* formatting
* binary in
* cli: patwaittime also takes time argument, api: patwaitclocks and patwaitinterval, tcp: patwaitinterval is 2 functions for set and get, patwaitclocks remains a single for backward compatibility with -1 for get, server (loadpattern): clks using member names (needs to be refactored). needs tobe discussed what to do with pattern files.
* all tests passed
* fixed test
* exptime deprecated for ctb and xilinx
* pyctbgui..not there yet
* fixed in pyctbgui
* removed redundant warning for ctb and xilinx exptime in Detector class (already in module class handling all exptime signatures), patwait, patloop and patnloop have to be non inferrable commands because of support for old commands (level as suffix)
* fix formatting error from command line parsing
* fix tests for patwaittime
* usleep in communication to actually relay the err message of memory allocation to the client (weird but test for now), function in server to handle memory allcoation issues (updates mess, ret and sendsit to the client and returns prior from function implementatin, setting fnum in client for the speicific functions that send to detector each argument separtely, they need to remember the fnum else they throw with the incorrect fnum
* server: every malloc must check if it succeeded, rearranging so that the free is clear as well (only in funcs so far)
* fixed malloc checks in other places other than funcs.c
* jf: rolling back firmware required to v1.5 and 2.5, updated release notes, fixed a bug when updating server (when server name same as link name:throws with no message, pedestal mode check changed for the time being for loops to be 0xFF size
* compensating for jf fw bug for pedestalmode where loops should be 16 bit, but is 8 bit in fw. to be fixed in next version
* formatting
* formatting, merge fix
* fixed python test simulator to kill previous servers
* rmeoved merge binary
* g2: chip reconfigure variable not set when powering on at startup because readconfig is the one configuring the chip the first time to default chip settings
* cleaning up code
* fixing nextframenumber properly with firmware
* updated firmware to have getnextframenumber and fixed setnextframenumber to reset also the header fifo when stopping
* fix tests for gotthard2
* get/set next frame number in G2 (firmware only has set, no get)
* firmware has issues: each stop keeps 2 frame header in fifo and the resetting frame number happens after that
* removed the option to set burstmode to burst external or continuwous internal
* needs to be revisited before 9.0.0
* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests
* updated readoutspeedlist command
- do not validate write reg, setbit and clearbit by default anymore
- --validate will force validation on the bitmask or entire reg
- remove return value for write reg (across server to client, but thankfully not in the Detector class)
- extend validation into writereg, setbit and clearbit for Eiger (always special)
- need to check python (TODO)
- missed the rx_zmqip implementations in detector.h and python bindings
* put back code to obtain adc and dac device indexafter loading device tree and then create folder iio_device_links and create symbolic links there according to device indices found. ln -sf operation not permitted, so folder has to be deleted and created everytime. Also refactored definitions to have all the xilinx name or detector specific stuff out of programbyArm.c
* uncommented waittransceiverreset at startup (should work now) and return of powering off chip at startup (error for transceiver alignment reset)
* updated registerdefs from firmware
* minor prints and updating names from registerdefs
* waittransceiverreset has been fixed in firmware and removing warnign for that, transceiver alignment check for powering off chip is not done in fw (giving a warning and returning ok for now)
* fixing ipchecksum (not done), removed startperiphery, allowing readout command to be allowed for xilinx when acquiring
* m3: fixed stop server not starting up with setup variables
* all servers except eiger fixed for virtual stop server to start up with setupDetector function called
* virtual tests work
* eiger: versions print neednt be in stop server
* jungfrau: stop server (not virtual) also needs to read config file
* ensuring master is setup for virtual and real servers
* voltage regulators only looks at dac and not at ctrl_reg
* xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different)
* Use links for dacs/adc and adapt power rglt thresholds
* Remove wait for transceiver reset
* adc and dac device not used anymore and hence removed
* udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited
---------
Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
* changed common.c readADCFromFile to make it more general and move temperature calculation for Eiger out of this function and inside whereever it is called.
* g2 and m2: gethighvoltage was just a variable set in server, it is now moved to a get inside DAC5671 implementation (but not reading a measured value, instead what is set from a file), high voltage variable used inside DAC5671 for virtual servers
* g2: switching off hv (ifrom non zero to zero value) will wait for 10s; powering on chip reconfigures chip; powering off chip unconfigures chip; powering off chip also includes check if hv = 0, if not throw exception; chip configuration checked before acquring; at start up: hv switched off and chip powered on, so does not wait 10s to switch off hv;
* included test to check powering off chip when hv is on should throw an exception
* g2: check if chip configured before acquiring
* nios: read hv value set from file and virtual still goes into DAC5671 for conversions to and fro dac to V, change common readadc to readparameter to generalize, make sethighvoltage into a get and set to catch errors in get as well, g2: if not at startup, remmeber hv value before setting it and after check if value was being switched off (from a non zero value) and wait 10s if it was (10s wait only for switching off from non zero and not at startup)
* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)
* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
* m3: minor print error if clk divider > max
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
