Dhanya Thattil 37e65634d4

Dev/g2 fix configure chip startup (#1009) ...

* g2: chip reconfigure variable not set when powering on at startup because readconfig is the one configuring the chip the first time to default chip settings

* cleaning up code

2024-10-22 17:19:28 +02:00

..

ctbDetectorServer

Dev/reg bit change no validate (#970)

2024-09-30 16:54:12 +02:00

eigerDetectorServer

Dev/reg bit change no validate (#970)

2024-09-30 16:54:12 +02:00

gotthard2DetectorServer

Dev/g2 fix configure chip startup (#1009)

2024-10-22 17:19:28 +02:00

gotthardDetectorServer

Dev/reg bit change no validate (#970)

2024-09-30 16:54:12 +02:00

jungfrauDetectorServer

updated jungfrau timing info decoder mask (#991)

2024-10-01 11:29:48 +02:00

moenchDetectorServer

Dev/reg bit change no validate (#970)

2024-09-30 16:54:12 +02:00

mythen3DetectorServer

jf: timing info decoder (#987)

2024-10-01 11:17:35 +02:00

slsDetectorServer

Dev/g2 stop frame number (#980)

2024-10-02 15:26:06 +02:00

stripDetectorDaemon

make files

2021-10-18 11:52:23 +02:00

xilinx_ctbDetectorServer

Dev/reg bit change no validate (#970)

2024-09-30 16:54:12 +02:00

CMakeLists.txt

Xilinx ctb (#884)

2024-01-04 17:10:16 +01:00

compileAllServers_noAPIUpdate.sh

Dev/xilinx defaults and pattern (#888)

2024-01-11 18:01:08 +01:00

compileAllServers.sh

Dev/xilinx defaults and pattern (#888)

2024-01-11 18:01:08 +01:00

compileEigerServer.sh

Versioning (#568)

2022-11-09 11:13:09 +01:00