update xilinx regs (#1123)

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>

slsDetectorServers/xilinx_ctbDetectorServer/chip_config_xilinx.txt

@@ -1,24 +1,24 @@
 # Prepare MH02 configuration
-reg 0x600 0x00000041
-reg 0x604 0x01200004
+reg 0xB1B0 0x00000041
+reg 0xB1B4 0x01200004
 
 # configure Matterhorn SPI
-setbit 0x608 0
+setbit 0xB1B8 0
 
 # wait till config is done
-pollbit 0x608 3 0
+pollbit 0xB1B8 3 0
 
 # reset transceiver
-reg 0x658 0x0
-reg 0x658 0x1
-reg 0x658 0x0
+reg 0xB820 0x0
+reg 0xB820 0x1
+reg 0xB820 0x0
 
 # set MSB LSB inversions and polarity for transceiver
-reg 0x658 0x61e0
+reg 0xB820 0x61e0
 
 # Enable MH02 PLL clock
 pattern enable_clock_pattern.pyat
 # start the flow
-setbit 0x108 0
-clearbit 0x108 0
+setbit 0xB004 0
+clearbit 0xB004 0
 sleep 1

slsDetectorServers/xilinx_ctbDetectorServer/reset_chip_xilinx.txt

@@ -1,39 +1,39 @@
 
 # turn off clock
-setbit 0x600 16 
-setbit 0x608 0
+setbit 0xB1B0 16 
+setbit 0xB1B8 0
 sleep 1
 
 # reset Matterhorn periphery
-setbit 0x608 1
+setbit 0xB1B8 1
 sleep 1
 
 # turn on clock
-clearbit 0x600 16
-setbit 0x608 0
+clearbit 0xB1B0 16
+setbit 0xB1B8 0
 sleep 1
 
 # reset rx transceiver datapath
-setbit 0x658 4
+setbit 0xB820 4
 sleep 1
 
 # reset 8b10b counters
-setbit 0x658 9
-setbit 0x658 10
-setbit 0x658 11
-setbit 0x658 12
+setbit 0xB820 9
+setbit 0xB820 10
+setbit 0xB820 11
+setbit 0xB820 12
 sleep 1
-clearbit 0x658 9
-clearbit 0x658 10
+clearbit 0xB820 9
+clearbit 0xB820 10
 
 # reset buffer fifos
-reg 0x5C8 0xFFFFFFFF
-reg 0x5D0 0xFFFFFFFF
-reg 0x5D8 0xFFFFFFFF
-reg 0x5C8 0x0
-reg 0x5D0 0x0
-reg 0x5D8 0x0
-setbit 0x500 18
+reg 0x9024 0xFFFFFFFF
+reg 0x9028 0xFFFFFFFF
+reg 0x902C 0xFFFFFFFF
+reg 0x9024 0x0
+reg 0x9028 0x0
+reg 0x902C 0x0
+setbit 0xA000 18
 
 # load default pattern
 pattern readout_pattern.pyat