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Dev/m3 readout speed (#985)

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* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests

* updated readoutspeedlist command
This commit is contained in:
maliakal_d 2024-09-30 17:22:24 +02:00 committed by GitHub
parent 5b832cb6aa
commit 8a7ed30676
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
12 changed files with 140 additions and 78 deletions
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19
python/slsdet/detector.py
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@ -2111,7 +2111,7 @@ class Detector(CppDetectorApi):
Note
-----
[Jungfrau][Moench] FULL_SPEED, HALF_SPEED (Default), QUARTER_SPEED
[Jungfrau][Moench][Mythen3] FULL_SPEED, HALF_SPEED (Default), QUARTER_SPEED
[Eiger] FULL_SPEED (Default), HALF_SPEED, QUARTER_SPEED
[Moench] FULL_SPEED (Default), HALF_SPEED, QUARTER_SPEED
[Gottthard2] G2_108MHZ (Default), G2_144MHZ
@ -2925,7 +2925,9 @@ class Detector(CppDetectorApi):
@property
def maxclkphaseshift(self):
"""
[Gotthard2][Mythen3] Absolute maximum Phase shift of clocks.
[Gotthard2][Mythen3] Absolute maximum Phase shift of clocks.\n
[Gotthard2] Clock index range: 0-5\n
[Mythen3] Clock index range: 0
:setter: Not Implemented
@ -3986,7 +3988,9 @@ class Detector(CppDetectorApi):
@property
def clkphase(self):
"""
[Gotthard2][Mythen3] Phase shift of all clocks.
[Gotthard2][Mythen3] Phase shift of all clocks.\n
[Gotthard2] Clock index range: 0-5\n
[Mythen3] Clock index range: 0
Example
-------
@ -4004,7 +4008,9 @@ class Detector(CppDetectorApi):
@property
def clkdiv(self):
"""
[Gotthard2][Mythen3] Clock Divider of all clocks. Must be greater than 1.
[Gotthard2][Mythen3] Clock Divider of all clocks. Must be greater than 1.\n
[Gotthard2] Clock index range: 0-5\n
[Mythen3] Clock index range: 0
Example
-------
@ -4060,7 +4066,10 @@ class Detector(CppDetectorApi):
@property
def clkfreq(self):
"""
[Gotthard2][Mythen3] Frequency of clock in Hz.
[Gotthard2][Mythen3] Frequency of clock in Hz.\n
[Gotthard2] Clock index range: 0-5\n
[Mythen3] Clock index range: 0
:setter: Not implemented. Use clkdiv to set frequency

3
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -7,9 +7,6 @@
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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Binary file not shown.

73
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -451,8 +451,6 @@ void setupDetector() {
if (updateModuleId() == FAIL)
return;
clkDivider[READOUT_C0] = DEFAULT_READOUT_C0;
clkDivider[READOUT_C1] = DEFAULT_READOUT_C1;
clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
@ -472,16 +470,10 @@ void setupDetector() {
// pll defines
ALTERA_PLL_C10_SetDefines(
REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, PLL_RESET_REG,
PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK, SYSTEM_STATUS_REG,
SYSTEM_STATUS_RDO_PLL_LCKD_MSK, SYSTEM_STATUS_R_PLL_LCKD_MSK,
READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
REG_OFFSET, 0, BASE_SYSTEM_PLL, PLL_RESET_REG, 0, PLL_RESET_SYSTEM_MSK,
SYSTEM_STATUS_REG, SYSTEM_STATUS_RDO_PLL_LCKD_MSK,
SYSTEM_STATUS_R_PLL_LCKD_MSK, 0, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// change startup clock divider in software
// because firmware only sets max clock divider
setClockDividerWithTimeUpdateOption(READOUT_C0, DEFAULT_READOUT_C0_STARTUP,
0);
// hv
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
@ -552,6 +544,7 @@ void setupDetector() {
}
setAllTrimbits(DEFAULT_TRIMBIT_VALUE);
setReadoutSpeed(DEFAULT_READOUT_SPEED);
}
int resetToDefaultDacs(int hardReset) {
@ -2246,9 +2239,7 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
ALTERA_PLL_C10_SetPhaseShift(SYSTEM_PLL, ind, relativePhase, direction);
clkPhase[ind] = valShift;
return OK;
@ -2318,8 +2309,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
return ALTERA_PLL_C10_GetVCOFrequency(SYSTEM_PLL);
}
int getMaxClockDivider() { return ALTERA_PLL_C10_GetMaxClockDivider(); }
@ -2358,9 +2348,7 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
}
// Calculate and set output frequency
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputClockDivider(pllIndex, clkIndex, val);
ALTERA_PLL_C10_SetOuputClockDivider(SYSTEM_PLL, ind, val);
// Update time settings that depend on system frequency
// timeUpdate = 0 for setChipRegister/setTrimbits etc
@ -2392,14 +2380,9 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
clkDivider[ind]));
// phase is reset by pll (when setting output frequency)
if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0;
} else {
clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0;
}
clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0;
// set the phase in degrees (reset by pll)
for (int i = 0; i < NUM_CLOCKS; ++i) {
@ -2422,6 +2405,42 @@ int getClockDivider(enum CLKINDEX ind) {
return clkDivider[ind];
}
int setReadoutSpeed(int val) {
enum speedLevel speed = FULL_SPEED;
switch (val) {
case FULL_SPEED:
LOG(logINFO, ("Setting Full Speed (100 MHz):\n"));
speed = FULL_SPEED_CLKDIV;
break;
case HALF_SPEED:
LOG(logINFO, ("Setting Half Speed (50 MHz):\n"));
speed = HALF_SPEED_CLKDIV;
break;
case QUARTER_SPEED:
LOG(logINFO, ("Setting Quarter Speed (25 MHz):\n"));
speed = QUARTER_SPEED_CLKDIV;
break;
default:
LOG(logERROR, ("Unknown readout speed %d\n", val));
return FAIL;
}
return setClockDivider(SYSTEM_C0, speed);
}
int getReadoutSpeed(int *retval) {
int clkdiv = getClockDivider(SYSTEM_C0);
if (clkdiv == FULL_SPEED_CLKDIV) {
*retval = FULL_SPEED;
} else if (clkdiv == HALF_SPEED_CLKDIV) {
*retval = HALF_SPEED;
} else if (clkdiv == QUARTER_SPEED_CLKDIV) {
*retval = QUARTER_SPEED;
} else {
return FAIL;
}
return OK;
}
int setBadChannels(int numChannels, int *channelList) {
LOG(logINFO, ("Setting %d bad channels\n", numChannels));
memset(badChannelMask, 0, NCHAN_PER_MODULE * sizeof(char));

35
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -57,15 +57,16 @@
#define DEFAULT_SETTINGS (STANDARD)
#define DEFAULT_TRIMBIT_VALUE (0)
#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
#define DEFAULT_READOUT_SPEED (HALF_SPEED)
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (6) //(166666666) // str_clk, 166 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define DEFAULT_READOUT_C0_STARTUP (20) //(50000000) // rdo_clk, 50 MHz
#define FULL_SPEED_CLKDIV (10) //(100000000) 100 MHz
#define HALF_SPEED_CLKDIV (20) //( 50000000) 50 MHz
#define QUARTER_SPEED_CLKDIV (40) //( 25000000) 25 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
@ -73,12 +74,11 @@
#define DEFAULT_ADIF_ADD_OFST_VAL (0)
/* Firmware Definitions */
#define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_NUM_DESERIALIZERS (40)
#define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_NUM_DESERIALIZERS (40)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
@ -140,19 +140,12 @@ enum ADCINDEX { TEMP_FPGA };
#define SPECIAL_DEFAULT_HIGHGAIN_DAC_VALS \
{ 1300, 1100 }
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
NUM_CLOCKS
};
#define NUM_CLOCKS_TO_SET (3)
enum CLKINDEX { SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS };
#define NUM_CLOCKS_TO_SET (1)
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
#define CLK_NAMES "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
#define SYSTEM_PLL (1)
/* Struct Definitions */
typedef struct udp_header_struct {

3
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
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@ -655,7 +655,8 @@ int setClockDivider(enum CLKINDEX ind, int val);
int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
int timeUpdate);
int getClockDivider(enum CLKINDEX ind);
int setReadoutSpeed(int val);
int getReadoutSpeed(int *retval);
#elif GOTTHARD2D
int checkDetectorType(char *mess);
int powerChip(int on, char *mess);

15
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
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@ -6009,11 +6009,9 @@ int get_clock_frequency(int file_des) {
case ADC_CLOCK:
c = ADC_CLK;
break;
#ifdef CHIPTESTBOARDD
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
case RUN_CLOCK:
c = RUN_CLK;
break;
@ -6078,7 +6076,11 @@ int set_clock_phase(int file_des) {
#endif
default:
#if defined(GOTTHARD2D) || defined(MYTHEN3D)
if (ind < NUM_CLOCKS) {
#ifdef MYTHEN3D
if (args[0] < NUM_CLOCKS_TO_SET) {
#else
if (args[0] < NUM_CLOCKS) {
#endif
c = (enum CLKINDEX)ind;
break;
}
@ -9687,7 +9689,7 @@ int get_readout_speed(int file_des) {
LOG(logDEBUG1, ("Getting readout speed\n"));
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(EIGERD) && \
!defined(GOTTHARD2D)
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
// get only
@ -9711,7 +9713,7 @@ int set_readout_speed(int file_des) {
LOG(logDEBUG1, ("Setting readout speed : %u\n", arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(EIGERD) && \
!defined(GOTTHARD2D)
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
// only set
@ -9727,7 +9729,8 @@ int set_readout_speed(int file_des) {
#endif
if (ret == OK) {
switch (arg) {
#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(MYTHEN3D)
case FULL_SPEED:
case HALF_SPEED:
case QUARTER_SPEED:

10
slsDetectorSoftware/generator/commands.yaml
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@ -2904,7 +2904,7 @@ exptime3:
value: 2
readoutspeed:
help: "\n\t[0 or full_speed|1 or half_speed|2 or quarter_speed]\n\t[Eiger][Jungfrau][Moench] Readout speed of chip.\n\t[Eiger][Moench] Default speed is full_speed.\n\t[Jungfrau] Default speed is half_speed. full_speed option only available from v2.0 boards and is recommended to set number of interfaces to 2. Also overwrites adcphase to recommended default.\n\t [144|108]\n\t\t[Gotthard2] Readout speed of chip in MHz. Default is 108."
help: "\n\t[0 or full_speed|1 or half_speed|2 or quarter_speed]\n\t[Eiger][Jungfrau][Moench][Mythen3] Readout speed of chip.\n\t[Eiger][Moench] Default speed is full_speed.\n\t[Jungfrau][Mythen3] Default speed is half_speed. \n\t[Jungfrau] full_speed option only available from v2.0 boards and is recommended to set number of interfaces to 2. Also overwrites adcphase to recommended default.\n\t [144|108]\n\t\t[Gotthard2] Readout speed of chip in MHz. Default is 108."
actions:
GET:
extra_variables:
@ -3044,7 +3044,7 @@ dbitphase:
output: [ 'args[0]',"' '", 'args[1]' ]
clkfreq:
help: "[n_clock (0-5)] [freq_in_Hz]\n\t[Gotthard2][Mythen3] Frequency of clock n_clock in Hz. Use clkdiv to set frequency."
help: "[n_clock] [freq_in_Hz]\n\t[Gotthard2][Mythen3] Frequency of clock n_clock in Hz. Use clkdiv to set frequency.\n\t[Gotthard2] Clock index range: 0-5\n\t[Mythen3] Clock index range: 0"
actions:
GET:
extra_variables:
@ -3063,7 +3063,7 @@ clkfreq:
output: [ OutString(t) ]
clkphase:
help: "[n_clock (0-5)] [phase] [deg (optional)]\n\t[Gotthard2][Mythen3] Phase of clock n_clock. If deg, then phase shift in degrees, else absolute phase shift values."
help: "[n_clock] [phase] [deg (optional)]\n\t[Gotthard2][Mythen3] Phase of clock n_clock. If deg, then phase shift in degrees, else absolute phase shift values.n\t[Gotthard2] Clock index range: 0-5\n\t[Mythen3] Clock index range: 0"
actions:
GET:
extra_variables:
@ -3118,7 +3118,7 @@ clkphase:
output: [ 'args[1]', '" "', 'args[2]' ]
maxclkphaseshift:
help: "[n_clock (0-5)]\n\t[Gotthard2][Mythen3] Absolute Maximum Phase shift of clock n_clock."
help: "[n_clock]\n\t[Gotthard2][Mythen3] Absolute Maximum Phase shift of clock n_clock.n\t[Gotthard2] Clock index range: 0-5\n\t[Mythen3] Clock index range: 0"
actions:
GET:
extra_variables:
@ -3137,7 +3137,7 @@ maxclkphaseshift:
function: getMaxClockPhaseShift
clkdiv:
help: "[n_clock (0-5)] [n_divider]\n\t[Gotthard2][Mythen3] Clock Divider of clock n_clock. Must be greater than 1."
help: "[n_clock] [n_divider]\n\t[Gotthard2][Mythen3] Clock Divider of clock n_clock. Must be greater than 1.n\t[Gotthard2] Clock index range: 0-5\n\t[Mythen3] Clock index range: 0"
actions:
GET:
extra_variables:

13
slsDetectorSoftware/include/sls/Detector.h
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@ -363,11 +363,11 @@ class Detector {
/** list of possible timing modes for this detector */
std::vector<defs::timingMode> getTimingModeList() const;
/** [Eiger][Jungfrau][Moench][Gotthard2] */
/** [Eiger][Jungfrau][Moench][Gotthard2][Mythen3] */
Result<defs::speedLevel> getReadoutSpeed(Positions pos = {}) const;
/** [Eiger][Jungfrau][Moench][Gotthard2]
* [Jungfrau] Options: FULL_SPEED, HALF_SPEED (Default),
* [Jungfrau][Mythen3] Options: FULL_SPEED, HALF_SPEED (Default),
* QUARTER_SPEED \n [Moench] Options: FULL_SPEED (Default) \n [Eiger]
* Options: FULL_SPEED (Default), HALF_SPEED, QUARTER_SPEED \n [Gotthard2]
* Options: G2_108MHZ (Default), G2_144MHZ \n [Jungfrau][Moench] FULL_SPEED
@ -429,7 +429,8 @@ class Detector {
/** [Mythen3][Gotthard2] */
Result<int> getClockPhase(int clkIndex, Positions pos = {});
/** [Mythen3][Gotthard2] absolute phase shift */
/** [Mythen3][Gotthard2] absolute phase shift \n
* [Gotthard2] clkIndex: 0-5, [Mythen3] clkIndex 0 only */
void setClockPhase(int clkIndex, int value, Positions pos = {});
/** [Mythen3][Gotthard2] */
@ -438,13 +439,15 @@ class Detector {
/** [Mythen3][Gotthard2] */
Result<int> getClockPhaseinDegrees(int clkIndex, Positions pos = {});
/** [Mythen3][Gotthard2] */
/** [Mythen3][Gotthard2] \n
* [Gotthard2] clkIndex: 0-5, [Mythen3] clkIndex 0 only */
void setClockPhaseinDegrees(int clkIndex, int value, Positions pos = {});
/** [Mythen3][Gotthard2] */
Result<int> getClockDivider(int clkIndex, Positions pos = {});
/** [Mythen3][Gotthard2] Must be greater than 1. */
/** [Mythen3][Gotthard2] Must be greater than 1. \n
* [Gotthard2] clkIndex: 0-5, [Mythen3] clkIndex 0 only */
void setClockDivider(int clkIndex, int value, Positions pos = {});
Result<int> getHighVoltage(Positions pos = {}) const;

1
slsDetectorSoftware/src/Detector.cpp
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@ -533,6 +533,7 @@ std::vector<defs::speedLevel> Detector::getReadoutSpeedList() const {
case defs::EIGER:
case defs::JUNGFRAU:
case defs::MOENCH:
case defs::MYTHEN3:
return std::vector<defs::speedLevel>{defs::FULL_SPEED, defs::HALF_SPEED,
defs::QUARTER_SPEED};
case defs::GOTTHARD2:

44
slsDetectorSoftware/tests/Caller/test-Caller.cpp
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@ -1101,14 +1101,16 @@ TEST_CASE("CALLER::readoutspeed", "[.cmdcall]") {
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::EIGER || det_type == defs::JUNGFRAU ||
det_type == defs::MOENCH || det_type == defs::GOTTHARD2) {
det_type == defs::MOENCH || det_type == defs::GOTTHARD2 ||
det_type == defs::MYTHEN3) {
auto prev_val = det.getReadoutSpeed();
// full speed for jungfrau/moench only works for new boards (chipv1.1 is
// with new board [hw1.0 and chipv1.0 not tested here])
if (((det_type == defs::JUNGFRAU) &&
det.getChipVersion().squash() * 10 == 11) ||
(det_type == defs::EIGER) || (det_type == defs::MOENCH)) {
det_type == defs::EIGER || det_type == defs::MOENCH ||
det_type == defs::MYTHEN3) {
std::ostringstream oss1, oss2, oss3, oss4;
caller.call("readoutspeed", {"0"}, -1, PUT, oss1);
REQUIRE(oss1.str() == "readoutspeed full_speed\n");
@ -1121,7 +1123,7 @@ TEST_CASE("CALLER::readoutspeed", "[.cmdcall]") {
}
if (det_type == defs::EIGER || det_type == defs::JUNGFRAU ||
det_type == defs::MOENCH) {
det_type == defs::MOENCH || det_type == defs::MYTHEN3) {
{
std::ostringstream oss1, oss2, oss3, oss4;
caller.call("readoutspeed", {"1"}, -1, PUT, oss1);
@ -1189,7 +1191,8 @@ TEST_CASE("CALLER::readoutspeedlist", "[.cmdcall]") {
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::GOTTHARD2 || det_type == defs::JUNGFRAU ||
det_type == defs::MOENCH || det_type == defs::EIGER) {
det_type == defs::MOENCH || det_type == defs::EIGER ||
det_type == defs::MYTHEN3) {
REQUIRE_NOTHROW(caller.call("readoutspeedlist", {}, -1, GET));
REQUIRE_THROWS(caller.call("readoutspeedlist", {}, -1, PUT));
} else {
@ -1301,6 +1304,12 @@ TEST_CASE("CALLER::clkfreq", "[.cmdcall]") {
REQUIRE_THROWS(caller.call("clkfreq", {}, -1, GET));
REQUIRE_THROWS(caller.call("clkfreq", {"7"}, -1, GET));
REQUIRE_NOTHROW(caller.call("clkfreq", {"0"}, -1, GET));
// other clocks removed for m3 (setting not supported)
if (det_type == defs::MYTHEN3) {
REQUIRE_NOTHROW(caller.call("clkfreq", {"1"}, -1, GET));
REQUIRE_NOTHROW(caller.call("clkfreq", {"2"}, -1, GET));
REQUIRE_THROWS(caller.call("clkfreq", {"3"}, -1, GET));
}
} else {
REQUIRE_THROWS(caller.call("clkfreq", {"0"}, -1, GET));
}
@ -1339,6 +1348,18 @@ TEST_CASE("CALLER::clkphase", "[.cmdcall]") {
for (int i = 0; i != det.size(); ++i) {
det.setClockPhase(0, prev_val[i], {i});
}
// other clocks removed for m3 (setting not supported)
if (det_type == defs::MYTHEN3) {
REQUIRE_THROWS(
caller.call("clkphase", {"1", s_deg_val, "deg"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("clkphase", {"1"}, -1, GET));
REQUIRE_THROWS(
caller.call("clkphase", {"2", s_deg_val, "deg"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("clkphase", {"2"}, -1, GET));
REQUIRE_THROWS(
caller.call("clkphase", {"3", s_deg_val, "deg"}, -1, PUT));
REQUIRE_THROWS(caller.call("clkphase", {"3"}, -1, GET));
}
} else {
REQUIRE_THROWS(caller.call("clkphase", {"0"}, -1, GET));
}
@ -1365,6 +1386,15 @@ TEST_CASE("CALLER::clkdiv", "[.cmdcall]") {
for (int i = 0; i != det.size(); ++i) {
det.setClockDivider(0, prev_val[i], {i});
}
// other clocks removed for m3 (setting not supported)
if (det_type == defs::MYTHEN3) {
REQUIRE_THROWS(caller.call("clkdiv", {"1", "2"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("clkdiv", {"1"}, -1, GET));
REQUIRE_THROWS(caller.call("clkdiv", {"2", "2"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("clkdiv", {"2"}, -1, GET));
REQUIRE_THROWS(caller.call("clkdiv", {"3", "2"}, -1, PUT));
REQUIRE_THROWS(caller.call("clkdiv", {"3"}, -1, GET));
}
} else {
REQUIRE_THROWS(caller.call("clkdiv", {"0"}, -1, GET));
}
@ -1379,6 +1409,12 @@ TEST_CASE("CALLER::maxclkphaseshift", "[.cmdcall]") {
REQUIRE_THROWS(caller.call("maxclkphaseshift", {}, -1, GET));
REQUIRE_THROWS(caller.call("maxclkphaseshift", {"7"}, -1, GET));
REQUIRE_NOTHROW(caller.call("maxclkphaseshift", {"0"}, -1, GET));
// other clocks removed for m3 (setting not supported)
if (det_type == defs::MYTHEN3) {
REQUIRE_NOTHROW(caller.call("maxclkphaseshift", {"1"}, -1, GET));
REQUIRE_NOTHROW(caller.call("maxclkphaseshift", {"2"}, -1, GET));
REQUIRE_THROWS(caller.call("maxclkphaseshift", {"3"}, -1, GET));
}
} else {
REQUIRE_THROWS(caller.call("maxclkphaseshift", {"0"}, -1, GET));
}

2
slsSupportLib/include/sls/versionAPI.h
View File

@ -7,8 +7,8 @@
#define APICTB "developer 0x240918"
#define APIGOTTHARD "developer 0x240918"
#define APIGOTTHARD2 "developer 0x240918"
#define APIMYTHEN3 "developer 0x240918"
#define APIMOENCH "developer 0x240918"
#define APIXILINXCTB "developer 0x240918"
#define APIEIGER "developer 0x240918"
#define APIJUNGFRAU "developer 0x240930"
#define APIMYTHEN3 "developer 0x240930"