Doc: Typo

measurement core

hdl/evr320_decoder.vhd

@@ -180,6 +180,7 @@ architecture behavioral of evr320_decoder is
    signal   mem_data_wren               : std_logic := '0';
    signal   mem_data_wr_addr            : std_logic_vector(10 downto  0) := (others => '0');
    signal   mem_data_wr_byte            : std_logic_vector( 7 downto  0) := (others => '0');
+   signal   mem_data                    : std_logic_vector(11+8-1 downto 0);
    -- Data memory read      
    signal   mem_data_dpram              : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
    signal   mem_data_event0             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
@@ -709,6 +710,9 @@ begin
    mem_data_wr_addr               <= frame_data_rd_addr;
    mem_data_wr_byte               <= frame_data_rd_byte;
 
+   -- concatenate - this avoids an internal error in ghdl v0.37!
+   mem_data                       <= mem_data_wr_addr & mem_data_wr_byte;
+
    -----------------------------------------------------------------------------
    -- Address delay for read data mux
    -----------------------------------------------------------------------------
@@ -870,7 +874,7 @@ begin
       OutRst  => '0',
       
       -- Input Data
-      InData  => mem_data_wr_addr & mem_data_wr_byte,
+      InData  => mem_data,
       InVld   => mem_data_wren,
       InRdy   => open,
       

hdl/evr320_ifc1210_wrapper.vhd

@@ -104,8 +104,10 @@ architecture rtl of evr320_ifc1210_wrapper is
   signal event_recorder_control       : typ_evt_rec_ctrl;
   signal event_recorder_control_sync  : typ_evt_rec_ctrl;
   signal event_recorder_control_xuser : typ_evt_rec_ctrl;
-  signal evr_latency_measure_stat     : typ_rec_latency_measure_stat;
-  signal evr_latency_measure_ctrl     : typ_rec_latency_measure_ctrl;
+  signal evr_latency_measure_A_stat   : typ_rec_latency_measure_stat;
+  signal evr_latency_measure_A_ctrl   : typ_rec_latency_measure_ctrl;
+  signal evr_latency_measure_B_stat   : typ_rec_latency_measure_stat;
+  signal evr_latency_measure_B_ctrl   : typ_rec_latency_measure_ctrl;
   signal evr_frequency                : std_logic_vector(31 downto 0) := (others => '0');
   signal debug_data                   : std_logic_vector(127 downto 0);
   signal decoder_event_valid          : std_logic;
@@ -239,8 +241,10 @@ begin
       evr_frequency_i            => evr_frequency,
       evr_evt_rec_status_i       => event_recorder_status,
       evr_evt_rec_control_o      => event_recorder_control_xuser,
-      evr_latency_measure_stat_i => evr_latency_measure_stat,
-      evr_latency_measure_ctrl_o => evr_latency_measure_ctrl,
+      evr_latency_measure_A_stat_i => evr_latency_measure_A_stat,
+      evr_latency_measure_A_ctrl_o => evr_latency_measure_A_ctrl,
+      evr_latency_measure_B_stat_i => evr_latency_measure_B_stat,
+      evr_latency_measure_B_ctrl_o => evr_latency_measure_B_ctrl,
       mgt_status_i               => mgt_status,
       mgt_reset_o                => mgt_reset_tmem_evr,
       mem_clk_o                  => mem_clk,
@@ -268,70 +272,33 @@ begin
     );
 
   -- --------------------------------------------------------------------------
-  -- Event Latency Measurement for SW tests
+  -- Latency Measurement for IFC1210 Interrupts
   -- --------------------------------------------------------------------------
-  lat_meas_block : block
-    type state_type is (armed, count);
-    signal state                   : state_type;
-    signal counter                 : unsigned(31 downto 0);
-    signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
-    signal event_detected          : std_logic_vector(3 downto 0);
-    signal event_detected_sync     : std_logic_vector(1 downto 0);
-    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 100, 32); -- MAX 10ms
-  begin
+  latency_meas_A_inst : entity work.latency_measurement
+    generic map(
+      CLK_FREQ_HZ  => g_XUSER_CLK_FREQ
+    )
+    port map(
+    evr_clk_i             => clk_evr,
+    xuser_clk_i           => xuser_CLK,
+    decoder_event_valid_i => decoder_event_valid,
+    decoder_event_i       => decoder_event,
+    status_o              => evr_latency_measure_A_stat,
+    ctrl_i                => evr_latency_measure_A_ctrl
+    );
 
-    -- Process: filter events for matching event_nr register:
-    ---------------------------------------------------------
-    ext_event_proc : process(clk_evr)
-    begin
-      if (rising_edge(clk_evr)) then
-        -- sync to MGT clock domain:
-        event_nr_sync <= evr_latency_measure_ctrl.event_nr;
-        event_nr      <= event_nr_sync;
-
-        -- check if event has been detected and stretch pulse: 
-        event_detected <= event_detected(2 downto 0) & '0';
-        if (decoder_event_valid = '1' and decoder_event = event_nr) then
-          event_detected <= (others => '1');
-        end if;
-      end if;
-    end process;
-
-    -- Process: Counter when configured event has been detected:
-    ------------------------------------------------------------
-    lat_meas_proc : process(xuser_CLK, counter)
-    begin
-      if rising_edge(xuser_CLK) then
-        -- sync to user clock domain:
-        event_detected_sync <= event_detected_sync(0) & event_detected(3);
-
-        -- counter FSM:
-        ---------------
-        case state is
-          -- counter is armed:
-          when armed =>
-            counter <= (others => '0');
-            -- start counting when event detected (rising edge):
-            if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
-              state <= count;
-            end if;
-
-          -- counting:
-          when count =>
-            -- count only up to 10ms, and stop:
-            if (counter < MAX_COUNT) then
-              counter <= counter + 1;
-            end if;
-            if (evr_latency_measure_ctrl.counter_arm = '1') then
-              state <= armed;
-            end if;
-        end case;
-      end if;
-
-      evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
-    end process;
-
-  end block;
+  latency_meas_B_inst : entity work.latency_measurement
+    generic map(
+      CLK_FREQ_HZ  => g_XUSER_CLK_FREQ
+    )
+    port map(
+    evr_clk_i             => clk_evr,
+    xuser_clk_i           => xuser_CLK,
+    decoder_event_valid_i => decoder_event_valid,
+    decoder_event_i       => decoder_event,
+    status_o              => evr_latency_measure_B_stat,
+    ctrl_i                => evr_latency_measure_B_ctrl
+    );
 
   -- --------------------------------------------------------------------------
   -- Add delay output
@@ -341,13 +308,21 @@ begin
     signal usr_evt_shaped_s    : std_logic_vector(4 downto 0);
     signal usr_events_adj_s    : std_logic_vector(4 downto 0);
     signal usr_events_concat_s : std_logic_vector(4 downto 0);
+    signal mmcm_locked         : std_logic;
+    signal rxpll_locked        : std_logic;
+    signal evr_rst_in          : std_logic;
 
   begin
+
+    rxpll_locked <= mgt_status(1);
+    mmcm_locked  <= mgt_status(2);
+    evr_rst_in   <= xuser_RESET or (not rxpll_locked) or (not mmcm_locked);
+
     --*** double stage sync for reset ***--
     proc_rst : process(clk_evr)
     begin
       if rising_edge(clk_evr) then
-        rst0_s <= xuser_RESET;
+        rst0_s <= evr_rst_in;
         rst1_s <= rst0_s;
       end if;
     end process;

hdl/evr320_pkg.vhd

@@ -12,6 +12,7 @@
 --------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use work.psi_common_math_pkg.all;
 
 package evr320_pkg is
@@ -19,9 +20,9 @@ package evr320_pkg is
   -- --------------------------------------------------------------------------
   -- Constants                                                    
   -- --------------------------------------------------------------------------
-  constant c_CHECKSUM_MIN_EVT     : std_logic_vector(31 downto 0)   := X"00000064"; -- Check sum min count for events 100
-  constant c_CHECKSUM_MIN_TIME    : std_logic_vector(31 downto 0)   := X"0015CA20"; -- Check sum min time for events 10 ms
-  constant c_SOS_EVENT_DEFAULT    : std_logic_vector( 7 downto 0)   := X"20";       -- decimal 32
+  constant c_CHECKSUM_MIN_EVT       : std_logic_vector(31 downto 0)   := X"00000064"; -- Check sum min count for events 100
+  constant c_CHECKSUM_MIN_TIME      : std_logic_vector(31 downto 0)   := X"0015CA20"; -- Check sum min time for events 10 ms
+  constant c_SOS_EVENT_DEFAULT      : std_logic_vector( 7 downto 0)   := X"26";       -- default start-of-sequence (SOS) event
   
  
   -- --------------------------------------------------------------------------
@@ -60,14 +61,17 @@ package evr320_pkg is
 
   type typ_rec_latency_measure_stat is record
     counter_val          : std_logic_vector(31 downto 0);
+    event_detected       : std_logic;
   end record;
   
   --*** Type record and constant for new feature pulse width & delay ***
-  constant MaxDuration_c  : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles 
-  constant MaxDelay_c     : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles 
+  constant MaxDuration_c          : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles 
+  constant MaxDelay_c             : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles 
+  constant UsrEventWidthDefault_c : std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0) := std_logic_vector(to_unsigned(4, log2ceil(MaxDuration_c)));  -- default pulse width of usr_events_adj_o
   type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
   type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
   
+  
   -- --------------------------------------------------------------------------
   -- Type Initialisation                                                      
   -- --------------------------------------------------------------------------
@@ -82,7 +86,8 @@ package evr320_pkg is
 
   constant c_INIT_REC_LATENCY_MEASURE_CTRL : typ_rec_latency_measure_ctrl :=  (event_nr    => (others =>'0'),
                                                                                counter_arm => '1'); 
-  constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat :=  (counter_val => (others =>'0'));
+  constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat :=  (counter_val => (others =>'0'),
+                                                                                event_detected => '0');
   -- --------------------------------------------------------------------------
   -- Function Prototypes
   -- --------------------------------------------------------------------------

hdl/evr320_tmem.vhd

@@ -37,9 +37,11 @@ entity evr320_tmem is
     evr_frequency_i               : in    std_logic_vector(31 downto  0);
     evr_evt_rec_status_i          : in    typ_evt_rec_status;           
     evr_evt_rec_control_o         : out   typ_evt_rec_ctrl;           
-    evr_latency_measure_stat_i    : in    typ_rec_latency_measure_stat;
-    evr_latency_measure_ctrl_o    : out   typ_rec_latency_measure_ctrl;
-    mgt_status_i                  : in    std_logic_vector(31 downto  0);          
+    evr_latency_measure_A_stat_i  : in    typ_rec_latency_measure_stat;
+    evr_latency_measure_A_ctrl_o  : out   typ_rec_latency_measure_ctrl;
+    evr_latency_measure_B_stat_i  : in    typ_rec_latency_measure_stat;
+    evr_latency_measure_B_ctrl_o  : out   typ_rec_latency_measure_ctrl;
+    mgt_status_i                  : in    std_logic_vector(31 downto  0) := (others=>'0');
     mgt_reset_o                   : out   std_logic;          
     mem_clk_o                     : out   std_logic; 
     mem_addr_o                    : out   std_logic_vector(10 downto  0); 
@@ -102,18 +104,15 @@ architecture rtl of evr320_tmem is
   signal er_control_concat      : std_logic_vector(31 downto 0)   := (others => '0');
 
   -- latency measurement
-  signal lat_counter_arm        : std_logic                       := '0'; 
-  signal lat_event_nr           : std_logic_vector(7 downto 0)    := x"26";  -- default SOS event
-  signal lat_counter_val        : std_logic_vector(31 downto 0)   := (others=>'0'); 
+  signal lat_A_counter_arm, lat_B_counter_arm           : std_logic                       := '0'; 
+  signal lat_A_event_nr, lat_B_event_nr                 : std_logic_vector(7 downto 0)    := c_SOS_EVENT_DEFAULT;
+  signal lat_A_event_detected, lat_B_event_detected     : std_logic_vector(7 downto 0);
+  signal lat_A_arm, lat_B_arm                           : std_logic := '0';
+  signal lat_A_arm_edge, lat_B_arm_edge                 : std_logic_vector(1 downto 0)    := (others=>'0');
 
-  -- signal evr_force              : std_logic_vector(3 downto 0)    := (others => '0');
-  -- signal evr_force_rd           : std_logic_vector(3 downto 0)    := (others => '0');  -- readback
-  -- signal evr_force_pulse        : typ_arr4(3 downto 0)            := (others => (others => '0'));
-  
   -- event pulse config
-  
-  signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
-  signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
+  signal evr_puls_width_cfg_s : typ_arr_width := (others => UsrEventWidthDefault_c);
+  signal evr_puls_delay_cfg_s : typ_arr_delay := (others => (others => '0'));
 
 -- ----------------------------------------------------------------------------
 -- ----------------------------------------------------------------------------
@@ -128,7 +127,34 @@ begin
   event_numbers_concat  <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
   er_handshake_status   <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
   er_control_concat     <= X"0000" & er_event_number & bit2byte(er_event_enable);
-  lat_counter_val       <= evr_latency_measure_stat_i.counter_val;
+
+  -- -----------------------------
+  -- latency measurement, arm 
+  -- -----------------------------
+  process (xuser_CLK)
+  begin
+    if rising_edge(xuser_CLK) then
+      -- edge detection of latency arm:
+      lat_A_arm_edge <= lat_A_arm_edge(0) & lat_A_arm;
+      lat_A_counter_arm <= lat_A_arm_edge(0) and not lat_A_arm_edge(1);
+      lat_B_arm_edge <= lat_B_arm_edge(0) & lat_B_arm;
+      lat_B_counter_arm <= lat_B_arm_edge(0) and not lat_B_arm_edge(1);
+
+      if (evr_latency_measure_A_stat_i.event_detected = '1') then
+        lat_A_event_detected  <= (others=>'1');
+      end if;
+      if (lat_A_counter_arm = '1') then
+        lat_A_event_detected  <= (others=>'0');
+      end if;
+
+      if (evr_latency_measure_B_stat_i.event_detected = '1') then
+        lat_B_event_detected  <= (others=>'1');
+      end if;
+      if (lat_B_counter_arm = '1') then
+        lat_B_event_detected  <= (others=>'0');
+      end if;
+    end if;
+  end process;
   
   -- --------------------------------------------------------------------------
   -- Synchronisation to xuser_CLK                                                      
@@ -157,21 +183,24 @@ begin
   -- --------------------------------------------------------------------------
   -- Read operation                                                       
   -- --------------------------------------------------------------------------
+  blk_tmemrd : block
+
+  begin
   read_tmem_evr: process(xuser_CLK)
   begin
     if (rising_edge(xuser_CLK)) then
-      lat_counter_arm <= '0';
       if (xuser_TMEM_ENA_reg = '1') then
         if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
           case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
             when X"0" =>    xuser_TMEM_DATR <=  event_numbers_concat       & X"0000" & mgt_status_evr;           -- 64bit / ByteAddr 000
             when X"1" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & X"0000_00" & bit2byte(mgt_reset);   -- 64bit / ByteAddr 008   --> 0x00C = not implemented in ifc1210
-            when X"2" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & bit2byte(event_enable);             -- 64bit / ByteAddr 010   --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...  evr_force
+            when X"2" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & bit2byte(event_enable);             -- 64bit / ByteAddr 010   --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...
             when X"3" =>    xuser_TMEM_DATR <=  evr_frequency              & reserved(31 downto 0);              -- 64bit / ByteAddr 018   --> 0x018 = Implementation Options + c_EVR_Location_vec 
             when X"4" =>    xuser_TMEM_DATR <=  cs_min_time                & cs_min_cnt;                         -- 64bit / ByteAddr 020
             when X"5" =>    xuser_TMEM_DATR <=  reserved(63 downto 0);                                           -- 64bit / ByteAddr 028
-            when X"6" =>    xuser_TMEM_DATR <=  lat_counter_val            & X"000000" & lat_event_nr;           -- 64bit / ByteAddr 030
-            when X"7" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
+            when X"6" =>    xuser_TMEM_DATR <=  evr_latency_measure_A_stat_i.counter_val   & 
+                                                lat_B_event_detected & lat_A_event_detected & lat_B_event_nr & lat_A_event_nr;               -- 64bit / ByteAddr 030
+            when X"7" =>    xuser_TMEM_DATR <=  evr_latency_measure_B_stat_i.counter_val   & reserved(31 downto 0);              -- 64bit / ByteAddr 038
             when X"8" =>    xuser_TMEM_DATR <=  er_handshake_status        & er_control_concat;                  -- 64bit / ByteAddr 040                
             when X"9" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & er_status.usr_events_counter;       -- 64bit / ByteAddr 048   
             when X"A" =>    xuser_TMEM_DATR <=  evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050   
@@ -186,6 +215,7 @@ begin
     end if;
   end process;
 
+  end block;
   
   -- --------------------------------------------------------------------------
   -- Write operation  - Byte control                                           
@@ -197,6 +227,8 @@ begin
       -- default assignments
       er_data_ack   <= er_data_ack(2 downto 0) & '0';
       er_error_ack  <= er_error_ack(2 downto 0) & '0';
+      lat_A_arm <= '0';
+      lat_B_arm <= '0';
 
       
       if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
@@ -246,8 +278,21 @@ begin
         end if;
         -----------------------------------------------------------------------------------------------------------------
         if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030   Latency Measurement
-          if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto  0)    <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
-       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto  8)      <= xuser_TMEM_DATW_reg(15 downto  8); end if;
+          if xuser_TMEM_WE_reg(0) = '1' then lat_A_event_nr ( 7 downto  0)  <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
+          if xuser_TMEM_WE_reg(1) = '1' then lat_B_event_nr ( 7 downto  0)  <= xuser_TMEM_DATW_reg(15 downto  8); end if; 
+       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8)       <= xuser_TMEM_DATW_reg(15 downto 8); end if;
+       -- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(23 downto 16); end if;
+       -- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(31 downto 24); end if;
+       -- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto  0)      <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+       -- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto  8)      <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+       -- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(55 downto 48); end if;
+       -- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(63 downto 56); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"7" then --ByteAddr 038   Latency Measurement
+          if xuser_TMEM_WE_reg(0) = '1' then lat_A_arm                      <= xuser_TMEM_DATW_reg(0); end if;
+          if xuser_TMEM_WE_reg(1) = '1' then lat_B_arm                      <= xuser_TMEM_DATW_reg(8); end if;
+       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8)       <= xuser_TMEM_DATW_reg(15 downto 8); end if;
        -- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(23 downto 16); end if;
        -- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(31 downto 24); end if;
        -- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto  0)      <= xuser_TMEM_DATW_reg(39 downto 32); end if;
@@ -298,7 +343,8 @@ begin
   evr_params_o                <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
   evr_evt_rec_control_o       <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
   mgt_reset_o                 <= mgt_reset;
-  evr_latency_measure_ctrl_o  <= (lat_event_nr, lat_counter_arm);
+  evr_latency_measure_A_ctrl_o  <= (lat_A_event_nr, lat_A_counter_arm);
+  evr_latency_measure_B_ctrl_o  <= (lat_B_event_nr, lat_B_counter_arm);
 
   -- --------------------------------------------------------------------------
   -- add CDC output
@@ -349,6 +395,4 @@ begin
   end block;
 
 end rtl;
--- ----------------------------------------------------------------------------
--- ////////////////////////////////////////////////////////////////////////////
--- ----------------------------------------------------------------------------
+

hdl/latency_measurement.vhd

@@ -0,0 +1,98 @@
+ ---------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+-- ---------------------------------------------------------------------------
+-- Unit    : latency_measurement.vhd
+-- Author  : Jonas Purtschert
+-- ---------------------------------------------------------------------------
+-- Copyright© PSI, Section DSV
+-- ---------------------------------------------------------------------------
+-- Comment : Latency Measurement for IFC1210 Interrupt latency debugging
+-- ---------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+use work.evr320_pkg.all;
+
+entity latency_measurement is
+  generic (
+    CLK_FREQ_HZ : natural := 125000000 -- Xuser Clk Frequency in Hz
+  );
+  port (
+    evr_clk_i             : in std_logic;
+    xuser_clk_i           : in std_logic;
+    decoder_event_valid_i : in std_logic;
+    decoder_event_i       : in std_logic_vector(7 downto 0);
+    status_o              : out typ_rec_latency_measure_stat;
+    ctrl_i                : in typ_rec_latency_measure_ctrl
+  );
+end latency_measurement;
+
+architecture rtl of latency_measurement is
+
+  -- --------------------------------------------------------------------------
+  -- Signal, Types, Constants
+  -- --------------------------------------------------------------------------
+    type state_type is (armed, count);
+    signal state                   : state_type;
+    signal counter                 : unsigned(31 downto 0);
+    signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
+    signal event_detected          : std_logic_vector(3 downto 0);
+    signal event_detected_sync     : std_logic_vector(1 downto 0);
+    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(CLK_FREQ_HZ / 100, 32); -- MAX 10ms
+
+begin
+
+    -- Process: filter events for matching event_nr register:
+    ---------------------------------------------------------
+    ext_event_proc : process(evr_clk_i)
+    begin
+      if (rising_edge(evr_clk_i)) then
+        -- sync to MGT clock domain:
+        event_nr_sync <= ctrl_i.event_nr;
+        event_nr      <= event_nr_sync;
+
+        -- check if event has been detected and stretch pulse: 
+        event_detected <= event_detected(2 downto 0) & '0';
+        if (decoder_event_valid_i = '1' and decoder_event_i = event_nr) then
+          event_detected <= (others => '1');
+        end if;
+      end if;
+    end process;
+
+    -- Process: Counter when configured event has been detected:
+    ------------------------------------------------------------
+    lat_meas_proc : process(xuser_clk_i, counter)
+    begin
+      if rising_edge(xuser_clk_i) then
+        -- sync to user clock domain:
+        event_detected_sync <= event_detected_sync(0) & event_detected(3);
+
+        -- counter FSM:
+        ---------------
+        case state is
+          -- counter is armed:
+          when armed =>
+            counter <= (others => '0');
+            -- start counting when event detected (rising edge):
+            if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
+              state <= count;
+            end if;
+
+          -- counting:
+          when count =>
+            -- count only up to 10ms, and stop:
+            if (counter < MAX_COUNT) then
+              counter <= counter + 1;
+            end if;
+            if (ctrl_i.counter_arm = '1') then
+              state <= armed;
+            end if;
+        end case;
+      end if;
+      status_o.counter_val <= std_logic_vector(counter);
+      status_o.event_detected <= event_detected_sync(event_detected_sync'left);
+    end process;
+
+end rtl;

hdl/v6vlx_gtxe1_wrapper.vhd

@@ -260,7 +260,7 @@ begin
       else
         case s_align_fsm is
           when align_idle =>
-            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
+            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' or o_mgt.rx.RXBYTEISALIGNED = '0' then
               s_align_fsm   <= align_slide;
             end if;
           when align_slide =>

sim/config.tcl

@@ -64,7 +64,6 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
 # EVR320 Decoder Testbench
 add_sources $LibPath/Firmware/VHDL/evr320/tb {
 	evr320_decoder_tb.vhd \
-	evr320_ifc1210_wrapper_tb.vhd \
 } -tag evr320_tb
 
 # EVR320 IFC1210 Wrapper Testbench

tb/evr320_decoder_tb.vhd

@@ -80,7 +80,7 @@ architecture testbench of evr320_decoder_tb is
   signal   usr_clk               : std_logic := '0';
   signal   evr_params            : typ_evr320_params;
   signal   mem_addr              : std_logic_vector(11 downto  0) := (others => '0');
-  signal   mem_data              : std_logic_vector(31 downto  0) := (others => '0');
+  signal   mem_data              : std_logic_vector(C_MEM_DATA_WIDTH-1 downto  0) := (others => '0');
   
   -- Decoder stream
   type dec_stream_type is record
@@ -169,12 +169,14 @@ begin
      --------------------------------------------------------------------------
      o_usr_events                => usr_events,
      o_usr_events_ext            => open,
-     o_sos_event                 => sos_event
+     o_sos_event                 => sos_event,
+     o_event                     => open,
+     o_event_valid               => open
   );
 
   evr320_data_filter_inst: entity work.evr320_data_filter
   generic map (
-    SWAP      => false 
+    SWAP      => true, -- non-swapped uses LE layout; our check below converts to BE
     NUM_BYTES => 8
   )
   port map (
@@ -399,7 +401,7 @@ begin
     variable i : integer := 0;
     type state is (idle, payload, frame_end, segment_nr);
     variable mem_base : integer range 0 to 127;
-    variable segment_data_word : std_logic_vector(31 downto 0);
+    variable segment_data_word : std_logic_vector(C_MEM_DATA_WIDTH-1 downto 0);
     variable var_filter_offset : integer range 0 to 2047;
     variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
     variable expected_evt_rec_events : integer range 0 to 255 := 0;
@@ -486,37 +488,51 @@ begin
         log(ID_DATA, "Check expected Event Flags after SOS Event detected");
         ----------------------------------------------------------------------
         wait until rising_edge(usr_clk);
-        for addr in 0 to 63 loop    
-          mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
-          wait until rising_edge(usr_clk);
-          await_value(mem_data(0),  all_expected_events(4*addr),     0 ns, 1 ns, ERROR, "Event " & to_string(4*addr)     & " Flag");
-          await_value(mem_data(8),  all_expected_events(4*addr + 1), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 1) & " Flag");
-          await_value(mem_data(16), all_expected_events(4*addr + 2), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 2) & " Flag");
-          await_value(mem_data(24), all_expected_events(4*addr + 3), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 3) & " Flag");
-        end loop;
-        
-        ----------------------------------------------------------------------
-        log(ID_DATA, "Check Memory block border");
-        ----------------------------------------------------------------------
-        -- read data mux switching made visible with delayed address.
-        mem_addr <= C_EVENT_REC_FLAGS & "000000";
-        wait until rising_edge(usr_clk);
-        wait for C_USRCLK_CYCLE/4;
-        for addr in 62 to 65 loop    
-          mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
-          wait until rising_edge(usr_clk);
-          check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
-          wait for C_USRCLK_CYCLE/4;
-          if (addr < 64) then
+        if (C_MEM_DATA_WIDTH = 32) then
+          for addr in 0 to 63 loop    
+            mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
+            wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
             check_value(mem_data(0),  all_expected_events(4*addr),     ERROR, "Event " & to_string(4*addr)     & " Flag");
             check_value(mem_data(8),  all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
             check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
             check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
-          else
-            check_value(mem_data,  X"0000_0000", ERROR, "After Event Recorder Mem Map");
-          end if;
-        end loop;
+            wait until rising_edge(usr_clk);
+          end loop;
+        elsif (C_MEM_DATA_WIDTH = 64) then
+          for addr in 0 to 31 loop    
+            mem_addr <= '0' & C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 5));
+            wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
+            for j in 0 to C_MEM_DATA_WIDTH/8 loop
+              check_value(mem_data(8*j),  all_expected_events(8*addr + j),     ERROR, "Event " & to_string(8*addr + j)     & " Flag");
+            end loop;
+          end loop;
+        else
+          error("Unsupported width of C_MEM_DATA_WIDTH");
+        end if;
         
+        -- ----------------------------------------------------------------------
+        -- log(ID_DATA, "Check Memory block border");
+        -- ----------------------------------------------------------------------
+        if (C_MEM_DATA_WIDTH = 32) then
+          -- read data mux switching made visible with delayed address.
+          mem_addr <= C_EVENT_REC_FLAGS & "000000";
+          wait until rising_edge(usr_clk);
+          wait for C_USRCLK_CYCLE/4;
+          for addr in 62 to 65 loop    
+            mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
+            wait until rising_edge(usr_clk);
+            check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
+            wait for C_USRCLK_CYCLE/4;
+            if (addr < 64) then
+              check_value(mem_data(0),  all_expected_events(4*addr),     ERROR, "Event " & to_string(4*addr)     & " Flag");
+              check_value(mem_data(8),  all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
+              check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
+              check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
+            else
+              check_value(mem_data,  X"0000_0000", ERROR, "After Event Recorder Mem Map");
+            end if;
+          end loop;
+        end if;
         ----------------------------------------------------------------------
         log(ID_DATA, "Check expected Event Recorder User Events");
         ----------------------------------------------------------------------
@@ -528,22 +544,24 @@ begin
     --------------------------------------------------------------------------
     log(ID_LOG_HDR, "Read DPRAM buffer", C_SCOPE);
     --------------------------------------------------------------------------
-    wait for 50 * C_USRCLK_CYCLE;
-    log(ID_DATA, "Read Segment from DPRAM");
-    -- print 16 words from dpram data buffer:
-    for offset in 0 to segment_length/4-1 loop
-      mem_base := to_integer(unsigned(segment_addr));
-      mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
-      wait until rising_edge(usr_clk);
-      wait until rising_edge(usr_clk);
-      wait until rising_edge(usr_clk);
-      segment_data_word := segment_data(offset*4+3) 
-                            & segment_data(offset*4+2) 
-                            & segment_data(offset*4+1) 
-                            & segment_data(offset*4);
-      check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
-      --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
-    end loop;
+    if (C_MEM_DATA_WIDTH = 32) then
+      wait for 50 * C_USRCLK_CYCLE;
+      log(ID_DATA, "Read Segment from DPRAM");
+      -- print 16 words from dpram data buffer:
+      for offset in 0 to segment_length/4-1 loop
+        mem_base := to_integer(unsigned(segment_addr));
+        mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
+        wait until rising_edge(usr_clk);
+        wait until rising_edge(usr_clk);
+        wait until rising_edge(usr_clk);
+        segment_data_word := segment_data(offset*4+3) 
+                              & segment_data(offset*4+2) 
+                              & segment_data(offset*4+1) 
+                              & segment_data(offset*4);
+        check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
+        --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
+      end loop;
+    end if;
 
     --------------------------------------------------------------------------
     -- Test Done

tb/stimuli_mgt.dat

@@ -167,7 +167,7 @@ FE 0  00 0   event 254
 FF 0  00 0   event 255
 BC 1  00 0   align
 00 0  00 0   gap
-0F 0  00 0   gap
+00 0  00 0   gap
 00 0  00 0   gap
 BC 1  00 0   align
 00 0  00 0   gap