75 lines
2.3 KiB
C++
75 lines
2.3 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "hls_jfjoch.h"
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#define upside(x) ((RAW_MODULE_LINES - 1 - i / 32) * 32 + i % 32)
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void module_upside_down(STREAM_512 &data_in, STREAM_512 &data_out) {
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#pragma HLS INTERFACE axis register both port=data_in
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#pragma HLS INTERFACE axis register both port=data_out
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ap_uint<512> memory_0[16384];
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#pragma HLS BIND_STORAGE variable=memory_0 type=ram_t2p impl=uram latency=3
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ap_uint<512> memory_1[16384];
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#pragma HLS BIND_STORAGE variable=memory_1 type=ram_t2p impl=uram latency=3
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ap_uint<1> mem_0_full = 0;
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ap_uint<1> mem_1_full = 0;
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ap_uint<1> curr_mem = 0;
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packet_512_t packet_in, packet_out;
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data_in >> packet_in;
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ap_uint<1> reverse = ((ACT_REG_MODE(packet_in.data) & MODE_MODULE_UPSIDE_DOWN)) ? 1 : 0;
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data_out << packet_in;
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data_in >> packet_in;
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if (reverse) {
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while (!packet_in.user) {
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if (curr_mem == 0) {
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for (int i = 0; i < 16384; i++) {
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#pragma HLS PIPELINE II=1
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memory_0[i] = packet_in.data;
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if (mem_1_full) {
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packet_out.data = memory_1[upside(i)];
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data_out << packet_out;
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}
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data_in >> packet_in;
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}
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mem_0_full = 1;
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mem_1_full = 0;
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curr_mem = 1;
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} else {
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for (int i = 0; i < 16384; i++) {
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#pragma HLS PIPELINE II=1
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memory_1[i] = packet_in.data;
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if (mem_0_full) {
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packet_out.data = memory_0[upside(i)];
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data_out << packet_out;
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}
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data_in >> packet_in;
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}
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mem_0_full = 0;
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mem_1_full = 1;
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curr_mem = 0;
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}
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}
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drain_memory:
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for (int i = 0; i < 16384; i++) {
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#pragma HLS PIPELINE II=1
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if (mem_0_full)
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packet_out.data = memory_0[upside(i)];
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else
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packet_out.data = memory_1[upside(i)];
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data_out << packet_out;
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}
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} else {
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while (!packet_in.user) {
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#pragma HLS PIPELINE II=1
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data_out << packet_in;
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data_in >> packet_in;
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}
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}
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data_out << packet_in;
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}
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