// Copyright (2019-2023) Paul Scherrer Institute

#include "hls_jfjoch.h"

#define upside(x) ((RAW_MODULE_LINES - 1 - i / 32) * 32 + i % 32)

void module_upside_down(STREAM_512 &data_in, STREAM_512 &data_out) {
#pragma HLS INTERFACE axis register both port=data_in
#pragma HLS INTERFACE axis register both port=data_out

    ap_uint<512> memory_0[16384];
#pragma HLS BIND_STORAGE variable=memory_0 type=ram_t2p impl=uram latency=3
    ap_uint<512> memory_1[16384];
#pragma HLS BIND_STORAGE variable=memory_1 type=ram_t2p impl=uram latency=3

    ap_uint<1> mem_0_full = 0;
    ap_uint<1> mem_1_full = 0;
    ap_uint<1> curr_mem = 0;

    packet_512_t packet_in, packet_out;
    data_in >> packet_in;
    ap_uint<1> reverse = ((ACT_REG_MODE(packet_in.data) & MODE_MODULE_UPSIDE_DOWN)) ? 1 : 0;
    data_out << packet_in;

    data_in >> packet_in;
    if (reverse) {
        while (!packet_in.user) {
            if (curr_mem == 0) {
                for (int i = 0; i < 16384; i++) {
#pragma HLS PIPELINE II=1
                    memory_0[i] = packet_in.data;
                    if (mem_1_full) {
                        packet_out.data = memory_1[upside(i)];
                        data_out << packet_out;
                    }
                    data_in >> packet_in;
                }
                mem_0_full = 1;
                mem_1_full = 0;
                curr_mem = 1;
            } else {
                for (int i = 0; i < 16384; i++) {
#pragma HLS PIPELINE II=1
                    memory_1[i] = packet_in.data;
                    if (mem_0_full) {
                        packet_out.data = memory_0[upside(i)];
                        data_out << packet_out;
                    }
                    data_in >> packet_in;
                }
                mem_0_full = 0;
                mem_1_full = 1;
                curr_mem = 0;
            }
        }
        drain_memory:
        for (int i = 0; i < 16384; i++) {
#pragma HLS PIPELINE II=1
            if (mem_0_full)
                packet_out.data = memory_0[upside(i)];
            else
                packet_out.data = memory_1[upside(i)];
            data_out << packet_out;
        }

    } else {
        while (!packet_in.user) {
#pragma HLS PIPELINE II=1
            data_out << packet_in;
            data_in >> packet_in;
        }
    }
    data_out << packet_in;
}