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b0607ab3ca
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v1.0.0-rc.34
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2025-04-14 11:52:06 +02:00 |
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a30707964d
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v.1.0.0-rc.32
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2025-03-24 12:16:33 +01:00 |
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ddf4c75645
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v1.0.0-rc.31
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2025-03-02 13:15:28 +01:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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40c1e3d49f
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version 1.0.0-rc.20
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2024-10-21 13:30:56 +02:00 |
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3be959f272
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version 1.0.0-rc.14
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2024-10-07 11:56:40 +02:00 |
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e812918e2e
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version 1.0.0-rc.13
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2024-10-05 13:14:49 +02:00 |
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6b5fddf2b7
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Version 1.0.0-rc.12
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2024-07-06 09:34:44 +02:00 |
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c6d2b5eedf
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File writer and spot finding improvements
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2024-04-08 11:18:50 +02:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
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2023-10-27 15:42:24 +02:00 |
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