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b0607ab3ca
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v1.0.0-rc.34
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2025-04-14 11:52:06 +02:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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40c1e3d49f
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version 1.0.0-rc.20
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2024-10-21 13:30:56 +02:00 |
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59aacf516d
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Updates March 2023
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2024-03-14 20:26:03 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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2268486824
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HLS: Added frame_summation core
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2023-10-26 22:31:09 +02:00 |
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19644a1f5f
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FPGA: Trigger synthesis
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2023-10-21 16:12:51 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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0f7c14c267
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FPGA: integration calculates sum^2
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2023-09-25 22:23:06 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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3f3ce6f354
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FPGA: fix integration bug
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2023-09-22 20:32:12 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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