139 lines
5.4 KiB
C++
139 lines
5.4 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "hls_jfjoch.h"
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void integration(STREAM_768 &data_in,
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STREAM_768 &data_out,
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hls::stream<ap_axiu<64,1,1,1>> &result_out,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion,
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ap_uint<256> *d_hbm_p0,
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ap_uint<256> *d_hbm_p1,
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ap_uint<256> *d_hbm_p2,
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ap_uint<256> *d_hbm_p3,
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volatile ap_uint<1> &idle,
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ap_uint<32> hbm_size_bytes) {
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=data_out
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#pragma HLS INTERFACE register both axis port=result_out
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#pragma HLS INTERFACE register both axis port=m_axis_completion
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#pragma HLS INTERFACE register both axis port=s_axis_completion
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#pragma HLS INTERFACE register ap_none port=hbm_size_bytes
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#pragma HLS INTERFACE register ap_none port=idle
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#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=16384 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
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#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=16384 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
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#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=16384 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
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#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=16384 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
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idle = 1;
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ap_fixed<50,44, AP_RND_CONV> sum[64][FPGA_INTEGRATION_BIN_COUNT];
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// log2(32768*512*1024/64) = 32 + sign 1 bit
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#pragma HLS BIND_STORAGE variable=sum type=ram_t2p impl=bram
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#pragma HLS ARRAY_PARTITION variable=sum type=complete dim=1
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ap_uint<18> count[64][FPGA_INTEGRATION_BIN_COUNT]; // log2(16*512*1024/64) = 17
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#pragma HLS BIND_STORAGE variable=count type=ram_t2p impl=bram
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#pragma HLS ARRAY_PARTITION variable=count type=complete dim=1
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for (int j = 0; j < FPGA_INTEGRATION_BIN_COUNT; j++) {
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#pragma HLS PIPELINE II=1
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for (int i = 0; i < 64; i++) {
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sum[i][j] = 0;
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count[i][j] = 0;
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}
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}
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ap_int<24> in_val[32];
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ap_uint<16> in_bin[32];
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integration_factor_t in_coeff[32];
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ap_uint<256> bins_0, bins_1, coeff_0, coeff_1;
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packet_768_t packet_in;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet_in;
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ap_wait();
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data_out << packet_in;
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ap_wait();
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idle = 0;
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ap_wait();
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}
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ap_uint<32> offset_hbm_0 = 16 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_1 = 17 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_2 = 18 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_3 = 19 * hbm_size_bytes / 32;
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axis_completion cmpl;
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s_axis_completion >> cmpl;
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while (!cmpl.last) {
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m_axis_completion << cmpl;
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for (int i = 0; i < RAW_MODULE_SIZE / 32 / 2; i++) {
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#pragma HLS PIPELINE II=2
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for (int k = 0; k < 2; k++) {
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data_in >> packet_in;
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data_out << packet_in;
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bins_0 = d_hbm_p0[offset_hbm_0 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k];
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bins_1 = d_hbm_p1[offset_hbm_1 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k];
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coeff_0 = d_hbm_p2[offset_hbm_2 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k];
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coeff_1 = d_hbm_p3[offset_hbm_3 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k];
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unpack_2xhbm_to_32x16bit(bins_0, bins_1, in_bin);
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unpack_2xhbm_to_32x16bit(coeff_0, coeff_1, in_coeff);
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unpack32(packet_in.data, in_val);
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for (int j = 0; j < 32; j++) {
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ap_fixed<32, 16, AP_RND_CONV> tmp = in_val[j] * in_coeff[j];
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if ((in_val[j] != INT24_MAX) && (in_val[j] != INT24_MIN) &&
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(in_bin[j] < FPGA_INTEGRATION_BIN_COUNT)) {
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sum[k * 32 + j][in_bin[j]] += tmp;
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count[k * 32 + j][in_bin[j]] += 1;
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}
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}
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}
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}
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s_axis_completion >> cmpl;
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for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) {
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#pragma HLS PIPELINE II=1
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ap_axiu<64,1,1,1> res;
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ap_fixed<64, 50, AP_RND_CONV> main_sum = 0;
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ap_uint<22> main_count = 0;
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for (int j = 0; j < 64; j++) {
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main_sum += sum[j][i];
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main_count += count[j][i];
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sum[j][i] = 0;
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count[j][i] = 0;
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}
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res.data(31, 0) = main_count;
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float_uint32 conv;
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conv.f = main_sum.to_float();
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res.data(63, 32) = conv.u;
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res.dest = 0;
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res.id = 0;
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res.keep = UINT8_MAX;
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res.strb = UINT8_MAX;
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res.user = 0;
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res.last = ((i == FPGA_INTEGRATION_BIN_COUNT - 1) ? 1 : 0);
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result_out << res;
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}
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}
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m_axis_completion << cmpl;
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result_out << ap_axiu<64,1,1,1>{.user = 1};
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data_in >> packet_in;
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data_out << packet_in;
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idle = 1;
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}
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