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61f4adf743
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Merge branch 'main' into 'fpga_hbm_cache'
# Conflicts:
# etc/broker.json
# python/jfjoch_pb2.py
# receiver/FPGAAcquisitionDevice.cpp
# receiver/FPGAAcquisitionDevice.h
# receiver/jfjoch_action_test.cpp
# tests/FPGAIntegrationTest.cpp
# tests/JFJochReceiverIntegrationTest.cpp
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2023-10-22 13:55:41 +00:00 |
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c1469d1e46
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JFJochReceiver: Skip frames if acquisition finished and frames stopped earlier on the first acquisition device
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2023-10-22 14:36:53 +02:00 |
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bc43921004
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JFJochReceiver: Remove local conversion (not useful -> simplify)
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2023-10-22 13:45:47 +02:00 |
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fe5b955289
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GPUImageAnalysis: Spot finder again produces 1-bit result (similar to FPGA) reduced on CPU + mask is not applied on GPU
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2023-10-22 13:42:09 +02:00 |
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566ff52bfc
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JFJochReceiver: Single preview, that can be switched to present all or indexed only results
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2023-10-22 12:41:59 +02:00 |
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ee363a8356
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JFJochReceiver: Given firmware now masks uncollected parts of the image, receiver will accept partial modules (but not for pedestal!)
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2023-10-21 23:01:17 +02:00 |
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624c928c84
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JFJochReceiver: ADU histogram saved on per module basis at the end of the measurement (but not on per image basis)
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2023-10-21 22:31:43 +02:00 |
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99741ae5c5
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ADU histogram: Save
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2023-10-21 19:51:25 +02:00 |
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53f4f4acf9
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RadialIntegration: Calculate only on FPGA
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2023-10-21 19:15:42 +02:00 |
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dd4988486c
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RadialIntegrationMapping: No mask
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2023-10-21 17:20:12 +02:00 |
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b4ab3087f1
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RadialIntegrationProfile: Extra routines to handle GPU/CPU/FPGA workflows in more versatile way
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2023-10-21 17:14:17 +02:00 |
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c86bc4591c
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AcquisitionDevice: Remove automatic setup of radial integration
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2023-10-21 16:08:49 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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0b5bbec1fc
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AcquisitionDevice: Setup rad. int. mapping automatically
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2023-10-20 18:00:29 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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ad78fb0149
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FPGA: Fixes and simplifications to spot_finder core + SNR threshold test
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2023-10-20 12:23:50 +02:00 |
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45de356c16
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FPGA: Minor changes
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2023-10-19 22:43:35 +02:00 |
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aa1ff0436b
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FPGA: Add SNR threshold to spot finder
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2023-10-19 22:29:38 +02:00 |
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6691b01265
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PCIe driver: accept spot finding parameters
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2023-10-18 21:23:41 +02:00 |
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a56a54c72d
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AcquisitionDevice: GetDeviceOutput to get the whole package
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2023-10-18 19:42:57 +02:00 |
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736a181e5e
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HLS: Spot finder outputs parameters + statistics
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2023-10-18 15:19:01 +02:00 |
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6565619035
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parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS)
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2023-10-18 12:10:00 +02:00 |
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05338887a7
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FPGA: Spot finder accepts 16-bit number for strong pixel threshold
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2023-10-16 22:07:41 +02:00 |
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faca7a3f15
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PCIe driver: Clean-up + add intermediate library between driver and AcquisitionDevice
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2023-10-16 19:54:13 +02:00 |
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c5ca10792e
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FPGA: Clean-up of spot_finder core + update README.MD
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2023-10-16 15:13:47 +02:00 |
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7889f1666a
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FPGA: Spot finder 2nd version improved
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2023-10-04 12:12:43 +02:00 |
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c6afbebd13
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FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result)
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2023-10-02 22:34:49 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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8831ad380f
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FPGA: Fix bug in adu_histo + add test + add access from AcquisitionDevice
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2023-09-29 18:34:29 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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5bb92aed61
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FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer
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2023-09-29 14:44:08 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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0f7c14c267
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FPGA: integration calculates sum^2
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2023-09-25 22:23:06 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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4028a59c4a
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PCIe driver: add option to read/write register
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2023-09-24 22:58:16 +02:00 |
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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f4f4b50be7
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FPGA: frame_generator has 8 module specific frames
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2023-09-24 15:43:04 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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5cf0d30603
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AcquisitionDevice: Enable access to integration results
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2023-09-22 20:32:13 +02:00 |
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f06e92fd1b
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FPGA: load_calibration allows to upload integration map
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2023-09-22 18:28:35 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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ffa3a2cdac
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FPGAAcquisitionDevice: Put warning for wrong data collection ID
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2023-09-20 16:52:59 +02:00 |
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8c1bc9d89d
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FPGA: Remove non-blocking mode
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2023-09-20 16:41:14 +02:00 |
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88e837a33a
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FPGAAcquisitionDevice: Remove non-blocking mode
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2023-09-20 16:29:50 +02:00 |
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ac2181e276
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FPGAAcquisitionDevice: Remove non-blocking mode
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2023-09-20 16:26:53 +02:00 |
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784b1f41ed
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jfjoch_receiver: Allow to set NUMA policy
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2023-09-20 14:28:24 +02:00 |
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494ccba73d
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JFJochReceiver: Handle better error in binding to NUMA policy
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2023-09-20 14:24:31 +02:00 |
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62bb0c9e98
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FPGAAcquisitionDevice: Monitor frame generator FIFO
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2023-09-19 19:46:00 +02:00 |
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