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Code Issues Pull Requests Actions Packages Projects Releases 42 Wiki Activity
372 Commits 48 Branches 127 Tags
ae7ccfdcecb41e00278118003eac23f705fa5a4b
Commit Graph

11 Commits

Author SHA1 Message Date
Filip Leonarski
48861aafcb FPGAAcquisitionDevice: Report HBM size 2023-09-10 16:38:25 +02:00
Filip Leonarski
175aefc4b8 FPGA: Save to HBM uses only 2 channels 2023-09-10 09:54:32 +02:00
Filip Leonarski
929f6c6544 FPGA: Handle HBM offsets internally in Jungfraujoch logic 2023-09-09 20:50:41 +02:00
Filip Leonarski
aca1bbda0e HLSSimulatedDevice: moving towards continuous HBM representation 2023-09-09 13:10:06 +02:00
Filip Leonarski
6251c58f32 FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer 2023-09-08 19:08:37 +02:00
Filip Leonarski
c2eaee6d8a FPGA: Save to HBM operates in parallel to host writer 2023-09-08 13:07:49 +02:00
Filip Leonarski
38df621cf6 FPGA: Add save to HBM (work in progress) 2023-09-07 22:15:20 +02:00
Filip Leonarski
347bfd3f2c HLSSimulateDevice: Remove reference to UltraRAM 2023-09-07 21:39:14 +02:00
Filip Leonarski
3aeb3e09ee FPGA: Do not load internal packet generator frame via DMA 2023-09-06 11:57:16 +02:00
Filip Leonarski
caf950f99f FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR 2023-09-06 08:19:03 +02:00
Filip Leonarski
a12fc941d5 JFJochReceiver: Remove host subdirectory 2023-06-07 21:28:22 +02:00
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