|
|
aca1bbda0e
|
HLSSimulatedDevice: moving towards continuous HBM representation
|
2023-09-09 13:10:06 +02:00 |
|
|
|
6251c58f32
|
FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
|
2023-09-08 19:08:37 +02:00 |
|
|
|
c2eaee6d8a
|
FPGA: Save to HBM operates in parallel to host writer
|
2023-09-08 13:07:49 +02:00 |
|
|
|
38df621cf6
|
FPGA: Add save to HBM (work in progress)
|
2023-09-07 22:15:20 +02:00 |
|
|
|
347bfd3f2c
|
HLSSimulateDevice: Remove reference to UltraRAM
|
2023-09-07 21:39:14 +02:00 |
|
|
|
3aeb3e09ee
|
FPGA: Do not load internal packet generator frame via DMA
|
2023-09-06 11:57:16 +02:00 |
|
|
|
caf950f99f
|
FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
|
2023-09-06 08:19:03 +02:00 |
|
|
|
a12fc941d5
|
JFJochReceiver: Remove host subdirectory
|
2023-06-07 21:28:22 +02:00 |
|
