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Code Issues Pull Requests Actions Packages Projects Releases 38 Wiki Activity
700 Commits 45 Branches 123 Tags
99f33eaf532fcc0b97e1c2dcbdcee336f8dcdde6
Commit Graph

6 Commits

Author SHA1 Message Date
leonarski_f
1798de247b Extend FPGA functionality 2023-12-09 12:08:39 +01:00
Filip Leonarski
961c17c4d0 FPGA: data analysis is done based on 24-bit numbers - allowing frame summation 2023-10-28 16:35:33 +02:00
Filip Leonarski
4fbd747341 FPGA: Remove multipixel from the pipeline 2023-10-27 20:47:44 +02:00
Filip Leonarski
4978149fdd FPGA: Add register slice in the data pipeline 2023-10-27 19:43:40 +02:00
Filip Leonarski
c896ec5659 FPGA: Remove bitshuffle from the pipeline 2023-10-27 19:41:02 +02:00
Filip Leonarski
08c2427fc7 FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign 2023-10-27 15:42:24 +02:00
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