3 Commits

Include renames

Author	SHA1	Message	Date
leonarski_f	1333ce9b29	FPGA: trigger synthesis	2023-09-06 12:36:14 +02:00
leonarski_f	3aeb3e09ee	FPGA: Do not load internal packet generator frame via DMA	2023-09-06 11:57:16 +02:00
leonarski_f	7a98766304	FPGA: Split receiver and FPGA design directories	2023-06-07 21:21:22 +02:00