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mx/Jungfraujoch
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Code Issues Pull Requests 1 Actions Packages Projects Releases 54 Wiki Activity
202 Commits 72 Branches 139 Tags
0994e142b3eeec92c9e62e884d7f00a4729b00a7
Commit Graph

12 Commits

Author SHA1 Message Date
leonarski_f a3996a81e3 FPGA: Remove data collection counter 2023-05-30 20:13:54 +02:00
leonarski_f 72cdb88c0c FPGA: Add host_writer idle marker 2023-05-27 21:45:21 +02:00
leonarski_f 7c9a5238e2 FPGA: Minor improvements to data_collection_fsm 2023-05-27 18:39:35 +02:00
leonarski_f c1212a14d9 FPGA: work requests are consumed while host_writer not working 2023-05-26 22:12:34 +02:00
leonarski_f b926e69885 FPGA: data_collection_fsm counter 2023-05-26 20:39:12 +02:00
leonarski_f 021e652dc6 FPGA: non-blocking mode (to be tested) 2023-05-26 18:46:26 +02:00
leonarski_f c2b42916c2 FPGA: host_writer allows to skip frames, if no available location in host memory 2023-05-24 11:54:51 +02:00
leonarski_f 7d5694139f FPGA: Save full JF timestamp and exptime 2023-05-17 21:30:42 +02:00
leonarski_f 001a7d86fc FPGA: For totally unknown reason making UDP metadata stream narrower results in timing not met 2023-04-17 08:02:24 +02:00
leonarski_f c792367496 FPGA: Minor clean-up of UDP processing 2023-04-15 19:33:34 +02:00
leonarski_f 653b82d6c3 FPGA + receiver + detector: Use column ID to decode detector half-module number 2023-04-15 11:08:32 +02:00
leonarski_f 1757d42182 Initial commit
Signed-off-by: Filip Leonarski <filip.leonarski@psi.ch>
2023-04-06 11:17:59 +02:00
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