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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
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2023-10-27 15:42:24 +02:00 |
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