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e0b8fb3609
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updated manuals, jungfrau server (reqd firmware vversion)
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2018-08-23 15:52:12 +02:00 |
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24db58e615
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jungfrau server required firmware version on server changed from 0x2018 to 0x18
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2018-06-06 10:23:06 +02:00 |
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cf8b0de433
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slsReceiver, slsDetector, eiger and jungfrau server: client checks firmware and software an dreceiver compatibility for each time shared memory is cleaned up
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2018-05-28 19:11:34 +02:00 |
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68e9648854
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created programming mode, where only programming is allowed, one has to restart servers afterwards
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2018-05-09 11:20:54 +02:00 |
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d096a5efeb
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jungfrau server: default storage cell start is 0xf
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2018-04-26 16:30:27 +02:00 |
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bc70cc3a26
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jungfrau server: added storage start, connected auto_comp_disable, changed adcphase, added ADC_PORT_INVERT_VAL, ADC_OFST_HALF_SPEED_VAL, minimum exposure time
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2018-04-13 17:33:46 +02:00 |
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e024774323
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added storage cells
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2018-04-13 15:05:43 +02:00 |
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bdcccb7732
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jungfrau server, changed api, fixed regdefs
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2018-04-13 11:43:30 +02:00 |
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5ff2e86060
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jungfrau server configuring ASIC timer at server startup
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2018-04-13 11:07:22 +02:00 |
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a36b715eab
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resolved conflicts from merging 3.1.1 in here
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2018-03-21 09:03:31 +01:00 |
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688dd15fe9
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Jungfrau bug fix: cannot give same adcphase value to pll, updated recommended default of adcphase for half speed and quarter speed, updated client manuals for both adcphase and clkdivider
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2018-03-20 12:12:38 +01:00 |
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7364f674ed
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[JUNGFRAU] - Modified memory map address shift for the interface between FPGA and Blackfin SOM. Shift has to be set to 1 since the basic AMC data transfers is 8-bit and not 16-bit.
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2018-02-22 11:15:24 +01:00 |
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1872deb1dd
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fix for temperature workaround for fpga
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2018-02-02 15:17:40 +01:00 |
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e6f475d7c4
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jungfrau server changes in temperature control for fpga bug: default temp threshold and temp event cleared at start and power reg only reads enable and not status
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2018-02-02 12:37:52 +01:00 |
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Dhanya Maliakal
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2d6e4c95a2
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temp_threshold, temp_control, temp_event done
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2018-01-11 15:37:24 +01:00 |
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Dhanya Maliakal
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d879379aa4
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jungfrau server: incorporated transmission delay
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2018-01-11 11:33:26 +01:00 |
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Dhanya Maliakal
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348a426242
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updating to have developer's debug mode, resetfpga, programfpga and added api versioning, changed software date to only have date
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2018-01-11 09:14:45 +01:00 |
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Dhanya Maliakal
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00e742e0e0
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took out also the ADC and serialspi
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2017-06-14 11:28:16 +02:00 |
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Dhanya Maliakal
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a95dbd2215
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made some functions common
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2017-06-14 10:43:15 +02:00 |
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Dhanya Maliakal
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d41abc2b1c
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added new jungfraustructure, wiht common detector tcp interface
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2017-06-12 18:50:18 +02:00 |
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