mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-28 01:00:02 +02:00
[JUNGFRAU] - Modified memory map address shift for the interface between FPGA and Blackfin SOM. Shift has to be set to 1 since the basic AMC data transfers is 8-bit and not 16-bit.
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@ -4,7 +4,7 @@
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/* Definitions for FPGA*/
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x00 << 11)
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#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
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#define BOARD_REVISION_OFST (0)
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#define BOARD_REVISION_MSK (0x00FFFFFF << BOARD_REVISION_OFST)
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@ -14,10 +14,10 @@
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/* Fix pattern register */
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#define FIX_PATT_REG (0x01 << 11)
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#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
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/* Status register */
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#define STATUS_REG (0x02 << 11)
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#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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@ -34,10 +34,10 @@
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/* Look at me register */
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#define LOOK_AT_ME_REG (0x03 << 11) //Not used in firmware or software
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#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) //Not used in firmware or software
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/* System Status register */
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#define SYSTEM_STATUS_REG (0x04 << 11) //Not used in software
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#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) //Not used in software
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#define DDR3_CAL_DONE_OFST (0) //Not used in software
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#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
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@ -54,7 +54,7 @@
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/* Module Control Board Serial Number Register */
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#define MOD_SERIAL_NUM_REG (0x0A << 11) //Not used in software
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#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT) //Not used in software
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#define HARDWARE_SERIAL_NUM_OFST (0) //Not used in software
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#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST) //Not used in software
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@ -63,7 +63,7 @@
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/* API Version Register */
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#define API_VERSION_REG (0x0F << 11)
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#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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@ -71,27 +71,27 @@
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Time from Start 64 bit register */
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#define TIME_FROM_START_LSB_REG (0x10 << 11)
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#define TIME_FROM_START_MSB_REG (0x11 << 11)
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#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
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/* Get Delay 64 bit register */
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#define GET_DELAY_LSB_REG (0x12 << 11)
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#define GET_DELAY_MSB_REG (0x13 << 11)
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#define GET_DELAY_LSB_REG (0x12 << MEM_MAP_SHIFT)
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#define GET_DELAY_MSB_REG (0x13 << MEM_MAP_SHIFT)
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/* Get Cycles 64 bit register */
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#define GET_CYCLES_LSB_REG (0x14 << 11)
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#define GET_CYCLES_MSB_REG (0x15 << 11)
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#define GET_CYCLES_LSB_REG (0x14 << MEM_MAP_SHIFT)
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#define GET_CYCLES_MSB_REG (0x15 << MEM_MAP_SHIFT)
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/* Get Frames 64 bit register */
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#define GET_FRAMES_LSB_REG (0x16 << 11)
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#define GET_FRAMES_MSB_REG (0x17 << 11)
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#define GET_FRAMES_LSB_REG (0x16 << MEM_MAP_SHIFT)
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#define GET_FRAMES_MSB_REG (0x17 << MEM_MAP_SHIFT)
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/* Get Period 64 bit register */
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#define GET_PERIOD_LSB_REG (0x18 << 11)
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#define GET_PERIOD_MSB_REG (0x19 << 11)
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#define GET_PERIOD_LSB_REG (0x18 << MEM_MAP_SHIFT)
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#define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
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/** Get Temperature Carlos, incorrectl as get gates */
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#define GET_TEMPERATURE_TMP112_REG (0x1c << 11) // (after multiplying by 625) in 10ths of millidegrees of TMP112
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#define GET_TEMPERATURE_TMP112_REG (0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of millidegrees of TMP112
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#define TEMPERATURE_POLARITY_BIT (15)
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#define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
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@ -100,15 +100,15 @@
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/* Get Frames from Start 64 bit register (frames from start Run Control) */
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
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/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
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#define START_FRAME_TIME_LSB_REG (0x26 << 11)
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#define START_FRAME_TIME_MSB_REG (0x27 << 11)
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#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
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#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
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/* SPI (Serial Peripheral Interface) Register */
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#define SPI_REG (0x40 << 11)
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#define SPI_REG (0x40 << MEM_MAP_SHIFT)
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#define DAC_SERIAL_DIGITAL_OUT_OFST (0)
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#define DAC_SERIAL_DIGITAL_OUT_MSK (0x00000001 << DAC_SERIAL_DIGITAL_OUT_OFST)
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@ -125,7 +125,7 @@
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/* ADC SPI (Serial Peripheral Interface) Register */
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#define ADC_SPI_REG (0x41 << 11)
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#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
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#define ADC_SERIAL_CLK_OUT_OFST (0)
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#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
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@ -135,16 +135,16 @@
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#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
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/* ADC offset Register */
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#define ADC_OFST_REG (0x42 << 11)
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#define ADC_OFST_REG (0x42 << MEM_MAP_SHIFT)
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/* ADC Port Invert Register */
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#define ADC_PORT_INVERT_REG (0x43 << 11)
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#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
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/* Receiver IP Address Register */
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#define RX_IP_REG (0x45 << 11)
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#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
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/* UDP Port */
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#define UDP_PORT_REG (0x46 << 11)
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#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
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#define UDP_PORT_RX_OFST (0)
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#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
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@ -152,8 +152,8 @@
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#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
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/* Receiver Mac Address 64 bit Register */
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#define RX_MAC_LSB_REG (0x47 << 11)
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#define RX_MAC_MSB_REG (0x48 << 11)
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#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
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#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
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#define RX_MAC_LSB_OFST (0)
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#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
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@ -161,8 +161,8 @@
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#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
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/* Detector/ Transmitter Mac Address 64 bit Register */
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#define TX_MAC_LSB_REG (0x49 << 11)
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#define TX_MAC_MSB_REG (0x4A << 11)
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#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
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#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
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#define TX_MAC_LSB_OFST (0)
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#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
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@ -170,16 +170,16 @@
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#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
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/* Detector/ Transmitter IP Address Register */
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#define TX_IP_REG (0x4B << 11)
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#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
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/* Detector/ Transmitter IP Checksum Register */
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#define TX_IP_CHECKSUM_REG (0x4C << 11)
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#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
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#define TX_IP_CHECKSUM_OFST (0)
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#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
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/* Configuration Register */
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#define CONFIG_REG (0x4D << 11)
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#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
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#define CONFIG_OPERATION_MODE_OFST (16)
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#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
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@ -199,13 +199,13 @@
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/* External Signal Register */
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#define EXT_SIGNAL_REG (0x4E << 11)
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#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
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#define EXT_SIGNAL_OFST (0)
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#define EXT_SIGNAL_MSK (0x00000003 << EXT_SIGNAL_OFST) //enabled when both bits high
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/* Control Register */
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#define CONTROL_REG (0x4F << 11)
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#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
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#define CONTROL_START_ACQ_OFST (0)
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#define CONTROL_START_ACQ_MSK (0x00000001 << CONTROL_START_ACQ_OFST)
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@ -223,10 +223,10 @@
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#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
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/* Reconfiguratble PLL Paramater Register */
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#define PLL_PARAM_REG (0x50 << 11)
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#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
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/* Reconfiguratble PLL Control Regiser */
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#define PLL_CONTROL_REG (0x51 << 11)
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#define PLL_CONTROL_REG (0x51 << MEM_MAP_SHIFT)
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#define PLL_CTRL_RECONFIG_RST_OFST (0) //parameter reset
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#define PLL_CTRL_RECONFIG_RST_MSK (0x00000001 << PLL_CTRL_RECONFIG_RST_OFST) //parameter reset
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@ -238,7 +238,7 @@
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#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
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/* Sample Register (Obsolete) */
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#define SAMPLE_REG (0x59 << 11)
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#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)
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#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
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#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
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@ -288,7 +288,7 @@
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#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
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/** Vref Comp Mod Register */
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#define VREF_COMP_MOD_REG (0x5C << 11)
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#define VREF_COMP_MOD_REG (0x5C << MEM_MAP_SHIFT)
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#define VREF_COMP_MOD_OFST (0)
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#define VREF_COMP_MOD_MSK (0x00000FFF << VREF_COMP_MOD_OFST)
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@ -297,10 +297,10 @@
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/** DAQ Register */
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#define DAQ_REG (0x5D << 11) //TBD in firmware
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#define DAQ_REG (0x5D << MEM_MAP_SHIFT) //TBD in firmware
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/** Chip Power Register */
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#define CHIP_POWER_REG (0x5E << 11)
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#define CHIP_POWER_REG (0x5E << MEM_MAP_SHIFT)
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#define CHIP_POWER_ENABLE_OFST (0)
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#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
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@ -309,7 +309,7 @@
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/** Temperature Control Register */
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#define TEMP_CTRL_REG (0x5F << 11)
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#define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
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#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
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#define TEMP_CTRL_PROTCT_THRSHLD_MSK (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
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@ -321,31 +321,31 @@
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/* Set Delay 64 bit register */
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#define SET_DELAY_LSB_REG (0x60 << 11)
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#define SET_DELAY_MSB_REG (0x61 << 11)
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#define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
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#define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
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/* Set Cycles 64 bit register */
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#define SET_CYCLES_LSB_REG (0x62 << 11)
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#define SET_CYCLES_MSB_REG (0x63 << 11)
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#define SET_CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
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#define SET_CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
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/* Set Frames 64 bit register */
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#define SET_FRAMES_LSB_REG (0x64 << 11)
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#define SET_FRAMES_MSB_REG (0x65 << 11)
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#define SET_FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
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#define SET_FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
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/* Set Period 64 bit register */
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#define SET_PERIOD_LSB_REG (0x66 << 11)
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#define SET_PERIOD_MSB_REG (0x67 << 11)
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#define SET_PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
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#define SET_PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
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/* Set Period 64 bit register */
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#define SET_EXPTIME_LSB_REG (0x68 << 11)
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#define SET_EXPTIME_MSB_REG (0x69 << 11)
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#define SET_EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT)
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#define SET_EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT)
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/* Trigger Delay 32 bit register */
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#define SET_TRIGGER_DELAY_LSB_REG (0x70 << 11)
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#define SET_TRIGGER_DELAY_MSB_REG (0x71 << 11)
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#define SET_TRIGGER_DELAY_LSB_REG (0x70 << MEM_MAP_SHIFT)
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#define SET_TRIGGER_DELAY_MSB_REG (0x71 << MEM_MAP_SHIFT)
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/* Module Coordinates Register 0 */
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#define COORD_0 (0x7C << 11)
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#define COORD_0 (0x7C << MEM_MAP_SHIFT)
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#define COORD_0_Y_OFST (0)
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#define COORD_0_Y_MSK (0x0000FFFF << COORD_0_Y_OFST)
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@ -353,7 +353,7 @@
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#define COORD_0_X_MSK (0x0000FFFF << COORD_0_X_OFST)
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/* Module Coordinates Register 1 */
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#define COORD_1 (0x7D << 11)
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#define COORD_1 (0x7D << MEM_MAP_SHIFT)
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#define COORD_0_Z_OFST (0)
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#define COORD_0_Z_MSK (0x0000FFFF << COORD_0_Z_OFST)
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Binary file not shown.
@ -1,9 +1,9 @@
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Path: slsDetectorsPackage/slsDetectorSoftware/jungfrauDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 3da6a6df6556312f7467407a8b5691bdc478424e
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Revision: 119
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Repsitory UUID: a536f8ac9be2f064974da454273bfa828edb5bb1
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Revision: 121
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Branch: developer
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Last Changed Author: Dhanya_Thattil
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Last Changed Rev: 3597
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Last Changed Date: 2018-02-07 10:44:06.000000002 +0100 ./RegisterDefs.h
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Last Changed Author: Erik_Frojdh
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Last Changed Rev: 3669
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Last Changed Date: 2018-02-22 10:31:42.834118468 +0100 ./blackfin.h~
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "3da6a6df6556312f7467407a8b5691bdc478424e"
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#define GITAUTH "Dhanya_Thattil"
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#define GITREV 0x3597
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#define GITDATE 0x20180207
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#define GITREPUUID "a536f8ac9be2f064974da454273bfa828edb5bb1"
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#define GITAUTH "Erik_Frojdh"
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#define GITREV 0x3669
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#define GITDATE 0x20180222
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#define GITBRANCH "developer"
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@ -8,8 +8,8 @@
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#define GOODBYE (-200)
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#define MIN_REQRD_VRSN_T_RD_API 0x171113
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#define REQRD_FRMWR_VRSN 0x171113
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define REQRD_FRMWR_VRSN 0x171220
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/* Struct Definitions */
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@ -12,6 +12,7 @@
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u_int32_t CSP0BASE = 0;
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#define CSP0 0x20200000
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#define MEM_SIZE 0x100000
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#define MEM_MAP_SHIFT 1
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@ -103,7 +104,7 @@ int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
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* @retuns 32 bit data read
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*/
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u_int32_t readRegister(u_int32_t offset) {
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return bus_r(offset << 11);
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return bus_r(offset << MEM_MAP_SHIFT);
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}
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/**
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@ -112,7 +113,7 @@ u_int32_t readRegister(u_int32_t offset) {
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* @param data 32 bit data
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*/
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u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
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bus_w(offset << 11, data);
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bus_w(offset << MEM_MAP_SHIFT, data);
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return readRegister(offset);
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}
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