From 7364f674eddf0751a3ab3696579bf7453cf55fe7 Mon Sep 17 00:00:00 2001
From: lopez_c <carlos.lopez-cuenca@psi.ch>
Date: Thu, 22 Feb 2018 11:15:24 +0100
Subject: [PATCH] [JUNGFRAU] - Modified memory map address shift for the
 interface between FPGA and Blackfin SOM. Shift has to be set to 1 since the
 basic AMC data transfers is 8-bit and not 16-bit.

---
 .../jungfrauDetectorServer/RegisterDefs.h     | 116 +++++++++---------
 .../bin/jungfrauDetectorServer_developer      | Bin 110872 -> 110680 bytes
 .../jungfrauDetectorServer/gitInfo.txt        |  10 +-
 .../jungfrauDetectorServer/gitInfoJungfrau.h  |   8 +-
 .../slsDetectorServer_defs.h                  |   4 +-
 .../slsDetectorServer/blackfin.h              |   5 +-
 6 files changed, 72 insertions(+), 71 deletions(-)

diff --git a/slsDetectorSoftware/jungfrauDetectorServer/RegisterDefs.h b/slsDetectorSoftware/jungfrauDetectorServer/RegisterDefs.h
index ebd2d94b5..697f0eaf5 100644
--- a/slsDetectorSoftware/jungfrauDetectorServer/RegisterDefs.h
+++ b/slsDetectorSoftware/jungfrauDetectorServer/RegisterDefs.h
@@ -4,7 +4,7 @@
 /* Definitions for FPGA*/
 
 /* FPGA Version register */
-#define FPGA_VERSION_REG      			(0x00 << 11)
+#define FPGA_VERSION_REG      			(0x00 << MEM_MAP_SHIFT)
 
 #define BOARD_REVISION_OFST				(0)
 #define BOARD_REVISION_MSK				(0x00FFFFFF << BOARD_REVISION_OFST)
@@ -14,10 +14,10 @@
 
 
 /* Fix pattern register */
-#define FIX_PATT_REG          			(0x01 << 11)
+#define FIX_PATT_REG          			(0x01 << MEM_MAP_SHIFT)
 
 /* Status register */
-#define STATUS_REG            			(0x02 << 11)
+#define STATUS_REG            			(0x02 << MEM_MAP_SHIFT)
 
 #define RUN_BUSY_OFST					(0)
 #define RUN_BUSY_MSK      				(0x00000001 << RUN_BUSY_OFST)
@@ -34,10 +34,10 @@
 
 
 /* Look at me register */
-#define LOOK_AT_ME_REG          		(0x03 << 11)								//Not used in firmware or software
+#define LOOK_AT_ME_REG          		(0x03 << MEM_MAP_SHIFT)								//Not used in firmware or software
 
 /* System Status register */
-#define SYSTEM_STATUS_REG       		(0x04 << 11)								//Not used in software
+#define SYSTEM_STATUS_REG       		(0x04 << MEM_MAP_SHIFT)								//Not used in software
 
 #define DDR3_CAL_DONE_OFST				(0)											//Not used in software
 #define DDR3_CAL_DONE_MSK 				(0x00000001 << DDR3_CAL_DONE_OFST)			//Not used in software
@@ -54,7 +54,7 @@
 
 
 /* Module Control Board Serial Number Register */
-#define MOD_SERIAL_NUM_REG				(0x0A << 11)								//Not used in software
+#define MOD_SERIAL_NUM_REG				(0x0A << MEM_MAP_SHIFT)								//Not used in software
 
 #define HARDWARE_SERIAL_NUM_OFST		(0)											//Not used in software
 #define HARDWARE_SERIAL_NUM_MSK			(0x000000FF << HARDWARE_SERIAL_NUM_OFST)	//Not used in software
@@ -63,7 +63,7 @@
 
 
 /* API Version Register */
-#define API_VERSION_REG                 (0x0F << 11)
+#define API_VERSION_REG                 (0x0F << MEM_MAP_SHIFT)
 
 #define API_VERSION_OFST                (0)
 #define API_VERSION_MSK                 (0x00FFFFFF << API_VERSION_OFST)
@@ -71,27 +71,27 @@
 #define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
 
 /* Time from Start 64 bit register */
-#define TIME_FROM_START_LSB_REG   		(0x10 << 11)
-#define TIME_FROM_START_MSB_REG   		(0x11 << 11)
+#define TIME_FROM_START_LSB_REG   		(0x10 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_MSB_REG   		(0x11 << MEM_MAP_SHIFT)
 
 /* Get Delay 64 bit register */
-#define GET_DELAY_LSB_REG     			(0x12 << 11)
-#define GET_DELAY_MSB_REG     			(0x13 << 11)
+#define GET_DELAY_LSB_REG     			(0x12 << MEM_MAP_SHIFT)
+#define GET_DELAY_MSB_REG     			(0x13 << MEM_MAP_SHIFT)
 
 /* Get Cycles 64 bit register */
-#define GET_CYCLES_LSB_REG    			(0x14 << 11)
-#define GET_CYCLES_MSB_REG    			(0x15 << 11)
+#define GET_CYCLES_LSB_REG    			(0x14 << MEM_MAP_SHIFT)
+#define GET_CYCLES_MSB_REG    			(0x15 << MEM_MAP_SHIFT)
 
 /* Get Frames 64 bit register */
-#define GET_FRAMES_LSB_REG   			(0x16 << 11)
-#define GET_FRAMES_MSB_REG    			(0x17 << 11)
+#define GET_FRAMES_LSB_REG   			(0x16 << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG    			(0x17 << MEM_MAP_SHIFT)
 
 /* Get Period 64 bit register */
-#define GET_PERIOD_LSB_REG    			(0x18 << 11)
-#define GET_PERIOD_MSB_REG    			(0x19 << 11)
+#define GET_PERIOD_LSB_REG    			(0x18 << MEM_MAP_SHIFT)
+#define GET_PERIOD_MSB_REG    			(0x19 << MEM_MAP_SHIFT)
 
 /** Get Temperature Carlos, incorrectl as get gates */
-#define GET_TEMPERATURE_TMP112_REG		(0x1c << 11)							// (after multiplying by 625) in 10ths of millidegrees of TMP112
+#define GET_TEMPERATURE_TMP112_REG		(0x1c << MEM_MAP_SHIFT)							// (after multiplying by 625) in 10ths of millidegrees of TMP112
 
 #define TEMPERATURE_POLARITY_BIT		(15)
 #define TEMPERATURE_POLARITY_MSK		(0x00000001 << TEMPERATURE_POLARITY_BIT)
@@ -100,15 +100,15 @@
 
 
 /* Get Frames from Start 64 bit register (frames from start Run Control) */
-#define FRAMES_FROM_START_PG_LSB_REG	(0x24 << 11)
-#define FRAMES_FROM_START_PG_MSB_REG 	(0x25 << 11)
+#define FRAMES_FROM_START_PG_LSB_REG	(0x24 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_MSB_REG 	(0x25 << MEM_MAP_SHIFT)
 
 /* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
-#define START_FRAME_TIME_LSB_REG		(0x26 << 11)
-#define START_FRAME_TIME_MSB_REG 		(0x27 << 11)
+#define START_FRAME_TIME_LSB_REG		(0x26 << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_MSB_REG 		(0x27 << MEM_MAP_SHIFT)
 
 /* SPI (Serial Peripheral Interface) Register */
-#define SPI_REG							(0x40 << 11)
+#define SPI_REG							(0x40 << MEM_MAP_SHIFT)
 
 #define DAC_SERIAL_DIGITAL_OUT_OFST		(0)
 #define DAC_SERIAL_DIGITAL_OUT_MSK		(0x00000001 << DAC_SERIAL_DIGITAL_OUT_OFST)
@@ -125,7 +125,7 @@
 
 
 /* ADC SPI (Serial Peripheral Interface) Register */
-#define ADC_SPI_REG   					(0x41 << 11)
+#define ADC_SPI_REG   					(0x41 << MEM_MAP_SHIFT)
 
 #define ADC_SERIAL_CLK_OUT_OFST			(0)
 #define ADC_SERIAL_CLK_OUT_MSK			(0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
@@ -135,16 +135,16 @@
 #define ADC_SERIAL_CS_OUT_MSK			(0x0000000F << ADC_SERIAL_CS_OUT_OFST)
 
 /* ADC offset Register */
-#define ADC_OFST_REG 					(0x42 << 11)
+#define ADC_OFST_REG 					(0x42 << MEM_MAP_SHIFT)
 
 /* ADC Port Invert Register */
-#define ADC_PORT_INVERT_REG   			(0x43 << 11)
+#define ADC_PORT_INVERT_REG   			(0x43 << MEM_MAP_SHIFT)
 
 /* Receiver IP Address Register */
-#define RX_IP_REG    					(0x45 << 11)
+#define RX_IP_REG    					(0x45 << MEM_MAP_SHIFT)
 
 /* UDP Port */
-#define UDP_PORT_REG    				(0x46 << 11)
+#define UDP_PORT_REG    				(0x46 << MEM_MAP_SHIFT)
 
 #define UDP_PORT_RX_OFST				(0)
 #define UDP_PORT_RX_MSK					(0x0000FFFF << UDP_PORT_RX_OFST)
@@ -152,8 +152,8 @@
 #define UDP_PORT_TX_MSK					(0x0000FFFF << UDP_PORT_TX_OFST)
 
 /* Receiver Mac Address 64 bit Register */
-#define RX_MAC_LSB_REG					(0x47 << 11)
-#define RX_MAC_MSB_REG					(0x48 << 11)
+#define RX_MAC_LSB_REG					(0x47 << MEM_MAP_SHIFT)
+#define RX_MAC_MSB_REG					(0x48 << MEM_MAP_SHIFT)
 
 #define RX_MAC_LSB_OFST					(0)
 #define RX_MAC_LSB_MSK					(0xFFFFFFFF << RX_MAC_LSB_OFST)
@@ -161,8 +161,8 @@
 #define RX_MAC_MSB_MSK					(0x0000FFFF << RX_MAC_MSB_OFST)
 
 /* Detector/ Transmitter Mac Address 64 bit Register */
-#define TX_MAC_LSB_REG					(0x49 << 11)
-#define TX_MAC_MSB_REG					(0x4A << 11)
+#define TX_MAC_LSB_REG					(0x49 << MEM_MAP_SHIFT)
+#define TX_MAC_MSB_REG					(0x4A << MEM_MAP_SHIFT)
 
 #define TX_MAC_LSB_OFST					(0)
 #define TX_MAC_LSB_MSK					(0xFFFFFFFF << TX_MAC_LSB_OFST)
@@ -170,16 +170,16 @@
 #define TX_MAC_MSB_MSK					(0x0000FFFF << TX_MAC_MSB_OFST)
 
 /* Detector/ Transmitter IP Address Register */
-#define TX_IP_REG						(0x4B << 11)
+#define TX_IP_REG						(0x4B << MEM_MAP_SHIFT)
 
 /* Detector/ Transmitter IP Checksum Register */
-#define TX_IP_CHECKSUM_REG				(0x4C << 11)
+#define TX_IP_CHECKSUM_REG				(0x4C << MEM_MAP_SHIFT)
 
 #define TX_IP_CHECKSUM_OFST				(0)
 #define TX_IP_CHECKSUM_MSK				(0x0000FFFF << TX_IP_CHECKSUM_OFST)
 
 /* Configuration Register */
-#define CONFIG_REG            			(0x4D << 11)
+#define CONFIG_REG            			(0x4D << MEM_MAP_SHIFT)
 
 #define CONFIG_OPERATION_MODE_OFST		(16)
 #define CONFIG_OPERATION_MODE_MSK		(0x00000001 << CONFIG_OPERATION_MODE_OFST)
@@ -199,13 +199,13 @@
 
 
 /* External Signal Register */
-#define EXT_SIGNAL_REG        			(0x4E << 11)
+#define EXT_SIGNAL_REG        			(0x4E << MEM_MAP_SHIFT)
 
 #define EXT_SIGNAL_OFST					(0)
 #define EXT_SIGNAL_MSK					(0x00000003 << EXT_SIGNAL_OFST)				//enabled when both bits high
 
 /* Control Register */
-#define CONTROL_REG           			(0x4F << 11)
+#define CONTROL_REG           			(0x4F << MEM_MAP_SHIFT)
 
 #define CONTROL_START_ACQ_OFST       	(0)
 #define CONTROL_START_ACQ_MSK			(0x00000001 << CONTROL_START_ACQ_OFST)
@@ -223,10 +223,10 @@
 #define CONTROL_STORAGE_CELL_NUM_MSK    (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
 
 /* Reconfiguratble PLL Paramater Register */
-#define PLL_PARAM_REG					(0x50 << 11)
+#define PLL_PARAM_REG					(0x50 << MEM_MAP_SHIFT)
 
 /* Reconfiguratble PLL Control Regiser */
-#define PLL_CONTROL_REG					(0x51 << 11)
+#define PLL_CONTROL_REG					(0x51 << MEM_MAP_SHIFT)
 
 #define PLL_CTRL_RECONFIG_RST_OFST		(0)											//parameter reset
 #define PLL_CTRL_RECONFIG_RST_MSK		(0x00000001 << PLL_CTRL_RECONFIG_RST_OFST)	//parameter reset
@@ -238,7 +238,7 @@
 #define PLL_CTRL_ADDR_MSK				(0x0000003F << PLL_CTRL_ADDR_OFST)
 
 /* Sample Register (Obsolete) */
-#define SAMPLE_REG 						(0x59 << 11)
+#define SAMPLE_REG 						(0x59 << MEM_MAP_SHIFT)
 
 #define SAMPLE_ADC_SAMPLE_SEL_OFST		(0)
 #define SAMPLE_ADC_SAMPLE_SEL_MSK		(0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
@@ -288,7 +288,7 @@
 #define SAMPLE_DECMT_FACTOR_4_VAL		((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
 
 /** Vref Comp Mod Register */
-#define VREF_COMP_MOD_REG				(0x5C << 11)
+#define VREF_COMP_MOD_REG				(0x5C << MEM_MAP_SHIFT)
 
 #define VREF_COMP_MOD_OFST              (0)
 #define VREF_COMP_MOD_MSK               (0x00000FFF << VREF_COMP_MOD_OFST)
@@ -297,10 +297,10 @@
 
 
 /** DAQ Register */
-#define DAQ_REG							(0x5D << 11)								//TBD in firmware
+#define DAQ_REG							(0x5D << MEM_MAP_SHIFT)								//TBD in firmware
 
 /** Chip Power Register */
-#define CHIP_POWER_REG					(0x5E << 11)
+#define CHIP_POWER_REG					(0x5E << MEM_MAP_SHIFT)
 
 #define CHIP_POWER_ENABLE_OFST			(0)
 #define CHIP_POWER_ENABLE_MSK			(0x00000001 << CHIP_POWER_ENABLE_OFST)
@@ -309,7 +309,7 @@
 
 
 /** Temperature Control Register */
-#define TEMP_CTRL_REG                   (0x5F << 11)
+#define TEMP_CTRL_REG                   (0x5F << MEM_MAP_SHIFT)
 
 #define TEMP_CTRL_PROTCT_THRSHLD_OFST   (0)
 #define TEMP_CTRL_PROTCT_THRSHLD_MSK    (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
@@ -321,31 +321,31 @@
 
 
 /* Set Delay 64 bit register */
-#define SET_DELAY_LSB_REG     			(0x60 << 11)
-#define SET_DELAY_MSB_REG     			(0x61 << 11)
+#define SET_DELAY_LSB_REG     			(0x60 << MEM_MAP_SHIFT)
+#define SET_DELAY_MSB_REG     			(0x61 << MEM_MAP_SHIFT)
 
 /* Set Cycles 64 bit register */
-#define SET_CYCLES_LSB_REG    			(0x62 << 11)
-#define SET_CYCLES_MSB_REG    			(0x63 << 11)
+#define SET_CYCLES_LSB_REG    			(0x62 << MEM_MAP_SHIFT)
+#define SET_CYCLES_MSB_REG    			(0x63 << MEM_MAP_SHIFT)
 
 /* Set Frames 64 bit register */
-#define SET_FRAMES_LSB_REG   			(0x64 << 11)
-#define SET_FRAMES_MSB_REG    			(0x65 << 11)
+#define SET_FRAMES_LSB_REG   			(0x64 << MEM_MAP_SHIFT)
+#define SET_FRAMES_MSB_REG    			(0x65 << MEM_MAP_SHIFT)
 
 /* Set Period 64 bit register */
-#define SET_PERIOD_LSB_REG    			(0x66 << 11)
-#define SET_PERIOD_MSB_REG    			(0x67 << 11)
+#define SET_PERIOD_LSB_REG    			(0x66 << MEM_MAP_SHIFT)
+#define SET_PERIOD_MSB_REG    			(0x67 << MEM_MAP_SHIFT)
 
 /* Set Period 64 bit register */
-#define SET_EXPTIME_LSB_REG    			(0x68 << 11)
-#define SET_EXPTIME_MSB_REG    			(0x69 << 11)
+#define SET_EXPTIME_LSB_REG    			(0x68 << MEM_MAP_SHIFT)
+#define SET_EXPTIME_MSB_REG    			(0x69 << MEM_MAP_SHIFT)
 
 /* Trigger Delay 32 bit register */
-#define SET_TRIGGER_DELAY_LSB_REG       (0x70 << 11)
-#define SET_TRIGGER_DELAY_MSB_REG       (0x71 << 11)
+#define SET_TRIGGER_DELAY_LSB_REG       (0x70 << MEM_MAP_SHIFT)
+#define SET_TRIGGER_DELAY_MSB_REG       (0x71 << MEM_MAP_SHIFT)
 
 /* Module Coordinates Register 0 */
-#define COORD_0							(0x7C << 11)
+#define COORD_0							(0x7C << MEM_MAP_SHIFT)
 
 #define COORD_0_Y_OFST					(0)
 #define COORD_0_Y_MSK					(0x0000FFFF << COORD_0_Y_OFST)
@@ -353,7 +353,7 @@
 #define COORD_0_X_MSK					(0x0000FFFF << COORD_0_X_OFST)
 
 /* Module Coordinates Register 1 */
-#define COORD_1							(0x7D << 11)
+#define COORD_1							(0x7D << MEM_MAP_SHIFT)
 
 #define COORD_0_Z_OFST					(0)
 #define COORD_0_Z_MSK					(0x0000FFFF << COORD_0_Z_OFST)
diff --git a/slsDetectorSoftware/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer b/slsDetectorSoftware/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
index 692fbb0c361223560c43ece3c778c4ddc1b7e02d..236ebd9a2d6f05fc6982c4bab9a9c6fc55dc383a 100755
GIT binary patch
delta 33230
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diff --git a/slsDetectorSoftware/jungfrauDetectorServer/gitInfo.txt b/slsDetectorSoftware/jungfrauDetectorServer/gitInfo.txt
index 5987000ab..fcd27ac13 100644
--- a/slsDetectorSoftware/jungfrauDetectorServer/gitInfo.txt
+++ b/slsDetectorSoftware/jungfrauDetectorServer/gitInfo.txt
@@ -1,9 +1,9 @@
 Path: slsDetectorsPackage/slsDetectorSoftware/jungfrauDetectorServer 
 URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
 Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
-Repsitory UUID: 3da6a6df6556312f7467407a8b5691bdc478424e 
-Revision: 119 
+Repsitory UUID: a536f8ac9be2f064974da454273bfa828edb5bb1 
+Revision: 121 
 Branch: developer 
-Last Changed Author: Dhanya_Thattil 
-Last Changed Rev: 3597 
-Last Changed Date: 2018-02-07 10:44:06.000000002 +0100 ./RegisterDefs.h
+Last Changed Author: Erik_Frojdh 
+Last Changed Rev: 3669 
+Last Changed Date: 2018-02-22 10:31:42.834118468 +0100 ./blackfin.h~
diff --git a/slsDetectorSoftware/jungfrauDetectorServer/gitInfoJungfrau.h b/slsDetectorSoftware/jungfrauDetectorServer/gitInfoJungfrau.h
index 826314e3a..b87a74e6b 100644
--- a/slsDetectorSoftware/jungfrauDetectorServer/gitInfoJungfrau.h
+++ b/slsDetectorSoftware/jungfrauDetectorServer/gitInfoJungfrau.h
@@ -1,6 +1,6 @@
 #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
-#define GITREPUUID "3da6a6df6556312f7467407a8b5691bdc478424e"
-#define GITAUTH "Dhanya_Thattil"
-#define GITREV 0x3597
-#define GITDATE 0x20180207
+#define GITREPUUID "a536f8ac9be2f064974da454273bfa828edb5bb1"
+#define GITAUTH "Erik_Frojdh"
+#define GITREV 0x3669
+#define GITDATE 0x20180222
 #define GITBRANCH "developer"
diff --git a/slsDetectorSoftware/jungfrauDetectorServer/slsDetectorServer_defs.h b/slsDetectorSoftware/jungfrauDetectorServer/slsDetectorServer_defs.h
index c3002121e..e9657d6a4 100644
--- a/slsDetectorSoftware/jungfrauDetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorSoftware/jungfrauDetectorServer/slsDetectorServer_defs.h
@@ -8,8 +8,8 @@
 
 
 #define GOODBYE 					(-200)
-#define MIN_REQRD_VRSN_T_RD_API     0x171113
-#define REQRD_FRMWR_VRSN            0x171113
+#define MIN_REQRD_VRSN_T_RD_API     0x171220
+#define REQRD_FRMWR_VRSN            0x171220
 
 
 /* Struct Definitions */
diff --git a/slsDetectorSoftware/slsDetectorServer/blackfin.h b/slsDetectorSoftware/slsDetectorServer/blackfin.h
index 0c962493e..312adfdc8 100755
--- a/slsDetectorSoftware/slsDetectorServer/blackfin.h
+++ b/slsDetectorSoftware/slsDetectorServer/blackfin.h
@@ -12,6 +12,7 @@
 u_int32_t CSP0BASE = 0;
 #define CSP0 0x20200000
 #define MEM_SIZE 0x100000
+#define MEM_MAP_SHIFT 1
 
 
 
@@ -103,7 +104,7 @@ int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
  * @retuns 32 bit data read
  */
 u_int32_t readRegister(u_int32_t offset) {
-	return bus_r(offset << 11);
+	return bus_r(offset << MEM_MAP_SHIFT);
 }
 
 /**
@@ -112,7 +113,7 @@ u_int32_t readRegister(u_int32_t offset) {
  * @param data 32 bit data
  */
 u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
-	bus_w(offset << 11, data);
+	bus_w(offset << MEM_MAP_SHIFT, data);
 	return readRegister(offset);
 }