* add rx_restream_stop command. This allows to send a ZMQ dummy header any time user wants to do so. For example this allows to pre-configure the ZMQ processing software before the acquisition begins. Therefore, the dummy header was adapted in order to contain the fields stored in the receiver.
* renamed command, changed inherit, moved commands to zmq related section
* update filename in restreamstop
* renamed helper function, sorted header fields alphabetically
* fixed fnametostream set
* renamed functions, add SetFileName method, format JSON parameters order
* added python bindings and formatting (does nothing really)
* renamed restream stop functions to stream dummy
* checkout .github files from ed8c885
* release notes
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* fmt_install for local libs code
* fix: small python warning about escaped character \* in docstring
* copy with -r in copy_lib.sh due to cmake directory
* repalce conda build with conda-build, bump actions versions
* updated github actions versions to run on node 24
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
* macOS import guards to have servers compile
* SPI mock since we don't do any actual transfer using the virtual server
* /proc/self/exe alternative for macOS
* fixed python simulator test fixture
* clear_roi after every test to bring it back to default state, test passing multiple parameters
* Exposing the ctb api tests now to CI
* Revert "Exposing the ctb api tests now to CI"
This reverts commit 411fad1b27.
* fixed tests removed uneccessary stuff
* did not save properly
* updated documentation, renamed file
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* round CTB clocks to next closest possible value, added freq measurement
* added time for firmware to measrue actual value after frequency change
* add check for backwards compatibility
* change CTB and XCTB clock values to MHz, TODO: units and validation errors
* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?
* do the same for dbit and adcclk
* added tolerance to exptime, fixed test
* update default values in server defs
* added virtual check in Altera_PLL, update testcases
* change python and pyctbgui to accept and return floating point MHz
* update help and comments
* Dev/ctb clocks fix (#1434)
* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)
* incorrect unit typo
* cmd generation and compiles
* default to MHz, removed space between units for consistency with timers, min and max checks for clks
* in python, but need to change the default to Hz again for clean code and intuition
* allow ints, doubles, implicit conversions
* dont allow raw ints, doubles and implicit conversions
* fixed tests
* added operators for Hz in python
* fix test for min clk for xilinx ctb
* fix test
* fix python tests
* fixed xilinx period and default clks
* test fix
* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb
* removing 3 clock cycle code from xilinx as well
* formatting
* loadpattern before 3 clk cycles code
* actualtime and measurement time to be implemented in 100ns already in fw
* fix tests
* pyzmq dependency forthe tests
* fixed pyctbgui for freq
* insert tolerance check again
* also added tolerance check for patwaittime
* formatting
* minor: rounding test
* removed Rep redundant in ToString for freq
* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary
* minor, and binaries
* minor, default clk vals are 0 but set up at detector setup
* get frequency only for that unit
* tolerance process
* missed in previous commit
* some more changes to exptime and validations
* ctb is probably done
* periodleft and delayleft
* fixed xilinx freq conv as well
* fixed m3 bug, binaries
* xilinx: setup also done in stop server so that the clk is not 0
* missed a test marker
* binaries in
* review fixes, simpler validation of timers in ctb and xilinx ctb
* typo fix
* format
* fix tests
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added enum ReturnCode
* added cpp TCP Interface to slsDetectorServer
* added fmt to workflows
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* added fmt to workflow
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* add fmt to conda recipe
* some format changes
* dont use public headers of fmt
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* Matterhorn in tostring
* warning unused variable from other PR
* fixed build
* updated cmake
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* used pause insetad of sleep
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* updated binaries and fixed a warning by moving the usleep_bf to blackfin.c
* suppressed warnings
* cleaned up docs
* renamed function
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
* fix pyctbgui powerindex
* detangled power enable and power dac values
* displaybox for vchip
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* testing matterhorn1 SPI on altera CTB, works for dummy-chip
* added bf_usleep with proper timing for blackfin
* simplified spi firmware interface, removed write and readstrobe
* define constant for BFIN spi sleep
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* not allowing power names for dac names to prevent duplicate names
* wip
* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power
* binary in
* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands
* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested
* wip. client and xilinx todo
* wip: ctb power works, tests left
* fixed some tests
* added vchip check
* python cmds still left. wip
* fixed xilinx. python left
* wip
* wip. xilinx
* fixed powerchip for ctb
* power all returns all
* configtransceiver is removed
* wip python
* wip
* wip
* wip
* wip
* wip
* wip
* wip xilinx
* wip
* wip
* wip
* pybindings
* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector
* wip
* fixed tests
* fixes for python api
* wip
* python: moved powerlist to Ctb
* fixed tests to work for powelist in Ctb
* moved signallist, adclist, slowadc, slowadclist to Ctb
* throw approperiate error when no modules added for powers
* added dac test
* fix dac default names and test for dacs
* ctb dacs, yet to do othe rdacs
* dacs should work now even in tests
* run all tests
* DetectorPowers->NamedPowers in ctb
* comments
* removed unnecessary test code
* removed hard coded dac names in python NamedDacs and NamedPowers
* minor
* minor
* fixed error messages
* changed power to be able to set DAC directly, using enable and disable methods with enabled to get
* rx_roi fixed when there is no roi for a particular port. Fixed tests for it
* removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough
* restore md5
---------
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
* only run tests for pull-requests
* build gui and simulators
* trigger upon push to all branches
* renamed workflows
* added python tests
* added colorama and numpy
* added slsdet to pythonpath
* updated workflow name
* wip
* wip
* wip. xilinx left
* wip. xilinx
* wip
* wip. compiles
* fixed eiger test
* more fixes
* fixed virtual m3
* fix typos and bugs
* setting power to 0
* set power fixed
* updated server binaries
* minor
* refactoring
* get vchip refactoring
* eiger: unnecessary check for setsettings undefined
* retval pointer for printout
* eiger.wip, mV in boolean
* wip. gotthard2 and m3
* wip. jungfrau
* moench.wip
* compiles.wip
* fix eiger
* m3 fix vthresh
* fix ctband xilinx
* default pwr index = pwr_io
* minor:fn name and highvoltage to local var
* refactor funcs
* minor
* minor
* check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1
* minor
* updated versioning
* review changes: removing validateDACValue and other minor stuff
* binaries in
* wip
* refactored m3 vth
* minor review
* minor review
* m3 serverdac index fix
* minor
mazzol_a
lunin_l
Erik Frojdh
maliakal_d