 maliakal_d
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89c774dbf7
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nios programming: check file size first
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2020-01-31 11:24:48 +01:00 |
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 Dhanya ThattilandGitHub
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5ca3a1b685
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gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming (#74)
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2020-01-30 19:52:35 -08:00 |
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maliakal_d
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a9e375ed34
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gotthard2: bursttype to burstmode
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2020-01-23 11:03:14 +01:00 |
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maliakal_d
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f881133795
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get/set timing, generate data for gotthard2, vref_rstore instead of restore for gotthard2
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2020-01-22 18:18:56 +01:00 |
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maliakal_d
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8cbf3c62a9
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merge from developer
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2020-01-22 17:30:13 +01:00 |
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maliakal_d
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3ea2520615
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PR minor changes
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2020-01-22 13:55:10 +01:00 |
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maliakal_d
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e746256653
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gotthard2: gain updated
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2020-01-21 16:01:38 +01:00 |
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maliakal_d
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2e78484b61
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gotthard2 virtual server sends data
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2020-01-21 14:50:31 +01:00 |
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maliakal_d
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c4137dc309
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gotthard2: works
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2020-01-20 17:03:11 +01:00 |
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maliakal_d
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23dffa47df
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gotthard2 bug fix: no module attached
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2020-01-20 14:42:06 +01:00 |
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maliakal_d
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6cfd0f8962
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gotthard2: first edit
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2020-01-20 12:13:23 +01:00 |
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maliakal_d
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e8bdf5a505
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gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
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2020-01-16 15:33:35 +01:00 |
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maliakal_d
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9455a5fba1
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ctb: adcenable10g included, 10g readout enables included
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2019-11-27 17:28:57 +01:00 |
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maliakal_d
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6b391a34dc
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gotthard2: bug fix adconfiguration initialization
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2019-11-25 14:14:05 +01:00 |
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maliakal_d
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94382c1ece
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m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
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2019-11-25 10:54:30 +01:00 |
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maliakal_d
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a95ab1e13e
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servers: default compile not update versionign
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2019-11-22 17:23:07 +01:00 |
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maliakal_d
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c4675da0c3
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m3: reset fixed
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2019-11-22 16:40:43 +01:00 |
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maliakal_d
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d07873ee39
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mythen3 and gotthard2: wait request not needed, reset to be implemented
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2019-11-22 11:29:24 +01:00 |
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maliakal_d
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f8df11886a
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ctb: change in phase done in degrees (phase reset due to change in frequency)
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2019-11-21 15:08:38 +01:00 |
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maliakal_d
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d976c9fcf9
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gotthard2: phase direction like mythen3
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2019-11-21 14:41:54 +01:00 |
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maliakal_d
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1cea6af590
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mythen3, gotthard2: change phase, change freq bugfix
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2019-11-19 17:57:28 +01:00 |
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maliakal_d
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6a27207875
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gotthard2: vetoref, burstmode
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2019-11-15 18:59:27 +01:00 |
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maliakal_d
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a62d6a2fb8
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gotthard2: veto reference, better code for byte aligment in server
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2019-11-15 11:58:23 +01:00 |
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maliakal_d
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5518531620
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gotthard2: veto reference
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2019-11-14 19:01:10 +01:00 |
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maliakal_d
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21d23be522
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gotthard2: inejct channel done
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2019-11-13 16:49:35 +01:00 |
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maliakal_d
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28a5aa8342
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injectchannel WIP
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2019-11-13 15:11:11 +01:00 |
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maliakal_d
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72ac2745ea
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gotthard2: server fix enum for onchip dac
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2019-11-12 12:11:52 +01:00 |
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maliakal_d
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90c34e4942
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gotthard2, dacs and onchip dacs from config file
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2019-11-11 18:02:08 +01:00 |
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maliakal_d
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bb26b993ea
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servers, firmware check message to init message, minor
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2019-11-11 12:00:04 +01:00 |
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maliakal_d
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aaeaeab576
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gotthard2 on chip dacs: -1 should set for all chips
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2019-11-08 17:20:47 +01:00 |
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maliakal_d
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d7e2ab8ec4
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gotthard2: on chip dacs
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2019-11-08 17:09:57 +01:00 |
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maliakal_d
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615b3b2557
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WIP
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2019-11-06 19:07:00 +01:00 |
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maliakal_d
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1797d39216
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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
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2019-11-06 18:58:22 +01:00 |
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maliakal_d
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0f9fd5cd73
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rename of clkdivider to clkfrequency in servers
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2019-11-06 16:58:34 +01:00 |
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maliakal_d
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18b8720c17
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separated parameters and versions
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2019-11-06 16:43:59 +01:00 |
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maliakal_d
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705ddb7f42
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WIP
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2019-11-06 11:11:57 +01:00 |
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maliakal_d
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c3180737ed
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fixed jungfau virtual server as well
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2019-11-06 11:05:02 +01:00 |
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maliakal_d
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1f64d2a4e2
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speed separated
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2019-11-05 18:50:35 +01:00 |
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maliakal_d
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031241ae28
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timer split up
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2019-11-04 16:40:11 +01:00 |
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maliakal_d
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ba9a0c7917
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removed unused multi functions
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2019-10-30 18:20:16 +01:00 |
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maliakal_d
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fe467cdf70
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jungfrau dacs named
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2019-10-29 18:11:16 +01:00 |
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maliakal_d
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aa8610fb04
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WIP
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2019-10-29 10:11:36 +01:00 |
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Dhanya ThattilandGitHub
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995f0924e5
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Commandline (#66)
* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
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2019-10-21 10:29:06 +02:00 |
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maliakal_d
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df4f37efc6
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gotthard2, change clock, remember in degrees, and max clock divider is 512
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2019-10-17 18:29:57 +02:00 |
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maliakal_d
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e16212bd23
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tests for clk for gotthard2
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2019-10-17 16:51:40 +02:00 |
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maliakal_d
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be50344b45
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set clock divider, phase and get clock freq for gotthard2, priliminary
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2019-10-17 16:39:41 +02:00 |
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maliakal_d
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cfd3680176
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gotthard2 dacs
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2019-10-08 17:10:36 +02:00 |
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maliakal_d
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030cfacc9b
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WIP
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2019-10-08 10:57:07 +02:00 |
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maliakal_d
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0f99dd141e
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gotthard 2 server test bus
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2019-10-01 17:34:52 +02:00 |
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maliakal_d
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b3ff825ce8
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updated gotthard2 api etc
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2019-10-01 16:26:42 +02:00 |
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