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ctb: change in phase done in degrees (phase reset due to change in frequency)

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This commit is contained in:
maliakal_d 2019-11-21 15:08:38 +01:00
parent d976c9fcf9
commit f8df11886a
7 changed files with 16 additions and 20 deletions
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slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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26
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -1633,29 +1633,25 @@ int setFrequency(enum CLKINDEX ind, int val) {
return FAIL;
}
// Remembering adcphase/ dbit phase
int adcPhase = getPhase(ADC_CLK, 0);
FILE_LOG(logDEBUG1, ("\tRemembering ADC phase: %d\n", adcPhase));
int dbitPhase = getPhase(DBIT_CLK, 0);
FILE_LOG(logDEBUG1, ("\tRemembering DBIT phase: %d\n", dbitPhase));
// Remembering adcphase/ dbit phase in degrees
int adcPhase = getPhase(ADC_CLK, 1);
FILE_LOG(logDEBUG1, ("\tRemembering ADC phase: %d degrees\n", adcPhase));
int dbitPhase = getPhase(DBIT_CLK, 1);
FILE_LOG(logDEBUG1, ("\tRemembering DBIT phase: %d degrees\n", dbitPhase));
// Calculate and set output frequency
clkFrequency[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind], ind, clkFrequency[ind]));
// adc and dbit phase is reset by pll (when setting output frequency)
// phase reset by pll (when setting output frequency)
clkPhase[ADC_CLK] = 0;
clkPhase[DBIT_CLK] = 0;
// set the phase if custom set
if (clkPhase[ADC_CLK] != adcPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting ADC phase to %d\n", adcPhase));
setPhase(ADC_CLK, adcPhase, 0);
}
if (clkPhase[DBIT_CLK] != dbitPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting DBIT phase to %d\n", dbitPhase));
setPhase(DBIT_CLK, dbitPhase, 0);
}
// set the phase (reset by pll)
FILE_LOG(logINFO, ("\tCorrecting ADC phase to %d degrees\n", adcPhase));
setPhase(ADC_CLK, adcPhase, 1);
FILE_LOG(logINFO, ("\tCorrecting DBIT phase to %d degrees\n", dbitPhase));
setPhase(DBIT_CLK, dbitPhase, 1);
// required to reconfigure as adc clock is stopped temporarily when resetting pll (in changing output frequency)
AD9257_Configure();

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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -1154,11 +1154,11 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkPhase[SYSTEM_C3] = 0;
}
// set the phase in degreesif custom set
// set the phase in degrees (reset by pll)
{
int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i]));
FILE_LOG(logINFO, ("\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i]));
setPhase(i, oldPhases[i], 1);
}
}

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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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4
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -1179,11 +1179,11 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkPhase[SYSTEM_C2] = 0;
}
// set the phase in degreesif custom set
// set the phase in degrees (reset by pll)
{
int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i]));
FILE_LOG(logINFO, ("\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i]));
setPhase(i, oldPhases[i], 1);
}
}

2
slsSupportLib/include/versionAPI.h
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@ -4,9 +4,9 @@
#define APIRECEIVER 0x190722
#define APIGUI 0x190723
#define APIMOENCH 0x190820
#define APICTB 0x191111
#define APIGOTTHARD 0x191111
#define APIJUNGFRAU 0x191111
#define APIEIGER 0x191111
#define APIMYTHEN3 0x191121
#define APIGOTTHARD2 0x191121
#define APICTB 0x191121