9551 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
maliakal_d	3feed07d95	wip	2026-03-17 17:26:57 +01:00
maliakal_d	16f8925ffa	wip	2026-03-17 16:03:45 +01:00
maliakal_d	8fcff75086	wip python	2026-03-16 18:00:04 +01:00
maliakal_d	7621d964cd	configtransceiver is removed	2026-03-13 16:59:28 +01:00
maliakal_d	bf25493de3	power all returns all	2026-03-13 16:51:41 +01:00
maliakal_d	a537de69c3	fixed powerchip for ctb	2026-03-13 16:18:11 +01:00
maliakal_d	3b3180ef0f	wip. xilinx	2026-03-13 12:32:47 +01:00
maliakal_d	afb808aef8	wip	2026-03-13 11:35:21 +01:00
maliakal_d	951304c39c	fixed xilinx. python left	2026-03-11 16:45:02 +01:00
maliakal_d	297e23d1d2	Merge branch 'developer' into dev/xilinx_power_cmd	2026-03-11 15:39:58 +01:00
maliakal_d	03df08cb8c	python cmds still left. wip	2026-03-11 15:38:02 +01:00
mazzol_a	c86ca1eaec	per default pyqtgraph should read array as row-major (#1419) ... * per default pyqtgraph should read array as row-major * dont transform for analog images * never flip rows	2026-03-11 12:28:42 +01:00
maliakal_d	8bed67b8c8	added vchip check	2026-03-11 11:33:17 +01:00
maliakal_d	7b305a1faf	fixed some tests	2026-03-09 18:01:19 +01:00
maliakal_d	4875597533	wip: ctb power works, tests left	2026-03-09 15:54:18 +01:00
maliakal_d	0fe1df7959	wip. client and xilinx todo	2026-03-06 21:24:00 +01:00
maliakal_d	c2e8d5954d	wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested	2026-03-06 14:23:34 +01:00
maliakal_d	3846aec46e	Dev/jungfrau 1m root display support (#1364) ... * Aldo Mozzanica added support for 2 modules in 1M configuration for root display * deleted the wrong files	2026-03-05 17:13:38 +01:00
maliakal_d	6982b8cfa4	rm unnecessary hidden test tags (#1415) ... * removed hidden tags other than .detectorintegration and .disable_check_data_file * updated label, minor	2026-03-05 17:11:56 +01:00
maliakal_d	4723eb2ff4	dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands	2026-03-05 17:09:00 +01:00
maliakal_d	b2cd043358	Merge branch 'developer' into dev/xilinx_power_cmd	2026-03-05 12:34:49 +01:00
maliakal_dandErik Fröjdh	384b2480ab	Dev/fix no rx roi port (#1372) ... * rx_roi fixed when there is no roi for a particular port. Fixed tests for it * removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough * restore md5 --------- Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>	2026-03-05 12:28:57 +01:00
Erik Fröjdh	a1b8dccdd9	added support for int() for RegisterAddress and RegisterValue (#1414)	2026-03-05 11:35:21 +01:00
Erik Fröjdh	9f72688b9c	Adding offset to RegisterAddress (#1413) ... * implemented + and += for RegisterAddres and tests plus test cleanup	2026-03-05 09:32:21 +01:00
mazzol_a	6e090dbba2	Dev/update workflows (#1406) ... * only run tests for pull-requests * build gui and simulators * trigger upon push to all branches * renamed workflows * added python tests * added colorama and numpy * added slsdet to pythonpath * updated workflow name	2026-03-02 14:30:27 +01:00
maliakal_d	60f5db1224	xilinx: slow adcs (#1405) ... * xilinx: slow adcs * minor * xilinx: max reference voltage back to 2500mV for slow adcs ad7689	2026-02-27 17:17:11 +01:00
maliakal_d	a3e6cc90ea	server versions werent getting updated (#1407)	2026-02-27 17:12:27 +01:00
maliakal_d	0c5a9ceafc	binary in	2026-02-27 16:12:14 +01:00
maliakal_d	fe390f46bd	Merge branch 'developer' into dev/xilinx_power_cmd	2026-02-27 14:51:01 +01:00
maliakal_d	89fc3eac45	v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power	2026-02-26 14:59:26 +01:00
maliakal_d	a1c5bf971f	ctb: vchip doesnt validate with vlimit anymore (#1404)	2026-02-26 14:22:46 +01:00
maliakal_d	42da2e04b7	wip	2026-02-26 10:22:40 +01:00
mazzol_a	6a9eac17c8	removed make for the pyctbgui (#1401)	2026-02-25 16:40:32 +01:00
maliakal_d	ec787ca931	not allowing power names for dac names to prevent duplicate names	2026-02-24 10:58:46 +01:00
maliakal_d	e5b8e4ee80	fix the master hdf5 extension from aprevious PR (#1399)	2026-02-24 10:49:11 +01:00
maliakal_d	8f07d2a464	Dev/xilinx set dac rewrite (#1389) ... * wip * wip * wip. xilinx left * wip. xilinx * wip * wip. compiles * fixed eiger test * more fixes * fixed virtual m3 * fix typos and bugs * setting power to 0 * set power fixed * updated server binaries * minor * refactoring * get vchip refactoring * eiger: unnecessary check for setsettings undefined * retval pointer for printout * eiger.wip, mV in boolean * wip. gotthard2 and m3 * wip. jungfrau * moench.wip * compiles.wip * fix eiger * m3 fix vthresh * fix ctband xilinx * default pwr index = pwr_io * minor:fn name and highvoltage to local var * refactor funcs * minor * minor * check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1 * minor * updated versioning * review changes: removing validateDACValue and other minor stuff * binaries in * wip * refactored m3 vth * minor review * minor review * m3 serverdac index fix * minor	2026-02-23 14:23:13 +01:00
mazzol_aandmaliakal_d	f4658ab094	Dev/automate documentation build (#1357) ... * some test about building docs * indendation error * typo - * forgot to get package hdf5 * had to add shinx and doxygen as well * oke created environmnet file * typo * dont use conda * dont use conda * cannot upload artefact commit to gh-pages * correct copy * mmh * try with tokem * set write permisison * script to update main_index for versioned documentation * rename main_index to index * use absolute path in python script * update main_index upon a release * extract release type from version * copy release notes * updated links from devdoc to slsDetectorPackage, handling .md for new versions * changed page source * updated documentation link in README * add guideline for Package Versioning to documentation also used as a test * typo in workflow * why didnt it copy? * copied from build instead of docs * change back - trigger for push * only trigger for pull_requests and releases * removed conda environment file * automatically update documentation paths in release notes * only keep templated README.md * added README and updated links * update Release notes template manually * generate release notes script not needed anymore * modified readme to reflect dependencies insides build from source * subheadings in dependencies --------- Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2026-02-23 14:21:44 +01:00
mazzol_aandErik Fröjdh	f8723eb0d8	Dev/use aare in pyctbgui (#1379) ... * added CMakeLists.txt for pyctbgui * using aare decoders * removed c code * showing proper error message * dvjgj --------- Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>	2026-02-23 12:33:10 +01:00
mazzol_a	65c8f2c7d8	dev/handes trailing / in filepath (#1391) ... * member filePath in Implementation is std::filesystem::path, some refactoring * PR Review * adapted function signature - compiled with hdf5 on	2026-02-17 17:11:33 +01:00
muelle_m1	26729b06cb	added copy of ctbDetectorServer to auto-deploy	2026-02-10 16:14:01 +01:00
maliakal_d	1c44a66964	formatted	2026-02-10 16:10:51 +01:00
mazzol_a	1c18803dc9	Merge pull request #1385 from slsdetectorgroup/dev/fix_update_ctb ... skip if not plotted	2026-02-09 15:22:16 +01:00
mazzol_a	b3f5473385	Merge branch 'developer' into dev/fix_update_ctb	2026-02-09 15:17:02 +01:00
Erik Fröjdh	3f4df445f1	send back the result of the SPI write (#1387)	2026-02-09 13:50:35 +01:00
mazzol_a	ec6a8b6d66	added range update	2026-02-09 12:42:35 +01:00
mazzol_a	78044b2783	always write all wave data & uncheck plot if digital bit unchecked	2026-02-06 16:41:04 +01:00
mazzol_a	7f5b26743f	uff introduced another bug	2026-02-06 14:55:18 +01:00
mazzol_a	92da709bda	skip if not plotted	2026-02-06 14:39:11 +01:00
Erik Fröjdh	0992c7ae4c	Read and write SPI for Xilinx CTB (#1381) ... -readSpi and writeSpi in C++ and Python API	2026-02-05 17:20:47 +01:00
muelle_m1	fb58fefe57	added RegDefs for 1G support on XCTB	2026-02-05 15:11:31 +01:00