Add logic for EXT/EN to DDG and MCS for flOMNI #136

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appel_c merged 12 commits from feat/add_flomni_ext_en into main 2026-02-16 10:41:35 +01:00

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appel_c commented 2026-02-02 10:34:21 +01:00

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PR to extend the logic on the DDG and the MCS card for operation with flOMNI. THe implementation now supports flOMNI fly scans, for which the mcs card is setup in a different fashion. We also configure the DDG differently in that scenario. In addition, we added the logic to the two devices to be able to cope with EXT/EN signals configured on the DDG. This is a first working version, but should be crosschecked for other built-in fly scans to make sure that they still work as expected.

PR to extend the logic on the DDG and the MCS card for operation with flOMNI. THe implementation now supports flOMNI fly scans, for which the mcs card is setup in a different fashion. We also configure the DDG differently in that scenario. In addition, we added the logic to the two devices to be able to cope with EXT/EN signals configured on the DDG. This is a first working version, but should be crosschecked for other built-in fly scans to make sure that they still work as expected.

appel_c added 1 commit 2026-02-02 10:34:22 +01:00

feat: add logic for ext/en in ddg, mcs and flomni ed8d012632

appel_c added 1 commit 2026-02-09 08:29:13 +01:00

fix(fast-shutter): Fix cSAXS fast shutter device 6fad4f2034

appel_c added 1 commit 2026-02-09 08:39:23 +01:00

fix(configs): add connectionTimeout=20s defaults to devices with SocketController c3aa882b1d

appel_c added 2 commits 2026-02-09 14:11:04 +01:00

fix(shutter); fix shutter_readback signal 8849b9ffea

refactor(ddg): Add fsh signal to ddg, improve trigger logic. 32b4c39659

bec_bl_push-gitea added 1 commit 2026-02-10 10:59:32 +01:00

fixes at beamline 2814add2de

appel_c added 2 commits 2026-02-11 08:53:06 +01:00

refactor(ddg1): Use mcs acquiring status to resolve trigger of DDG1 a45aa094ef

fix(fast-shutter): Add close shutter on 'stop' call. 8195c12a35

appel_c added 1 commit 2026-02-11 09:45:46 +01:00

fix(ddg1): revert to shutter signal as mcs status signal is too slow f8d2af4c5b

appel_c added 1 commit 2026-02-11 11:22:14 +01:00

fix(ddg): fix logic to resolve trigger on ddg1. 67ef20cfc8

appel_c added 1 commit 2026-02-11 11:50:25 +01:00

tests: fix tests for ddg1 75cc672f08

appel_c requested review from holler 2026-02-11 11:53:50 +01:00

appel_c requested review from wakonig_k 2026-02-11 11:53:50 +01:00

holler approved these changes 2026-02-11 13:11:45 +01:00

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Looks great to me. One thing I am currently wondering is the DDG line where we removed the shutter close time.
d = a + exp_time * burst_count + 1ms (to allow the shutter to close)
Removing the 1 ms makes sense because the shutter shall start closing immediately after the exposure ends.
Having some additional delay on another channel to account for the close time could be used to block the delay generator for the full shutter close time of 2 ms. Then the entire setup would be in a clean state for opening the shutter again.
With the new fast shutter system, I actually execute the full close movement before starting the open movement. If the trigger signal for opening comes to early, the shutter will still open, but then it will not take 2 ms but the full close open cycle of 2+2 ms.

Looks great to me. One thing I am currently wondering is the DDG line where we removed the shutter close time. d = a + exp_time * burst_count + 1ms (to allow the shutter to close) Removing the 1 ms makes sense because the shutter shall start closing immediately after the exposure ends. Having some additional delay on another channel to account for the close time could be used to block the delay generator for the full shutter close time of 2 ms. Then the entire setup would be in a clean state for opening the shutter again. With the new fast shutter system, I actually execute the full close movement before starting the open movement. If the trigger signal for opening comes to early, the shutter will still open, but then it will not take 2 ms but the full close open cycle of 2+2 ms.

bec_bl_push-gitea added 1 commit 2026-02-16 10:18:57 +01:00

refactor: add gh signal for ddg1 with TTL for full acquisition 7a2c6629f7

appel_c merged commit 7a2c6629f7 into main 2026-02-16 10:41:35 +01:00

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acerbo_a (acerbo_a) bec-gitea celcer_t (celcer_t) debenjak_l (debenjak_l) diaz (diaz) divall_e (divall_e) guizar_m (guizar_m) haghta_s (haghta_s) holler (holler) lombosi_c (lombosi_c) menzel (menzel) perl_d (perl_d) usov_i (usov_i) wakonig_k (wakonig_k) wang_x1 (wang_x1) wyzula_j (wyzula_j) zamofing_t (zamofing_t)

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Reference: bec/csaxs_bec#136