 ritt
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6b57df374f
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Added drs_exam_2018.cpp
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2017-12-13 11:16:21 +01:00 |
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ritt
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426776ab0c
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Changed comment
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2017-12-12 14:03:06 +01:00 |
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ritt
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aded8e478f
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Fixed code for external trigger
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2017-12-12 13:58:01 +01:00 |
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ritt
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7916c5dbab
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Compiled drscl.exe
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2017-10-11 10:03:20 +02:00 |
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ritt
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ed441935a7
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Optimized chip tests for good new chips with lower leakage current
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2017-10-10 17:36:34 +02:00 |
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ritt
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9df66d5c96
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Implemented “-l” option to check USB
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2017-04-12 10:26:50 +02:00 |
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ritt
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9e6aa0e059
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Recompiled under Windows
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2017-01-09 17:06:59 +01:00 |
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ritt
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8461281a67
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Optimized chip test for new test board, implemented leakage current limit of 100 pA
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2017-01-09 16:54:01 +01:00 |
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ritt
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118ded9ac0
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Added optional histogram output in chip test
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2016-12-05 14:03:06 +01:00 |
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ritt
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dfe33dc32d
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Made chip test work with normal V5 board
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2016-12-01 12:25:02 +01:00 |
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ritt
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50964d81ca
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Updated examples to new project structure
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2016-12-01 09:31:25 +01:00 |
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ritt
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7bca3829fa
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Copied files over from SVN repositories
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2016-11-14 15:38:40 +01:00 |
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