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||||
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<!-- along with the project source files, is sufficient to open and -->
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|
||||
<property xil_pn:name="Key 4 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Key 5 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load Setting File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Load Timing Specification Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 0 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 1 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 2 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 3 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 4 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Location of Key 5 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Critical Paths" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Critical Paths Synthesis" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Start/End Points" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="drs4_eval5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tq144" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="drs4_eval5_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="drs4_eval5_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="drs4_eval5_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="drs4_eval5_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Push Tristates across Process/Block Boundaries" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="drs4_eval5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Clock Frequencies" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Critical Paths" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Missing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Timing Summary" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Timing Violations" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setting Output File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show Clock Domain Crossing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show Net Fan Out" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting CBC Value (Hex)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Key" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Symbolic FSM Compiler" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Sysgen Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Transform Set/Reset on DFFs to Latches" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tri-state Buffer Transformation Mode" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Update modelsim.ini File for Xilinx SmartModel Use" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP48" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Safe FSM" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax Precision" xil_pn:value="VHDL 93" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="drs4_eval5.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|drs4_eval4|arch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="usb_mezz3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_HdlTemplateLang" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_HdlTemplateName" xil_pn:value="usb_mezz3.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-12-04T15:29:14" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7B3B4F10DCBE4CAD8D0CA9E4D95B4253" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_xawInstTempTargetLang" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Binary file not shown.
@@ -0,0 +1,332 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: FX2.h
|
||||
// Contents: EZ-USB FX2/FX2LP/FX1 constants, macros, datatypes, globals, and library
|
||||
// function prototypes.
|
||||
//
|
||||
// $Archive: /USB/Target/Inc/Fx2.h $
|
||||
// $Date: 3/23/05 2:30p $
|
||||
// $Revision: 16 $
|
||||
// $Id: Fx2.h 11698 2008-06-12 15:28:35Z ritt@PSI.CH $
|
||||
//
|
||||
// Copyright (c) 2005 Cypress Semiconductor, All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef FX2_H //Header sentry
|
||||
#define FX2_H
|
||||
|
||||
#define INTERNAL_DSCR_ADDR 0x0080 // Relocate Descriptors to 0x80
|
||||
#define bmSTRETCH 0x07
|
||||
#define FW_STRETCH_VALUE 0x0 // Set stretch to 0 in frameworks
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Constants
|
||||
//-----------------------------------------------------------------------------
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define bmBIT0 0x01
|
||||
#define bmBIT1 0x02
|
||||
#define bmBIT2 0x04
|
||||
#define bmBIT3 0x08
|
||||
#define bmBIT4 0x10
|
||||
#define bmBIT5 0x20
|
||||
#define bmBIT6 0x40
|
||||
#define bmBIT7 0x80
|
||||
|
||||
#define DEVICE_DSCR 0x01 // Descriptor type: Device
|
||||
#define CONFIG_DSCR 0x02 // Descriptor type: Configuration
|
||||
#define STRING_DSCR 0x03 // Descriptor type: String
|
||||
#define INTRFC_DSCR 0x04 // Descriptor type: Interface
|
||||
#define ENDPNT_DSCR 0x05 // Descriptor type: End Point
|
||||
#define DEVQUAL_DSCR 0x06 // Descriptor type: Device Qualifier
|
||||
#define OTHERSPEED_DSCR 0x07 // Descriptor type: Other Speed Configuration
|
||||
|
||||
#define bmBUSPWR bmBIT7 // Config. attribute: Bus powered
|
||||
#define bmSELFPWR bmBIT6 // Config. attribute: Self powered
|
||||
#define bmRWU bmBIT5 // Config. attribute: Remote Wakeup
|
||||
|
||||
#define bmEPOUT bmBIT7
|
||||
#define bmEPIN 0x00
|
||||
|
||||
#define EP_CONTROL 0x00 // End Point type: Control
|
||||
#define EP_ISO 0x01 // End Point type: Isochronous
|
||||
#define EP_BULK 0x02 // End Point type: Bulk
|
||||
#define EP_INT 0x03 // End Point type: Interrupt
|
||||
|
||||
#define SUD_SIZE 8 // Setup data packet size
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
//Added for HID
|
||||
|
||||
#define SETUP_MASK 0x60 //Used to mask off request type
|
||||
#define SETUP_STANDARD_REQUEST 0 //Standard Request
|
||||
#define SETUP_CLASS_REQUEST 0x20 //Class Request
|
||||
#define SETUP_VENDOR_REQUEST 0x40 //Vendor Request
|
||||
#define SETUP_RESERVED_REQUEST 0x60 //Reserved or illegal request
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#define SC_GET_STATUS 0x00 // Setup command: Get Status
|
||||
#define SC_CLEAR_FEATURE 0x01 // Setup command: Clear Feature
|
||||
#define SC_RESERVED 0x02 // Setup command: Reserved
|
||||
#define SC_SET_FEATURE 0x03 // Setup command: Set Feature
|
||||
#define SC_SET_ADDRESS 0x05 // Setup command: Set Address
|
||||
#define SC_GET_DESCRIPTOR 0x06 // Setup command: Get Descriptor
|
||||
#define SC_SET_DESCRIPTOR 0x07 // Setup command: Set Descriptor
|
||||
#define SC_GET_CONFIGURATION 0x08 // Setup command: Get Configuration
|
||||
#define SC_SET_CONFIGURATION 0x09 // Setup command: Set Configuration
|
||||
#define SC_GET_INTERFACE 0x0a // Setup command: Get Interface
|
||||
#define SC_SET_INTERFACE 0x0b // Setup command: Set Interface
|
||||
#define SC_SYNC_FRAME 0x0c // Setup command: Sync Frame
|
||||
#define SC_ANCHOR_LOAD 0xa0 // Setup command: Anchor load
|
||||
|
||||
#define GD_DEVICE 0x01 // Get descriptor: Device
|
||||
#define GD_CONFIGURATION 0x02 // Get descriptor: Configuration
|
||||
#define GD_STRING 0x03 // Get descriptor: String
|
||||
#define GD_INTERFACE 0x04 // Get descriptor: Interface
|
||||
#define GD_ENDPOINT 0x05 // Get descriptor: Endpoint
|
||||
#define GD_DEVICE_QUALIFIER 0x06 // Get descriptor: Device Qualifier
|
||||
#define GD_OTHER_SPEED_CONFIGURATION 0x07 // Get descriptor: Other Configuration
|
||||
#define GD_INTERFACE_POWER 0x08 // Get descriptor: Interface Power
|
||||
#define GD_HID 0x21 // Get descriptor: HID
|
||||
#define GD_REPORT 0x22 // Get descriptor: Report
|
||||
|
||||
#define GS_DEVICE 0x80 // Get Status: Device
|
||||
#define GS_INTERFACE 0x81 // Get Status: Interface
|
||||
#define GS_ENDPOINT 0x82 // Get Status: End Point
|
||||
|
||||
#define FT_DEVICE 0x00 // Feature: Device
|
||||
#define FT_ENDPOINT 0x02 // Feature: End Point
|
||||
|
||||
#define I2C_IDLE 0 // I2C Status: Idle mode
|
||||
#define I2C_SENDING 1 // I2C Status: I2C is sending data
|
||||
#define I2C_RECEIVING 2 // I2C Status: I2C is receiving data
|
||||
#define I2C_PRIME 3 // I2C Status: I2C is receiving the first byte of a string
|
||||
#define I2C_STOP 5 // I2C Status: I2C waiting for stop completion
|
||||
#define I2C_BERROR 6 // I2C Status: I2C error; Bit Error
|
||||
#define I2C_NACK 7 // I2C Status: I2C error; No Acknowledge
|
||||
#define I2C_OK 8 // I2C positive return code
|
||||
#define I2C_WAITSTOP 9 // I2C Status: Wait for STOP complete
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Macros
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
|
||||
#define LSB(word) (BYTE)((WORD)(word) & 0xff)
|
||||
|
||||
#define SWAP_ENDIAN(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1];\
|
||||
((BYTE*)&word)[1] ^= ((BYTE*)&word)[0];\
|
||||
((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
|
||||
|
||||
#define EZUSB_IRQ_ENABLE() EUSB = 1
|
||||
#define EZUSB_IRQ_DISABLE() EUSB = 0
|
||||
#define EZUSB_IRQ_CLEAR() EXIF &= ~0x10 // IE2_
|
||||
|
||||
#define EZUSB_STALL_EP0() EP0CS |= bmEPSTALL
|
||||
|
||||
// WRITEDELAY() has been replaced by SYNCDELAY; macro in fx2sdly.h
|
||||
// ...it is here for backwards compatibility...
|
||||
|
||||
// the WRITEDELAY macro compiles to the time equivalent of 3 NOPs.
|
||||
// It is used in the frameworks to allow for write recovery time
|
||||
// requirements of certain registers. This is only necessary for
|
||||
// EZ-USB FX parts. See the EZ-USB FX TRM for
|
||||
// more information on write recovery time issues.
|
||||
#define WRITEDELAY() {char writedelaydummy = 0;}
|
||||
// if this firmware will never run on an EZ-USB FX part replace
|
||||
// with:
|
||||
// #define WRITEDELAY()
|
||||
|
||||
// macro to reset and endpoint data toggle
|
||||
#define EZUSB_RESET_DATA_TOGGLE(ep) TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x0F));\
|
||||
TOGCTL |= bmRESETTOGGLE
|
||||
|
||||
|
||||
#define EZUSB_ENABLE_RSMIRQ() (EICON |= 0x20) // Enable Resume Interrupt (EPFI_)
|
||||
#define EZUSB_DISABLE_RSMIRQ() (EICON &= ~0x20) // Disable Resume Interrupt (EPFI_)
|
||||
#define EZUSB_CLEAR_RSMIRQ() (EICON &= ~0x10) // Clear Resume Interrupt Flag (PFI_)
|
||||
|
||||
#define EZUSB_GETI2CSTATUS() (I2CPckt.status)
|
||||
#define EZUSB_CLEARI2CSTATUS() if((I2CPckt.status == I2C_BERROR) || (I2CPckt.status == I2C_NACK))\
|
||||
I2CPckt.status = I2C_IDLE;
|
||||
|
||||
#define EZUSB_ENABLEBP() (BREAKPT |= bmBPEN)
|
||||
#define EZUSB_DISABLEBP() (BREAKPT &= ~bmBPEN)
|
||||
#define EZUSB_CLEARBP() (BREAKPT |= bmBREAK)
|
||||
#define EZUSB_BP(addr) BPADDRH = (BYTE)(((WORD)addr >> 8) & 0xff);\
|
||||
BPADDRL = (BYTE)addr
|
||||
|
||||
#define EZUSB_EXTWAKEUP() (((WAKEUPCS & bmWU2) && (WAKEUPCS & bmWU2EN)) ||\
|
||||
((WAKEUPCS & bmWU) && (WAKEUPCS & bmWUEN)))
|
||||
|
||||
#define EZUSB_HIGHSPEED() (USBCS & bmHSM)
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Datatypes
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned long DWORD;
|
||||
typedef bit BOOL;
|
||||
|
||||
#define INT0_VECT 0
|
||||
#define TMR0_VECT 1
|
||||
#define INT1_VECT 2
|
||||
#define TMR1_VECT 3
|
||||
#define COM0_VECT 4
|
||||
#define TMR2_VECT 5
|
||||
#define WKUP_VECT 6
|
||||
#define COM1_VECT 7
|
||||
#define USB_VECT 8
|
||||
#define I2C_VECT 9
|
||||
#define INT4_VECT 10
|
||||
#define INT5_VECT 11
|
||||
#define INT6_VECT 12
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length;
|
||||
BYTE type;
|
||||
}DSCR;
|
||||
|
||||
typedef struct // Device Descriptor
|
||||
{
|
||||
BYTE length; // Descriptor length ( = sizeof(DEVICEDSCR) )
|
||||
BYTE type; // Decriptor type (Device = 1)
|
||||
BYTE spec_ver_minor; // Specification Version (BCD) minor
|
||||
BYTE spec_ver_major; // Specification Version (BCD) major
|
||||
BYTE dev_class; // Device class
|
||||
BYTE sub_class; // Device sub-class
|
||||
BYTE protocol; // Device sub-sub-class
|
||||
BYTE max_packet; // Maximum packet size
|
||||
WORD vendor_id; // Vendor ID
|
||||
WORD product_id; // Product ID
|
||||
WORD version_id; // Product version ID
|
||||
BYTE mfg_str; // Manufacturer string index
|
||||
BYTE prod_str; // Product string index
|
||||
BYTE serialnum_str; // Serial number string index
|
||||
BYTE configs; // Number of configurations
|
||||
}DEVICEDSCR;
|
||||
|
||||
typedef struct // Device Qualifier Descriptor
|
||||
{
|
||||
BYTE length; // Descriptor length ( = sizeof(DEVICEQUALDSCR) )
|
||||
BYTE type; // Decriptor type (Device Qualifier = 6)
|
||||
BYTE spec_ver_minor; // Specification Version (BCD) minor
|
||||
BYTE spec_ver_major; // Specification Version (BCD) major
|
||||
BYTE dev_class; // Device class
|
||||
BYTE sub_class; // Device sub-class
|
||||
BYTE protocol; // Device sub-sub-class
|
||||
BYTE max_packet; // Maximum packet size
|
||||
BYTE configs; // Number of configurations
|
||||
BYTE reserved0;
|
||||
}DEVICEQUALDSCR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length; // Configuration length ( = sizeof(CONFIGDSCR) )
|
||||
BYTE type; // Descriptor type (Configuration = 2)
|
||||
WORD config_len; // Configuration + End Points length
|
||||
BYTE interfaces; // Number of interfaces
|
||||
BYTE index; // Configuration number
|
||||
BYTE config_str; // Configuration string
|
||||
BYTE attrib; // Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu
|
||||
BYTE power; // Power requirement (div 2 ma)
|
||||
}CONFIGDSCR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length; // Interface descriptor length ( - sizeof(INTRFCDSCR) )
|
||||
BYTE type; // Descriptor type (Interface = 4)
|
||||
BYTE index; // Zero-based index of this interface
|
||||
BYTE alt_setting; // Alternate setting
|
||||
BYTE ep_cnt; // Number of end points
|
||||
BYTE class; // Interface class
|
||||
BYTE sub_class; // Interface sub class
|
||||
BYTE protocol; // Interface sub sub class
|
||||
BYTE interface_str; // Interface descriptor string index
|
||||
}INTRFCDSCR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length; // End point descriptor length ( = sizeof(ENDPNTDSCR) )
|
||||
BYTE type; // Descriptor type (End point = 5)
|
||||
BYTE addr; // End point address
|
||||
BYTE ep_type; // End point type
|
||||
BYTE mp_L; // Maximum packet size
|
||||
BYTE mp_H;
|
||||
BYTE interval; // Interrupt polling interval
|
||||
}ENDPNTDSCR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length; // String descriptor length
|
||||
BYTE type; // Descriptor type
|
||||
}STRINGDSCR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE cntrl; // End point control register
|
||||
BYTE bytes; // End point buffer byte count
|
||||
}EPIOC;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length;
|
||||
BYTE *dat;
|
||||
BYTE count;
|
||||
BYTE status;
|
||||
}I2CPCKT;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Globals
|
||||
//-----------------------------------------------------------------------------
|
||||
extern code BYTE USB_AutoVector;
|
||||
|
||||
extern WORD pDeviceDscr;
|
||||
extern WORD pDeviceQualDscr;
|
||||
extern WORD pHighSpeedConfigDscr;
|
||||
extern WORD pFullSpeedConfigDscr;
|
||||
extern WORD pConfigDscr;
|
||||
extern WORD pOtherConfigDscr;
|
||||
extern WORD pStringDscr;
|
||||
|
||||
extern code DEVICEDSCR DeviceDscr;
|
||||
extern code DEVICEQUALDSCR DeviceQualDscr;
|
||||
extern code CONFIGDSCR HighSpeedConfigDscr;
|
||||
extern code CONFIGDSCR FullSpeedConfigDscr;
|
||||
extern code STRINGDSCR StringDscr;
|
||||
extern code DSCR UserDscr;
|
||||
|
||||
extern I2CPCKT I2CPckt;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Function Prototypes
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
extern void EZUSB_Renum(void);
|
||||
extern void EZUSB_Discon(BOOL renum);
|
||||
|
||||
extern void EZUSB_Susp(void);
|
||||
extern void EZUSB_Resume(void);
|
||||
|
||||
extern void EZUSB_Delay1ms(void);
|
||||
extern void EZUSB_Delay(WORD ms);
|
||||
|
||||
extern CONFIGDSCR xdata* EZUSB_GetConfigDscr(BYTE ConfigIdx);
|
||||
extern INTRFCDSCR xdata* EZUSB_GetIntrfcDscr(BYTE ConfigIdx, BYTE IntrfcIdx, BYTE AltSetting);
|
||||
extern STRINGDSCR xdata* EZUSB_GetStringDscr(BYTE StrIdx);
|
||||
extern DSCR xdata* EZUSB_GetDscr(BYTE index, DSCR* dscr, BYTE type);
|
||||
|
||||
extern void EZUSB_InitI2C(void);
|
||||
extern BOOL EZUSB_WriteI2C_(BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
extern BOOL EZUSB_ReadI2C_(BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
extern BOOL EZUSB_WriteI2C(BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
extern BOOL EZUSB_ReadI2C(BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
extern void EZUSB_WaitForEEPROMWrite(BYTE addr);
|
||||
|
||||
extern void modify_endpoint_stall(BYTE epid, BYTE stall);
|
||||
|
||||
#endif // FX2_H
|
||||
@@ -0,0 +1,155 @@
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; File: usbjmptb.a51
|
||||
;; Contents:
|
||||
;;
|
||||
;; $Archive: /USB/Target/Lib/lp/USBJmpTb.a51 $
|
||||
;; $Date: 8/12/03 3:32p $
|
||||
;; $Revision: 1 $
|
||||
;;
|
||||
;;
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; Copyright 2003, Cypress Semiconductor Corporation
|
||||
;;
|
||||
;; This software is owned by Cypress Semiconductor Corporation (Cypress) and is
|
||||
;; protected by United States copyright laws and international treaty provisions. Cypress
|
||||
;; hereby grants to Licensee a personal, non-exclusive, non-transferable license to copy,
|
||||
;; use, modify, create derivative works of, and compile the Cypress Source Code and
|
||||
;; derivative works for the sole purpose of creating custom software in support of Licensee
|
||||
;; product ("Licensee Product") to be used only in conjunction with a Cypress integrated
|
||||
;; circuit. Any reproduction, modification, translation, compilation, or representation of this
|
||||
;; software except as specified above is prohibited without the express written permission of
|
||||
;; Cypress.
|
||||
;;
|
||||
;; Disclaimer: Cypress makes no warranty of any kind, express or implied, with regard to
|
||||
;; this material, including, but not limited to, the implied warranties of merchantability and
|
||||
;; fitness for a particular purpose. Cypress reserves the right to make changes without
|
||||
;; further notice to the materials described herein. Cypress does not assume any liability
|
||||
;; arising out of the application or use of any product or circuit described herein. Cypress’
|
||||
;; products described herein are not authorized for use as components in life-support
|
||||
;; devices.
|
||||
;;
|
||||
;; This software is protected by and subject to worldwide patent coverage, including U.S.
|
||||
;; and foreign patents. Use may be limited by and subject to the Cypress Software License
|
||||
;; Agreement.
|
||||
;;-----------------------------------------------------------------------------
|
||||
NAME USBJmpTbl
|
||||
|
||||
extrn code (ISR_Sudav, ISR_Sof, ISR_Sutok, ISR_Susp, ISR_Ures, ISR_Highspeed, ISR_Ep0ack, ISR_Stub, ISR_Ep0in, ISR_Ep0out, ISR_Ep1in, ISR_Ep1out, ISR_Ep2inout, ISR_Ep4inout, ISR_Ep6inout, ISR_Ep8inout,ISR_Ibn)
|
||||
|
||||
extrn code (ISR_Ep0pingnak, ISR_Ep1pingnak, ISR_Ep2pingnak, ISR_Ep4pingnak, ISR_Ep6pingnak, ISR_Ep8pingnak, ISR_Errorlimit, ISR_Ep2piderror, ISR_Ep4piderror, ISR_Ep6piderror, ISR_Ep8piderror, ISR_Ep2pflag)
|
||||
|
||||
extrn code (ISR_Ep4pflag, ISR_Ep6pflag, ISR_Ep8pflag, ISR_Ep2eflag, ISR_Ep4eflag, ISR_Ep6eflag, ISR_Ep8eflag, ISR_Ep2fflag, ISR_Ep4fflag, ISR_Ep6fflag, ISR_Ep8fflag, ISR_GpifComplete, ISR_GpifWaveform)
|
||||
|
||||
public USB_Int2AutoVector, USB_Int4AutoVector, USB_Jump_Table
|
||||
;------------------------------------------------------------------------------
|
||||
; Interrupt Vectors
|
||||
;------------------------------------------------------------------------------
|
||||
CSEG AT 43H
|
||||
USB_Int2AutoVector equ $ + 2
|
||||
ljmp USB_Jump_Table ; Autovector will replace byte 45
|
||||
|
||||
CSEG AT 53H
|
||||
USB_Int4AutoVector equ $ + 2
|
||||
ljmp USB_Jump_Table ; Autovector will replace byte 55
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; USB Jump Table
|
||||
;------------------------------------------------------------------------------
|
||||
?PR?USB_JUMP_TABLE?USBJT segment code page ; Place jump table on a page boundary
|
||||
RSEG ?PR?USB_JUMP_TABLE?USBJT ; autovector jump table
|
||||
USB_Jump_Table:
|
||||
ljmp ISR_Sudav ;(00) Setup Data Available
|
||||
db 0
|
||||
ljmp ISR_Sof ;(04) Start of Frame
|
||||
db 0
|
||||
ljmp ISR_Sutok ;(08) Setup Data Loading
|
||||
db 0
|
||||
ljmp ISR_Susp ;(0C) Global Suspend
|
||||
db 0
|
||||
ljmp ISR_Ures ;(10) USB Reset
|
||||
db 0
|
||||
ljmp ISR_Highspeed ;(14) Entered High Speed
|
||||
db 0
|
||||
ljmp ISR_Ep0ack ;(18) EP0ACK
|
||||
db 0
|
||||
ljmp ISR_Stub ;(1C) Reserved
|
||||
db 0
|
||||
ljmp ISR_Ep0in ;(20) EP0 In
|
||||
db 0
|
||||
ljmp ISR_Ep0out ;(24) EP0 Out
|
||||
db 0
|
||||
ljmp ISR_Ep1in ;(28) EP1 In
|
||||
db 0
|
||||
ljmp ISR_Ep1out ;(2C) EP1 Out
|
||||
db 0
|
||||
ljmp ISR_Ep2inout ;(30) EP2 In/Out
|
||||
db 0
|
||||
ljmp ISR_Ep4inout ;(34) EP4 In/Out
|
||||
db 0
|
||||
ljmp ISR_Ep6inout ;(38) EP6 In/Out
|
||||
db 0
|
||||
ljmp ISR_Ep8inout ;(3C) EP8 In/Out
|
||||
db 0
|
||||
ljmp ISR_Ibn ;(40) IBN
|
||||
db 0
|
||||
ljmp ISR_Stub ;(44) Reserved
|
||||
db 0
|
||||
ljmp ISR_Ep0pingnak ;(48) EP0 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Ep1pingnak ;(4C) EP1 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Ep2pingnak ;(50) EP2 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Ep4pingnak ;(54) EP4 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Ep6pingnak ;(58) EP6 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Ep8pingnak ;(5C) EP8 PING NAK
|
||||
db 0
|
||||
ljmp ISR_Errorlimit ;(60) Error Limit
|
||||
db 0
|
||||
ljmp ISR_Stub ;(64) Reserved
|
||||
db 0
|
||||
ljmp ISR_Stub ;(68) Reserved
|
||||
db 0
|
||||
ljmp ISR_Stub ;(6C) Reserved
|
||||
db 0
|
||||
ljmp ISR_Ep2piderror ;(70) EP2 ISO Pid Sequence Error
|
||||
db 0
|
||||
ljmp ISR_Ep4piderror ;(74) EP4 ISO Pid Sequence Error
|
||||
db 0
|
||||
ljmp ISR_Ep6piderror ;(78) EP6 ISO Pid Sequence Error
|
||||
db 0
|
||||
ljmp ISR_Ep8piderror ;(7C) EP8 ISO Pid Sequence Error
|
||||
db 0
|
||||
;INT4_Jump_Table
|
||||
ljmp ISR_Ep2pflag ;(80) EP2 Programmable Flag
|
||||
db 0
|
||||
ljmp ISR_Ep4pflag ;(84) EP4 Programmable Flag
|
||||
db 0
|
||||
ljmp ISR_Ep6pflag ;(88) EP6 Programmable Flag
|
||||
db 0
|
||||
ljmp ISR_Ep8pflag ;(8C) EP8 Programmable Flag
|
||||
db 0
|
||||
ljmp ISR_Ep2eflag ;(90) EP2 Empty Flag
|
||||
db 0
|
||||
ljmp ISR_Ep4eflag ;(94) EP4 Empty Flag
|
||||
db 0
|
||||
ljmp ISR_Ep6eflag ;(98) EP6 Empty Flag
|
||||
db 0
|
||||
ljmp ISR_Ep8eflag ;(9C) EP8 Empty Flag
|
||||
db 0
|
||||
ljmp ISR_Ep2fflag ;(A0) EP2 Full Flag
|
||||
db 0
|
||||
ljmp ISR_Ep4fflag ;(A4) EP4 Full Flag
|
||||
db 0
|
||||
ljmp ISR_Ep6fflag ;(A8) EP6 Full Flag
|
||||
db 0
|
||||
ljmp ISR_Ep8fflag ;(AC) EP8 Full Flag
|
||||
db 0
|
||||
ljmp ISR_GpifComplete ;(B0) GPIF Operation Complete
|
||||
db 0
|
||||
ljmp ISR_GpifWaveform ;(B4) GPIF Waveform
|
||||
db 0
|
||||
|
||||
end
|
||||
Binary file not shown.
@@ -0,0 +1,114 @@
|
||||
### uVision2 Project, (C) Keil Software
|
||||
### Do not modify !
|
||||
|
||||
Target (Target 1), 0x0000 // Tools: 'MCS-51'
|
||||
|
||||
Group (Source Group 1)
|
||||
|
||||
File 1,1,<.\drs_eval.c><drs_eval.c> 0x0
|
||||
|
||||
|
||||
Options 1,0,0 // Target 'Target 1'
|
||||
Device (EZ-USB FX2 (CY7C68XXX))
|
||||
Vendor (Cypress Semiconductor)
|
||||
Cpu (IRAM(0 - 0xFF) XRAM(0 - 0x3FF) CLOCK(48000000) MODDP2)
|
||||
FlashUt ()
|
||||
StupF ()
|
||||
FlashDR ()
|
||||
Rgf (REG52.H)
|
||||
Mem ()
|
||||
C ()
|
||||
A ()
|
||||
RL ()
|
||||
OH ()
|
||||
UseEnv=0
|
||||
EnvBin (C:\Program Files\Keil\C51\BIN\)
|
||||
EnvInc (C:\Cypress\USB\Target\Inc\;C:\Keil\C51\INC\)
|
||||
EnvLib (C:\Program Files\Keil\C51\LIB\)
|
||||
EnvReg ()
|
||||
OrgReg ()
|
||||
TgStat=0
|
||||
OutDir (.\)
|
||||
OutName (drs_eval)
|
||||
GenApp=1
|
||||
GenLib=0
|
||||
GenHex=1
|
||||
Debug=1
|
||||
Browse=1
|
||||
LstDir (.\)
|
||||
HexSel=0
|
||||
MG32K=0
|
||||
TGMORE=0
|
||||
RunUsr 0 1 <c:\cypress\usb\bin\hex2bix -i -f 0xC2 -v 0x04B4 -p 0x1175 -c 0x00 -o drs_eval.iic drs_eval.hex>
|
||||
RunUsr 1 0 <>
|
||||
BrunUsr 0 0 <>
|
||||
BrunUsr 1 0 <>
|
||||
SVCSID <>
|
||||
MODEL5=0
|
||||
RTOS5=0
|
||||
ROMSZ5=2
|
||||
DHOLD5=0
|
||||
XHOLD5=0
|
||||
T51FL=304
|
||||
CBANKS5=4
|
||||
XBANKS5=0
|
||||
RCB51 { 0,0,0,0,0,255,255,0,0 }
|
||||
RXB51 { 0,0,0,0,0,0,0,0,0 }
|
||||
OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
IRO51 { 0,0,0,0,0,0,0,0,0 }
|
||||
IRA51 { 0,0,0,0,0,0,1,0,0 }
|
||||
XRA51 { 0,0,0,0,0,0,4,0,0 }
|
||||
XRA512 { 0,0,0,0,0,0,0,0,0 }
|
||||
C51FL=21597456
|
||||
C51VA=0
|
||||
C51MSC ()
|
||||
C51DEF ()
|
||||
C51UDF ()
|
||||
INCC5 (c:\cypress\usb\target\inc)
|
||||
AX51FL=4
|
||||
AX51MSC ()
|
||||
AX51SET ()
|
||||
AX51RST ()
|
||||
INCA5 ()
|
||||
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
IncBld=1
|
||||
AlwaysBuild=0
|
||||
GenAsm=0
|
||||
AsmAsm=0
|
||||
PublicsOnly=0
|
||||
StopCode=3
|
||||
CustArgs ()
|
||||
LibMods ()
|
||||
BankNo=65535
|
||||
LX51FL=288
|
||||
LX51OVL ()
|
||||
LX51MSC ()
|
||||
LX51DWN ()
|
||||
LX51LFI ()
|
||||
LX51ASN ()
|
||||
LX51RES ()
|
||||
LX51CCL ()
|
||||
LX51UCL ()
|
||||
LX51CSC ()
|
||||
LX51UCS ()
|
||||
LX51COB (0x0080)
|
||||
LX51XDB (0x1000)
|
||||
LX51PDB ()
|
||||
LX51BIB ()
|
||||
LX51DAB ()
|
||||
LX51IDB ()
|
||||
LX51PRC ()
|
||||
LX51STK ()
|
||||
LX51COS ()
|
||||
LX51XDS ()
|
||||
LX51BIS ()
|
||||
LX51DAS ()
|
||||
LX51IDS ()
|
||||
OPTDL (S8051.DLL)()(DP51.DLL)(-p52)(S8051.DLL)()(TP51.DLL)(-p52)
|
||||
OPTDBG 49149,-1,()()()()()()()()()() (BIN\Mon51.dll)()()()
|
||||
FLASH1 { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
FLASH2 ()
|
||||
FLASH3 ("" ())
|
||||
EndOpt
|
||||
|
||||
@@ -0,0 +1,160 @@
|
||||
/********************************************************************\
|
||||
|
||||
Name: drs_eval.c
|
||||
Created by: Stefan Ritt
|
||||
|
||||
Contents: Cy7c68013A firmware for DRS4 evaluation board
|
||||
|
||||
$Id: drs_eval.c 18733 2011-12-14 07:57:23Z ritt $
|
||||
|
||||
\********************************************************************/
|
||||
|
||||
#define ALLOCATE_EXTERN
|
||||
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "intrins.h"
|
||||
|
||||
/* Syncronization delay:
|
||||
CPU running at 12 MHz
|
||||
FIFO running at 30 MHz
|
||||
-> 3 CPU cycles
|
||||
*/
|
||||
#define SYNCDELAY _nop_( ); _nop_( ); _nop_( )
|
||||
|
||||
void config_ep4_ep8()
|
||||
{
|
||||
/* default values for Reset to work */
|
||||
SYNCDELAY;
|
||||
EP4FIFOCFG = 0x03;
|
||||
|
||||
SYNCDELAY;
|
||||
EP8FIFOCFG = 0x03;
|
||||
|
||||
/* Endpoint 4 Configuration
|
||||
BULK OUT 512 Bytes
|
||||
*/
|
||||
SYNCDELAY;
|
||||
EP4CFG = 0xA0; // equals default
|
||||
|
||||
/* Endpoint 8 Configuration
|
||||
BULK IN 512 Bytes
|
||||
*/
|
||||
SYNCDELAY;
|
||||
EP8CFG = 0xE0; // equals default
|
||||
|
||||
/* FIFO Reset */
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x80; // NAKALL
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x84; // Reset EP4
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x88; // Reset EP8
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x00; // Normal operation
|
||||
|
||||
/* Flags definition:
|
||||
FLAGA is progammed level flag
|
||||
FLAGB is full flag
|
||||
FLAGC is empty flag
|
||||
*/
|
||||
PINFLAGSAB = 0x00;
|
||||
PINFLAGSCD = 0x00;
|
||||
|
||||
/* set all FIFO interface pins as active low */
|
||||
SYNCDELAY;
|
||||
FIFOPINPOLAR = 0x00;
|
||||
|
||||
/* EZ-USB automatically commits data in 512-byte chunks */
|
||||
SYNCDELAY;
|
||||
EP8AUTOINLENH = 0x02; // equals default
|
||||
SYNCDELAY;
|
||||
EP8AUTOINLENL = 0x00; // equals default
|
||||
|
||||
/* arm EP4 OUT buffer with SKIP=1 */
|
||||
SYNCDELAY;
|
||||
OUTPKTEND = 0x84; // first buffer
|
||||
SYNCDELAY;
|
||||
OUTPKTEND = 0x84; // second buffer
|
||||
|
||||
/* Endpoint 4 FIFO configuration
|
||||
0 dummy
|
||||
INFM1 = 0 "IN Full Minus One" off
|
||||
OEP1 = 0 "OUT Empty Plus One" off
|
||||
AUTOOUT = 1 Automatically commit OUT packets
|
||||
AUTOIN = 0 Automatically commit IN packets off
|
||||
ZEROLENIN = 0 Disable zero length packets
|
||||
0 dummy
|
||||
WORDWIDE = 1 Use word wide FIFO
|
||||
*/
|
||||
SYNCDELAY;
|
||||
EP4FIFOCFG = 0x11;
|
||||
|
||||
/* Endpoint 8 FIFO configuration
|
||||
0 dummy
|
||||
INFM1 = 0 "IN Full Minus One" off
|
||||
OEP1 = 0 "OUT Empty Plus One" off
|
||||
AUTOOUT = 0 Automatically commit OUT packets off
|
||||
AUTOIN = 1 Automatically commit IN packets
|
||||
ZEROLENIN = 1 Disable zero length packets
|
||||
0 dummy
|
||||
WORDWIDE = 1 Use word wide FIFO
|
||||
*/
|
||||
SYNCDELAY;
|
||||
EP8FIFOCFG = 0x0D;
|
||||
}
|
||||
|
||||
main()
|
||||
{
|
||||
/* Configure interface:
|
||||
IFCLKSDRC = 1 use internal FIFO clock
|
||||
3048MHZ = 0 select internal 30 MHz clock
|
||||
IFCLKOE = 1 enable IFCLK pin output
|
||||
IFCLKPOL = 0 do not invert clock
|
||||
ASYNC = 0 use synchronous mode
|
||||
GSTATE = 0 do not output GSTATE bits
|
||||
IFCFG1:0 = 11 select slave FIFO interface
|
||||
*/
|
||||
IFCONFIG = 0xA3;
|
||||
|
||||
/* Chip revision control
|
||||
DYN_OUT = 1 endpoints are not auto-armed on AUTOOUT transitions
|
||||
ENH_PKT = 1 enable CPU enhanced packet handling
|
||||
*/
|
||||
SYNCDELAY;
|
||||
REVCTL = 0x03;
|
||||
|
||||
config_ep4_ep8();
|
||||
|
||||
// set LED port to output
|
||||
OEA = 0x01;
|
||||
// turn on LED
|
||||
PA0 = 1;
|
||||
|
||||
// set the CPU clock to 48MHz
|
||||
// CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
|
||||
|
||||
// set RENUM = 0 to let EZ-USB handle all traffic
|
||||
USBCS &=!bmRENUM;
|
||||
|
||||
while (1) {
|
||||
SYNCDELAY;
|
||||
EP1OUTBC = 1; // arm EP1 to receive data
|
||||
while (EP1OUTCS & bmBIT1); // wait until data available
|
||||
PA0 = EP1OUTBUF[0];
|
||||
|
||||
/* echo back data */
|
||||
/*
|
||||
EP1INBUF[0] = EP1OUTBUF[0] + 1;
|
||||
|
||||
SYNCDELAY;
|
||||
EP1INBC = 1; // arm EP1 to send data
|
||||
while (EP1INCS & bmBIT1); // wait until host has read data
|
||||
*/
|
||||
|
||||
config_ep4_ep8();
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
:10008000000090E6197403F0000090E61BF00000F9
|
||||
:1000900090E61374A0F0000090E61574E0F0000004
|
||||
:1000A00090E6047480F000007484F000007488F01E
|
||||
:1000B0000000E4F090E602F0A3F0000090E609F002
|
||||
:1000C000000090E6267402F00000E4A3F000009027
|
||||
:1000D000E6497484F00000F0000090E6197411F015
|
||||
:0900E000000090E61B740DF022F3
|
||||
:1000E90090E60174A3F0000090E60B7403F012008F
|
||||
:1000F9008075B201D28090E680E0E4F0000090E6DD
|
||||
:100109008D7401F090E6A1E020E1F990E780E02408
|
||||
:0B011900FF928012008080E480FE2234
|
||||
:03000000020124D6
|
||||
:0C012400787FE4F6D8FD7581070200E941
|
||||
:00000001FF
|
||||
Binary file not shown.
@@ -0,0 +1,250 @@
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; File: dscr.a51
|
||||
;; Contents: This file contains descriptor data tables.
|
||||
;;
|
||||
;; $Archive: /USB/Examples/Fx2lp/bulkloop/dscr.a51 $
|
||||
;; $Date: 9/01/03 8:51p $
|
||||
;; $Revision: 3 $
|
||||
;;
|
||||
;;
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; Copyright 2003, Cypress Semiconductor Corporation
|
||||
;;-----------------------------------------------------------------------------;;-----------------------------------------------------------------------------
|
||||
|
||||
DSCR_DEVICE equ 1 ;; Descriptor type: Device
|
||||
DSCR_CONFIG equ 2 ;; Descriptor type: Configuration
|
||||
DSCR_STRING equ 3 ;; Descriptor type: String
|
||||
DSCR_INTRFC equ 4 ;; Descriptor type: Interface
|
||||
DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint
|
||||
DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier
|
||||
|
||||
DSCR_DEVICE_LEN equ 18
|
||||
DSCR_CONFIG_LEN equ 9
|
||||
DSCR_INTRFC_LEN equ 9
|
||||
DSCR_ENDPNT_LEN equ 7
|
||||
DSCR_DEVQUAL_LEN equ 10
|
||||
|
||||
ET_CONTROL equ 0 ;; Endpoint type: Control
|
||||
ET_ISO equ 1 ;; Endpoint type: Isochronous
|
||||
ET_BULK equ 2 ;; Endpoint type: Bulk
|
||||
ET_INT equ 3 ;; Endpoint type: Interrupt
|
||||
|
||||
public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr
|
||||
|
||||
DSCR SEGMENT CODE PAGE
|
||||
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; Global Variables
|
||||
;;-----------------------------------------------------------------------------
|
||||
rseg DSCR ;; locate the descriptor table in on-part memory.
|
||||
|
||||
DeviceDscr:
|
||||
db DSCR_DEVICE_LEN ;; Descriptor length
|
||||
db DSCR_DEVICE ;; Decriptor type
|
||||
dw 0002H ;; Specification Version (BCD)
|
||||
db 00H ;; Device class
|
||||
db 00H ;; Device sub-class
|
||||
db 01H ;; Device sub-sub-class
|
||||
db 64 ;; Maximum packet size
|
||||
dw 0B404H ;; Vendor ID
|
||||
dw 7511H ;; Product ID (Sample Device)
|
||||
dw 0100H ;; Product version ID
|
||||
db 1 ;; Manufacturer string index
|
||||
db 2 ;; Product string index
|
||||
db 3 ;; Serial number string index
|
||||
db 1 ;; Number of configurations
|
||||
|
||||
DeviceQualDscr:
|
||||
db DSCR_DEVQUAL_LEN ;; Descriptor length
|
||||
db DSCR_DEVQUAL ;; Decriptor type
|
||||
dw 0002H ;; Specification Version (BCD)
|
||||
db 00H ;; Device class
|
||||
db 00H ;; Device sub-class
|
||||
db 00H ;; Device sub-sub-class
|
||||
db 64 ;; Maximum packet size
|
||||
db 1 ;; Number of configurations
|
||||
db 0 ;; Reserved
|
||||
|
||||
HighSpeedConfigDscr:
|
||||
db DSCR_CONFIG_LEN ;; Descriptor length
|
||||
db DSCR_CONFIG ;; Descriptor type
|
||||
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
|
||||
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
|
||||
db 1 ;; Number of interfaces
|
||||
db 1 ;; Configuration number
|
||||
db 0 ;; Configuration string
|
||||
db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
|
||||
db 250 ;; Power requirement (div 2 ma)
|
||||
|
||||
;; Interface Descriptor
|
||||
db DSCR_INTRFC_LEN ;; Descriptor length
|
||||
db DSCR_INTRFC ;; Descriptor type
|
||||
db 0 ;; Zero-based index of this interface
|
||||
db 0 ;; Alternate setting
|
||||
db 4 ;; Number of end points
|
||||
db 0ffH ;; Interface class
|
||||
db 00H ;; Interface sub class
|
||||
db 00H ;; Interface sub sub class
|
||||
db 0 ;; Interface descriptor string index
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 01H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximun packet size (LSB)
|
||||
db 02H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 04H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximun packet size (LSB)
|
||||
db 02H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 81H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximun packet size (LSB)
|
||||
db 02H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 88H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximun packet size (LSB)
|
||||
db 02H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
HighSpeedConfigDscrEnd:
|
||||
|
||||
FullSpeedConfigDscr:
|
||||
db DSCR_CONFIG_LEN ;; Descriptor length
|
||||
db DSCR_CONFIG ;; Descriptor type
|
||||
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB)
|
||||
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB)
|
||||
db 1 ;; Number of interfaces
|
||||
db 1 ;; Configuration number
|
||||
db 0 ;; Configuration string
|
||||
db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
|
||||
db 250 ;; Power requirement (div 2 ma)
|
||||
|
||||
;; Interface Descriptor
|
||||
db DSCR_INTRFC_LEN ;; Descriptor length
|
||||
db DSCR_INTRFC ;; Descriptor type
|
||||
db 0 ;; Zero-based index of this interface
|
||||
db 0 ;; Alternate setting
|
||||
db 4 ;; Number of end points
|
||||
db 0ffH ;; Interface class
|
||||
db 00H ;; Interface sub class
|
||||
db 00H ;; Interface sub sub class
|
||||
db 0 ;; Interface descriptor string index
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 02H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximun packet size (LSB)
|
||||
db 00H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 04H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximun packet size (LSB)
|
||||
db 00H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 86H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximun packet size (LSB)
|
||||
db 00H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 88H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximun packet size (LSB)
|
||||
db 00H ;; Max packect size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
FullSpeedConfigDscrEnd:
|
||||
|
||||
StringDscr:
|
||||
|
||||
StringDscr0:
|
||||
db StringDscr0End-StringDscr0 ;; String descriptor length
|
||||
db DSCR_STRING
|
||||
db 09H,04H
|
||||
StringDscr0End:
|
||||
|
||||
StringDscr1:
|
||||
db StringDscr1End-StringDscr1 ;; String descriptor length
|
||||
db DSCR_STRING
|
||||
db 'S',00
|
||||
db '.',00
|
||||
db ' ',00
|
||||
db 'R',00
|
||||
db 'i',00
|
||||
db 't',00
|
||||
db 't',00
|
||||
db ' ',00
|
||||
db 'P',00
|
||||
db 'S',00
|
||||
db 'I',00
|
||||
StringDscr1End:
|
||||
|
||||
StringDscr2:
|
||||
db StringDscr2End-StringDscr2 ;; Descriptor length
|
||||
db DSCR_STRING
|
||||
db 'D',00
|
||||
db 'R',00
|
||||
db 'S',00
|
||||
db '4',00
|
||||
db ' ',00
|
||||
db 'E',00
|
||||
db 'v',00
|
||||
db 'a',00
|
||||
db 'l',00
|
||||
db 'u',00
|
||||
db 'a',00
|
||||
db 't',00
|
||||
db 'i',00
|
||||
db 'o',00
|
||||
db 'n',00
|
||||
db ' ',00
|
||||
db 'B',00
|
||||
db 'o',00
|
||||
db 'a',00
|
||||
db 'r',00
|
||||
db 'd',00
|
||||
StringDscr2End:
|
||||
|
||||
StringDscr3:
|
||||
db StringDscr3End-StringDscr3 ;; String descriptor length
|
||||
db DSCR_STRING
|
||||
db 'R',00
|
||||
db 'E',00
|
||||
db 'V',00
|
||||
db '1',00
|
||||
StringDscr3End:
|
||||
|
||||
UserDscr:
|
||||
dw 0000H
|
||||
end
|
||||
|
||||
@@ -0,0 +1,368 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: fw.c
|
||||
// Contents: Firmware frameworks task dispatcher and device request parser
|
||||
//
|
||||
// $Id: fw.c 15170 2010-04-30 06:27:56Z ritt $
|
||||
//
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright 2003, Cypress Semiconductor Corporation
|
||||
//-----------------------------------------------------------------------------
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "fx2sdly.h" // SYNCDELAY macro
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Constants
|
||||
//-----------------------------------------------------------------------------
|
||||
#define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48
|
||||
#define _IFREQ 48000 // IFCLK constant for Synchronization Delay
|
||||
#define _CFREQ 48000 // CLKOUT constant for Synchronization Delay
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Random Macros
|
||||
//-----------------------------------------------------------------------------
|
||||
#define min(a,b) (((a)<(b))?(a):(b))
|
||||
#define max(a,b) (((a)>(b))?(a):(b))
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global Variables
|
||||
//-----------------------------------------------------------------------------
|
||||
volatile BOOL GotSUD;
|
||||
BOOL Rwuen;
|
||||
BOOL Selfpwr;
|
||||
volatile BOOL Sleep; // Sleep mode enable flag
|
||||
|
||||
WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved
|
||||
WORD pDeviceQualDscr;
|
||||
WORD pHighSpeedConfigDscr;
|
||||
WORD pFullSpeedConfigDscr;
|
||||
WORD pConfigDscr;
|
||||
WORD pOtherConfigDscr;
|
||||
WORD pStringDscr;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Prototypes
|
||||
//-----------------------------------------------------------------------------
|
||||
void SetupCommand(void);
|
||||
void TD_Init(void);
|
||||
void TD_Poll(void);
|
||||
BOOL TD_Suspend(void);
|
||||
BOOL TD_Resume(void);
|
||||
|
||||
BOOL DR_GetDescriptor(void);
|
||||
BOOL DR_SetConfiguration(void);
|
||||
BOOL DR_GetConfiguration(void);
|
||||
BOOL DR_SetInterface(void);
|
||||
BOOL DR_GetInterface(void);
|
||||
BOOL DR_GetStatus(void);
|
||||
BOOL DR_ClearFeature(void);
|
||||
BOOL DR_SetFeature(void);
|
||||
BOOL DR_VendorCmnd(void);
|
||||
|
||||
// this table is used by the epcs macro
|
||||
const char code EPCS_Offset_Lookup_Table[] =
|
||||
{
|
||||
0, // EP1OUT
|
||||
1, // EP1IN
|
||||
2, // EP2OUT
|
||||
2, // EP2IN
|
||||
3, // EP4OUT
|
||||
3, // EP4IN
|
||||
4, // EP6OUT
|
||||
4, // EP6IN
|
||||
5, // EP8OUT
|
||||
5, // EP8IN
|
||||
};
|
||||
|
||||
// macro for generating the address of an endpoint's control and status register (EPnCS)
|
||||
#define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1)
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Code
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// Task dispatcher
|
||||
void main(void)
|
||||
{
|
||||
DWORD i;
|
||||
WORD offset;
|
||||
DWORD DevDescrLen;
|
||||
DWORD j=0;
|
||||
WORD IntDescrAddr;
|
||||
WORD ExtDescrAddr;
|
||||
|
||||
// Initialize Global States
|
||||
Sleep = FALSE; // Disable sleep mode
|
||||
Rwuen = FALSE; // Disable remote wakeup
|
||||
Selfpwr = FALSE; // Disable self powered
|
||||
GotSUD = FALSE; // Clear "Got setup data" flag
|
||||
|
||||
// Initialize user device
|
||||
TD_Init();
|
||||
|
||||
// The following section of code is used to relocate the descriptor table.
|
||||
// The frameworks uses SUDPTRH and SUDPTRL to automate the SETUP requests
|
||||
// for descriptors. These registers only work with memory locations
|
||||
// in the EZ-USB internal RAM. Therefore, if the descriptors are located
|
||||
// in external RAM, they must be copied to in internal RAM.
|
||||
// The descriptor table is relocated by the frameworks ONLY if it is found
|
||||
// to be located in external memory.
|
||||
pDeviceDscr = (WORD)&DeviceDscr;
|
||||
pDeviceQualDscr = (WORD)&DeviceQualDscr;
|
||||
pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr;
|
||||
pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr;
|
||||
pStringDscr = (WORD)&StringDscr;
|
||||
|
||||
// Is the descriptor table in external RAM (> 16Kbytes)? If yes,
|
||||
// then relocate.
|
||||
// Note that this code only checks if the descriptors START in
|
||||
// external RAM. It will not work if the descriptor table spans
|
||||
// internal and external RAM.
|
||||
if ((WORD)&DeviceDscr & 0xC000)
|
||||
{
|
||||
// first, relocate the descriptors
|
||||
IntDescrAddr = INTERNAL_DSCR_ADDR;
|
||||
ExtDescrAddr = (WORD)&DeviceDscr;
|
||||
DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2;
|
||||
for (i = 0; i < DevDescrLen; i++)
|
||||
*((BYTE xdata *)IntDescrAddr+i) = *((BYTE xdata *)ExtDescrAddr+i);
|
||||
|
||||
// update all of the descriptor pointers
|
||||
pDeviceDscr = IntDescrAddr;
|
||||
offset = (WORD)&DeviceDscr - INTERNAL_DSCR_ADDR;
|
||||
pDeviceQualDscr -= offset;
|
||||
pConfigDscr -= offset;
|
||||
pOtherConfigDscr -= offset;
|
||||
pHighSpeedConfigDscr -= offset;
|
||||
pFullSpeedConfigDscr -= offset;
|
||||
pStringDscr -= offset;
|
||||
}
|
||||
|
||||
EZUSB_IRQ_ENABLE(); // Enable USB interrupt (INT2)
|
||||
EZUSB_ENABLE_RSMIRQ(); // Wake-up interrupt
|
||||
|
||||
INTSETUP |= (bmAV2EN | bmAV4EN); // Enable INT 2 & 4 autovectoring
|
||||
|
||||
USBIE |= bmSUDAV | bmSUTOK | bmSUSP | bmURES | bmHSGRANT; // Enable selected interrupts
|
||||
EA = 1; // Enable 8051 interrupts
|
||||
|
||||
#ifndef NO_RENUM
|
||||
// Renumerate if necessary. Do this by checking the renum bit. If it
|
||||
// is already set, there is no need to renumerate. The renum bit will
|
||||
// already be set if this firmware was loaded from an eeprom.
|
||||
if(!(USBCS & bmRENUM))
|
||||
{
|
||||
EZUSB_Discon(TRUE); // renumerate
|
||||
}
|
||||
#endif
|
||||
|
||||
// unconditionally re-connect. If we loaded from eeprom we are
|
||||
// disconnected and need to connect. If we just renumerated this
|
||||
// is not necessary but doesn't hurt anything
|
||||
USBCS &=~bmDISCON;
|
||||
|
||||
CKCON = (CKCON&(~bmSTRETCH)) | FW_STRETCH_VALUE; // Set stretch
|
||||
|
||||
// clear the Sleep flag.
|
||||
Sleep = FALSE;
|
||||
|
||||
// Task Dispatcher
|
||||
while(TRUE) // Main Loop
|
||||
{
|
||||
// Poll User Device
|
||||
TD_Poll();
|
||||
|
||||
// Check for pending SETUP
|
||||
if(GotSUD)
|
||||
{
|
||||
SetupCommand(); // Implement setup command
|
||||
GotSUD = FALSE; // Clear SETUP flag
|
||||
}
|
||||
|
||||
// check for and handle suspend.
|
||||
// NOTE: Idle mode stops the processor clock. There are only two
|
||||
// ways out of idle mode, the WAKEUP pin, and detection of the USB
|
||||
// resume state on the USB bus. The timers will stop and the
|
||||
// processor will not wake up on any other interrupts.
|
||||
if (Sleep)
|
||||
{
|
||||
if(TD_Suspend())
|
||||
{
|
||||
Sleep = FALSE; // Clear the "go to sleep" flag. Do it here to prevent any race condition between wakeup and the next sleep.
|
||||
do
|
||||
{
|
||||
EZUSB_Susp(); // Place processor in idle mode.
|
||||
}
|
||||
while(!Rwuen && EZUSB_EXTWAKEUP());
|
||||
// above. Must continue to go back into suspend if the host has disabled remote wakeup
|
||||
// *and* the wakeup was caused by the external wakeup pin.
|
||||
|
||||
// 8051 activity will resume here due to USB bus or Wakeup# pin activity.
|
||||
EZUSB_Resume(); // If source is the Wakeup# pin, signal the host to Resume.
|
||||
TD_Resume();
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
BOOL HighSpeedCapable()
|
||||
{
|
||||
// this function determines if the chip is high-speed capable.
|
||||
// FX2 and FX2LP are high-speed capable. FX1 is not - it does
|
||||
// not have a high-speed transceiver.
|
||||
|
||||
if (GPCR2 & bmFULLSPEEDONLY)
|
||||
return FALSE;
|
||||
else
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
// Device request parser
|
||||
void SetupCommand(void)
|
||||
{
|
||||
void *dscr_ptr;
|
||||
|
||||
switch(SETUPDAT[1])
|
||||
{
|
||||
case SC_GET_DESCRIPTOR: // *** Get Descriptor
|
||||
if(DR_GetDescriptor())
|
||||
switch(SETUPDAT[3])
|
||||
{
|
||||
case GD_DEVICE: // Device
|
||||
SUDPTRH = MSB(pDeviceDscr);
|
||||
SUDPTRL = LSB(pDeviceDscr);
|
||||
break;
|
||||
case GD_DEVICE_QUALIFIER: // Device Qualifier
|
||||
// only retuen a device qualifier if this is a high speed
|
||||
// capable chip.
|
||||
if (HighSpeedCapable())
|
||||
{
|
||||
SUDPTRH = MSB(pDeviceQualDscr);
|
||||
SUDPTRL = LSB(pDeviceQualDscr);
|
||||
}
|
||||
else
|
||||
{
|
||||
EZUSB_STALL_EP0();
|
||||
}
|
||||
break;
|
||||
case GD_CONFIGURATION: // Configuration
|
||||
SUDPTRH = MSB(pConfigDscr);
|
||||
SUDPTRL = LSB(pConfigDscr);
|
||||
break;
|
||||
case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration
|
||||
SUDPTRH = MSB(pOtherConfigDscr);
|
||||
SUDPTRL = LSB(pOtherConfigDscr);
|
||||
break;
|
||||
case GD_STRING: // String
|
||||
if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2]))
|
||||
{
|
||||
SUDPTRH = MSB(dscr_ptr);
|
||||
SUDPTRL = LSB(dscr_ptr);
|
||||
}
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
default: // Invalid request
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
break;
|
||||
case SC_GET_INTERFACE: // *** Get Interface
|
||||
DR_GetInterface();
|
||||
break;
|
||||
case SC_SET_INTERFACE: // *** Set Interface
|
||||
DR_SetInterface();
|
||||
break;
|
||||
case SC_SET_CONFIGURATION: // *** Set Configuration
|
||||
DR_SetConfiguration();
|
||||
break;
|
||||
case SC_GET_CONFIGURATION: // *** Get Configuration
|
||||
DR_GetConfiguration();
|
||||
break;
|
||||
case SC_GET_STATUS: // *** Get Status
|
||||
if(DR_GetStatus())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case GS_DEVICE: // Device
|
||||
EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
case GS_INTERFACE: // Interface
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
case GS_ENDPOINT: // End Point
|
||||
EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
default: // Invalid Command
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
break;
|
||||
case SC_CLEAR_FEATURE: // *** Clear Feature
|
||||
if(DR_ClearFeature())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case FT_DEVICE: // Device
|
||||
if(SETUPDAT[2] == 1)
|
||||
Rwuen = FALSE; // Disable Remote Wakeup
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
case FT_ENDPOINT: // End Point
|
||||
if(SETUPDAT[2] == 0)
|
||||
{
|
||||
*(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL;
|
||||
EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
|
||||
}
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case SC_SET_FEATURE: // *** Set Feature
|
||||
if(DR_SetFeature())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case FT_DEVICE: // Device
|
||||
if(SETUPDAT[2] == 1)
|
||||
Rwuen = TRUE; // Enable Remote Wakeup
|
||||
else if(SETUPDAT[2] == 2)
|
||||
// Set Feature Test Mode. The core handles this request. However, it is
|
||||
// necessary for the firmware to complete the handshake phase of the
|
||||
// control transfer before the chip will enter test mode. It is also
|
||||
// necessary for FX2 to be physically disconnected (D+ and D-)
|
||||
// from the host before it will enter test mode.
|
||||
break;
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
case FT_ENDPOINT: // End Point
|
||||
*(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL;
|
||||
break;
|
||||
default:
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
break;
|
||||
default: // *** Invalid Command
|
||||
if(DR_VendorCmnd())
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
|
||||
// Acknowledge handshake phase of device request
|
||||
EP0CS |= bmHSNAK;
|
||||
}
|
||||
|
||||
// Wake-up interrupt handler
|
||||
void resume_isr(void) interrupt WKUP_VECT
|
||||
{
|
||||
EZUSB_CLEAR_RSMIRQ();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,686 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: FX2regs.h
|
||||
// Contents: EZ-USB FX2/FX2LP/FX1 register declarations and bit mask definitions.
|
||||
//
|
||||
// $Archive: /USB/Target/Inc/fx2regs.h $
|
||||
// $Date: 4/13/05 4:29p $
|
||||
// $Revision: 42 $
|
||||
// $Id: fx2regs.h 11698 2008-06-12 15:28:35Z ritt@PSI.CH $
|
||||
//
|
||||
// Copyright (c) 2005 Cypress Semiconductor, All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#ifndef FX2REGS_H /* Header Sentry */
|
||||
#define FX2REGS_H
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// FX2/FX2LP/FX1 Related Register Assignments
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// The Ez-USB FX2/FX2LP/FX1 registers are defined here. We use fx2regs.h for register
|
||||
// address allocation by using "#define ALLOCATE_EXTERN".
|
||||
// When using "#define ALLOCATE_EXTERN", you get (for instance):
|
||||
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
|
||||
// Such lines are created from FX2.h by using the preprocessor.
|
||||
// Incidently, these lines will not generate any space in the resulting hex
|
||||
// file; they just bind the symbols to the addresses for compilation.
|
||||
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
|
||||
// i.e. fw.c or a stand-alone C source file.
|
||||
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
|
||||
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
|
||||
// This uses the concatenation operator "##" to insert a comment "//"
|
||||
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
|
||||
|
||||
#ifdef ALLOCATE_EXTERN
|
||||
#define EXTERN
|
||||
#define _AT_ _at_
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#define _AT_ ;/ ## /
|
||||
#endif
|
||||
|
||||
EXTERN xdata volatile BYTE GPIF_WAVE_DATA _AT_ 0xE400;
|
||||
EXTERN xdata volatile BYTE RES_WAVEDATA_END _AT_ 0xE480;
|
||||
|
||||
// General Configuration
|
||||
|
||||
EXTERN xdata volatile BYTE CPUCS _AT_ 0xE600; // Control & Status
|
||||
EXTERN xdata volatile BYTE IFCONFIG _AT_ 0xE601; // Interface Configuration
|
||||
EXTERN xdata volatile BYTE PINFLAGSAB _AT_ 0xE602; // FIFO FLAGA and FLAGB Assignments
|
||||
EXTERN xdata volatile BYTE PINFLAGSCD _AT_ 0xE603; // FIFO FLAGC and FLAGD Assignments
|
||||
EXTERN xdata volatile BYTE FIFORESET _AT_ 0xE604; // Restore FIFOS to default state
|
||||
EXTERN xdata volatile BYTE BREAKPT _AT_ 0xE605; // Breakpoint
|
||||
EXTERN xdata volatile BYTE BPADDRH _AT_ 0xE606; // Breakpoint Address H
|
||||
EXTERN xdata volatile BYTE BPADDRL _AT_ 0xE607; // Breakpoint Address L
|
||||
EXTERN xdata volatile BYTE UART230 _AT_ 0xE608; // 230 Kbaud clock for T0,T1,T2
|
||||
EXTERN xdata volatile BYTE FIFOPINPOLAR _AT_ 0xE609; // FIFO polarities
|
||||
EXTERN xdata volatile BYTE REVID _AT_ 0xE60A; // Chip Revision
|
||||
EXTERN xdata volatile BYTE REVCTL _AT_ 0xE60B; // Chip Revision Control
|
||||
|
||||
// Endpoint Configuration
|
||||
|
||||
EXTERN xdata volatile BYTE EP1OUTCFG _AT_ 0xE610; // Endpoint 1-OUT Configuration
|
||||
EXTERN xdata volatile BYTE EP1INCFG _AT_ 0xE611; // Endpoint 1-IN Configuration
|
||||
EXTERN xdata volatile BYTE EP2CFG _AT_ 0xE612; // Endpoint 2 Configuration
|
||||
EXTERN xdata volatile BYTE EP4CFG _AT_ 0xE613; // Endpoint 4 Configuration
|
||||
EXTERN xdata volatile BYTE EP6CFG _AT_ 0xE614; // Endpoint 6 Configuration
|
||||
EXTERN xdata volatile BYTE EP8CFG _AT_ 0xE615; // Endpoint 8 Configuration
|
||||
EXTERN xdata volatile BYTE EP2FIFOCFG _AT_ 0xE618; // Endpoint 2 FIFO configuration
|
||||
EXTERN xdata volatile BYTE EP4FIFOCFG _AT_ 0xE619; // Endpoint 4 FIFO configuration
|
||||
EXTERN xdata volatile BYTE EP6FIFOCFG _AT_ 0xE61A; // Endpoint 6 FIFO configuration
|
||||
EXTERN xdata volatile BYTE EP8FIFOCFG _AT_ 0xE61B; // Endpoint 8 FIFO configuration
|
||||
EXTERN xdata volatile BYTE EP2AUTOINLENH _AT_ 0xE620; // Endpoint 2 Packet Length H (IN only)
|
||||
EXTERN xdata volatile BYTE EP2AUTOINLENL _AT_ 0xE621; // Endpoint 2 Packet Length L (IN only)
|
||||
EXTERN xdata volatile BYTE EP4AUTOINLENH _AT_ 0xE622; // Endpoint 4 Packet Length H (IN only)
|
||||
EXTERN xdata volatile BYTE EP4AUTOINLENL _AT_ 0xE623; // Endpoint 4 Packet Length L (IN only)
|
||||
EXTERN xdata volatile BYTE EP6AUTOINLENH _AT_ 0xE624; // Endpoint 6 Packet Length H (IN only)
|
||||
EXTERN xdata volatile BYTE EP6AUTOINLENL _AT_ 0xE625; // Endpoint 6 Packet Length L (IN only)
|
||||
EXTERN xdata volatile BYTE EP8AUTOINLENH _AT_ 0xE626; // Endpoint 8 Packet Length H (IN only)
|
||||
EXTERN xdata volatile BYTE EP8AUTOINLENL _AT_ 0xE627; // Endpoint 8 Packet Length L (IN only)
|
||||
EXTERN xdata volatile BYTE EP2FIFOPFH _AT_ 0xE630; // EP2 Programmable Flag trigger H
|
||||
EXTERN xdata volatile BYTE EP2FIFOPFL _AT_ 0xE631; // EP2 Programmable Flag trigger L
|
||||
EXTERN xdata volatile BYTE EP4FIFOPFH _AT_ 0xE632; // EP4 Programmable Flag trigger H
|
||||
EXTERN xdata volatile BYTE EP4FIFOPFL _AT_ 0xE633; // EP4 Programmable Flag trigger L
|
||||
EXTERN xdata volatile BYTE EP6FIFOPFH _AT_ 0xE634; // EP6 Programmable Flag trigger H
|
||||
EXTERN xdata volatile BYTE EP6FIFOPFL _AT_ 0xE635; // EP6 Programmable Flag trigger L
|
||||
EXTERN xdata volatile BYTE EP8FIFOPFH _AT_ 0xE636; // EP8 Programmable Flag trigger H
|
||||
EXTERN xdata volatile BYTE EP8FIFOPFL _AT_ 0xE637; // EP8 Programmable Flag trigger L
|
||||
EXTERN xdata volatile BYTE EP2ISOINPKTS _AT_ 0xE640; // EP2 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata volatile BYTE EP4ISOINPKTS _AT_ 0xE641; // EP4 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata volatile BYTE EP6ISOINPKTS _AT_ 0xE642; // EP6 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata volatile BYTE EP8ISOINPKTS _AT_ 0xE643; // EP8 (if ISO) IN Packets per frame (1-3)
|
||||
EXTERN xdata volatile BYTE INPKTEND _AT_ 0xE648; // Force IN Packet End
|
||||
EXTERN xdata volatile BYTE OUTPKTEND _AT_ 0xE649; // Force OUT Packet End
|
||||
|
||||
// Interrupts
|
||||
|
||||
EXTERN xdata volatile BYTE EP2FIFOIE _AT_ 0xE650; // Endpoint 2 Flag Interrupt Enable
|
||||
EXTERN xdata volatile BYTE EP2FIFOIRQ _AT_ 0xE651; // Endpoint 2 Flag Interrupt Request
|
||||
EXTERN xdata volatile BYTE EP4FIFOIE _AT_ 0xE652; // Endpoint 4 Flag Interrupt Enable
|
||||
EXTERN xdata volatile BYTE EP4FIFOIRQ _AT_ 0xE653; // Endpoint 4 Flag Interrupt Request
|
||||
EXTERN xdata volatile BYTE EP6FIFOIE _AT_ 0xE654; // Endpoint 6 Flag Interrupt Enable
|
||||
EXTERN xdata volatile BYTE EP6FIFOIRQ _AT_ 0xE655; // Endpoint 6 Flag Interrupt Request
|
||||
EXTERN xdata volatile BYTE EP8FIFOIE _AT_ 0xE656; // Endpoint 8 Flag Interrupt Enable
|
||||
EXTERN xdata volatile BYTE EP8FIFOIRQ _AT_ 0xE657; // Endpoint 8 Flag Interrupt Request
|
||||
EXTERN xdata volatile BYTE IBNIE _AT_ 0xE658; // IN-BULK-NAK Interrupt Enable
|
||||
EXTERN xdata volatile BYTE IBNIRQ _AT_ 0xE659; // IN-BULK-NAK interrupt Request
|
||||
EXTERN xdata volatile BYTE NAKIE _AT_ 0xE65A; // Endpoint Ping NAK interrupt Enable
|
||||
EXTERN xdata volatile BYTE NAKIRQ _AT_ 0xE65B; // Endpoint Ping NAK interrupt Request
|
||||
EXTERN xdata volatile BYTE USBIE _AT_ 0xE65C; // USB Int Enables
|
||||
EXTERN xdata volatile BYTE USBIRQ _AT_ 0xE65D; // USB Interrupt Requests
|
||||
EXTERN xdata volatile BYTE EPIE _AT_ 0xE65E; // Endpoint Interrupt Enables
|
||||
EXTERN xdata volatile BYTE EPIRQ _AT_ 0xE65F; // Endpoint Interrupt Requests
|
||||
EXTERN xdata volatile BYTE GPIFIE _AT_ 0xE660; // GPIF Interrupt Enable
|
||||
EXTERN xdata volatile BYTE GPIFIRQ _AT_ 0xE661; // GPIF Interrupt Request
|
||||
EXTERN xdata volatile BYTE USBERRIE _AT_ 0xE662; // USB Error Interrupt Enables
|
||||
EXTERN xdata volatile BYTE USBERRIRQ _AT_ 0xE663; // USB Error Interrupt Requests
|
||||
EXTERN xdata volatile BYTE ERRCNTLIM _AT_ 0xE664; // USB Error counter and limit
|
||||
EXTERN xdata volatile BYTE CLRERRCNT _AT_ 0xE665; // Clear Error Counter EC[3..0]
|
||||
EXTERN xdata volatile BYTE INT2IVEC _AT_ 0xE666; // Interupt 2 (USB) Autovector
|
||||
EXTERN xdata volatile BYTE INT4IVEC _AT_ 0xE667; // Interupt 4 (FIFOS & GPIF) Autovector
|
||||
EXTERN xdata volatile BYTE INTSETUP _AT_ 0xE668; // Interrupt 2&4 Setup
|
||||
|
||||
// Input/Output
|
||||
|
||||
EXTERN xdata volatile BYTE PORTACFG _AT_ 0xE670; // I/O PORTA Alternate Configuration
|
||||
EXTERN xdata volatile BYTE PORTCCFG _AT_ 0xE671; // I/O PORTC Alternate Configuration
|
||||
EXTERN xdata volatile BYTE PORTECFG _AT_ 0xE672; // I/O PORTE Alternate Configuration
|
||||
EXTERN xdata volatile BYTE I2CS _AT_ 0xE678; // Control & Status
|
||||
EXTERN xdata volatile BYTE I2DAT _AT_ 0xE679; // Data
|
||||
EXTERN xdata volatile BYTE I2CTL _AT_ 0xE67A; // I2C Control
|
||||
EXTERN xdata volatile BYTE XAUTODAT1 _AT_ 0xE67B; // Autoptr1 MOVX access
|
||||
EXTERN xdata volatile BYTE XAUTODAT2 _AT_ 0xE67C; // Autoptr2 MOVX access
|
||||
|
||||
#define EXTAUTODAT1 XAUTODAT1
|
||||
#define EXTAUTODAT2 XAUTODAT2
|
||||
|
||||
// USB Control
|
||||
|
||||
EXTERN xdata volatile BYTE USBCS _AT_ 0xE680; // USB Control & Status
|
||||
EXTERN xdata volatile BYTE SUSPEND _AT_ 0xE681; // Put chip into suspend
|
||||
EXTERN xdata volatile BYTE WAKEUPCS _AT_ 0xE682; // Wakeup source and polarity
|
||||
EXTERN xdata volatile BYTE TOGCTL _AT_ 0xE683; // Toggle Control
|
||||
EXTERN xdata volatile BYTE USBFRAMEH _AT_ 0xE684; // USB Frame count H
|
||||
EXTERN xdata volatile BYTE USBFRAMEL _AT_ 0xE685; // USB Frame count L
|
||||
EXTERN xdata volatile BYTE MICROFRAME _AT_ 0xE686; // Microframe count, 0-7
|
||||
EXTERN xdata volatile BYTE FNADDR _AT_ 0xE687; // USB Function address
|
||||
|
||||
// Endpoints
|
||||
|
||||
EXTERN xdata volatile BYTE EP0BCH _AT_ 0xE68A; // Endpoint 0 Byte Count H
|
||||
EXTERN xdata volatile BYTE EP0BCL _AT_ 0xE68B; // Endpoint 0 Byte Count L
|
||||
EXTERN xdata volatile BYTE EP1OUTBC _AT_ 0xE68D; // Endpoint 1 OUT Byte Count
|
||||
EXTERN xdata volatile BYTE EP1INBC _AT_ 0xE68F; // Endpoint 1 IN Byte Count
|
||||
EXTERN xdata volatile BYTE EP2BCH _AT_ 0xE690; // Endpoint 2 Byte Count H
|
||||
EXTERN xdata volatile BYTE EP2BCL _AT_ 0xE691; // Endpoint 2 Byte Count L
|
||||
EXTERN xdata volatile BYTE EP4BCH _AT_ 0xE694; // Endpoint 4 Byte Count H
|
||||
EXTERN xdata volatile BYTE EP4BCL _AT_ 0xE695; // Endpoint 4 Byte Count L
|
||||
EXTERN xdata volatile BYTE EP6BCH _AT_ 0xE698; // Endpoint 6 Byte Count H
|
||||
EXTERN xdata volatile BYTE EP6BCL _AT_ 0xE699; // Endpoint 6 Byte Count L
|
||||
EXTERN xdata volatile BYTE EP8BCH _AT_ 0xE69C; // Endpoint 8 Byte Count H
|
||||
EXTERN xdata volatile BYTE EP8BCL _AT_ 0xE69D; // Endpoint 8 Byte Count L
|
||||
EXTERN xdata volatile BYTE EP0CS _AT_ 0xE6A0; // Endpoint Control and Status
|
||||
EXTERN xdata volatile BYTE EP1OUTCS _AT_ 0xE6A1; // Endpoint 1 OUT Control and Status
|
||||
EXTERN xdata volatile BYTE EP1INCS _AT_ 0xE6A2; // Endpoint 1 IN Control and Status
|
||||
EXTERN xdata volatile BYTE EP2CS _AT_ 0xE6A3; // Endpoint 2 Control and Status
|
||||
EXTERN xdata volatile BYTE EP4CS _AT_ 0xE6A4; // Endpoint 4 Control and Status
|
||||
EXTERN xdata volatile BYTE EP6CS _AT_ 0xE6A5; // Endpoint 6 Control and Status
|
||||
EXTERN xdata volatile BYTE EP8CS _AT_ 0xE6A6; // Endpoint 8 Control and Status
|
||||
EXTERN xdata volatile BYTE EP2FIFOFLGS _AT_ 0xE6A7; // Endpoint 2 Flags
|
||||
EXTERN xdata volatile BYTE EP4FIFOFLGS _AT_ 0xE6A8; // Endpoint 4 Flags
|
||||
EXTERN xdata volatile BYTE EP6FIFOFLGS _AT_ 0xE6A9; // Endpoint 6 Flags
|
||||
EXTERN xdata volatile BYTE EP8FIFOFLGS _AT_ 0xE6AA; // Endpoint 8 Flags
|
||||
EXTERN xdata volatile BYTE EP2FIFOBCH _AT_ 0xE6AB; // EP2 FIFO total byte count H
|
||||
EXTERN xdata volatile BYTE EP2FIFOBCL _AT_ 0xE6AC; // EP2 FIFO total byte count L
|
||||
EXTERN xdata volatile BYTE EP4FIFOBCH _AT_ 0xE6AD; // EP4 FIFO total byte count H
|
||||
EXTERN xdata volatile BYTE EP4FIFOBCL _AT_ 0xE6AE; // EP4 FIFO total byte count L
|
||||
EXTERN xdata volatile BYTE EP6FIFOBCH _AT_ 0xE6AF; // EP6 FIFO total byte count H
|
||||
EXTERN xdata volatile BYTE EP6FIFOBCL _AT_ 0xE6B0; // EP6 FIFO total byte count L
|
||||
EXTERN xdata volatile BYTE EP8FIFOBCH _AT_ 0xE6B1; // EP8 FIFO total byte count H
|
||||
EXTERN xdata volatile BYTE EP8FIFOBCL _AT_ 0xE6B2; // EP8 FIFO total byte count L
|
||||
EXTERN xdata volatile BYTE SUDPTRH _AT_ 0xE6B3; // Setup Data Pointer high address byte
|
||||
EXTERN xdata volatile BYTE SUDPTRL _AT_ 0xE6B4; // Setup Data Pointer low address byte
|
||||
EXTERN xdata volatile BYTE SUDPTRCTL _AT_ 0xE6B5; // Setup Data Pointer Auto Mode
|
||||
EXTERN xdata volatile BYTE SETUPDAT[8] _AT_ 0xE6B8; // 8 bytes of SETUP data
|
||||
|
||||
// GPIF
|
||||
|
||||
EXTERN xdata volatile BYTE GPIFWFSELECT _AT_ 0xE6C0; // Waveform Selector
|
||||
EXTERN xdata volatile BYTE GPIFIDLECS _AT_ 0xE6C1; // GPIF Done, GPIF IDLE drive mode
|
||||
EXTERN xdata volatile BYTE GPIFIDLECTL _AT_ 0xE6C2; // Inactive Bus, CTL states
|
||||
EXTERN xdata volatile BYTE GPIFCTLCFG _AT_ 0xE6C3; // CTL OUT pin drive
|
||||
EXTERN xdata volatile BYTE GPIFADRH _AT_ 0xE6C4; // GPIF Address H
|
||||
EXTERN xdata volatile BYTE GPIFADRL _AT_ 0xE6C5; // GPIF Address L
|
||||
|
||||
EXTERN xdata volatile BYTE GPIFTCB3 _AT_ 0xE6CE; // GPIF Transaction Count Byte 3
|
||||
EXTERN xdata volatile BYTE GPIFTCB2 _AT_ 0xE6CF; // GPIF Transaction Count Byte 2
|
||||
EXTERN xdata volatile BYTE GPIFTCB1 _AT_ 0xE6D0; // GPIF Transaction Count Byte 1
|
||||
EXTERN xdata volatile BYTE GPIFTCB0 _AT_ 0xE6D1; // GPIF Transaction Count Byte 0
|
||||
|
||||
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP2GPIFTCL GPIFTCB0 //
|
||||
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP4GPIFTCL GPIFTCB0 //
|
||||
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP6GPIFTCL GPIFTCB0 //
|
||||
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP8GPIFTCL GPIFTCB0 //
|
||||
|
||||
EXTERN xdata volatile BYTE EP2GPIFFLGSEL _AT_ 0xE6D2; // EP2 GPIF Flag select
|
||||
EXTERN xdata volatile BYTE EP2GPIFPFSTOP _AT_ 0xE6D3; // Stop GPIF EP2 transaction on prog. flag
|
||||
EXTERN xdata volatile BYTE EP2GPIFTRIG _AT_ 0xE6D4; // EP2 FIFO Trigger
|
||||
EXTERN xdata volatile BYTE EP4GPIFFLGSEL _AT_ 0xE6DA; // EP4 GPIF Flag select
|
||||
EXTERN xdata volatile BYTE EP4GPIFPFSTOP _AT_ 0xE6DB; // Stop GPIF EP4 transaction on prog. flag
|
||||
EXTERN xdata volatile BYTE EP4GPIFTRIG _AT_ 0xE6DC; // EP4 FIFO Trigger
|
||||
EXTERN xdata volatile BYTE EP6GPIFFLGSEL _AT_ 0xE6E2; // EP6 GPIF Flag select
|
||||
EXTERN xdata volatile BYTE EP6GPIFPFSTOP _AT_ 0xE6E3; // Stop GPIF EP6 transaction on prog. flag
|
||||
EXTERN xdata volatile BYTE EP6GPIFTRIG _AT_ 0xE6E4; // EP6 FIFO Trigger
|
||||
EXTERN xdata volatile BYTE EP8GPIFFLGSEL _AT_ 0xE6EA; // EP8 GPIF Flag select
|
||||
EXTERN xdata volatile BYTE EP8GPIFPFSTOP _AT_ 0xE6EB; // Stop GPIF EP8 transaction on prog. flag
|
||||
EXTERN xdata volatile BYTE EP8GPIFTRIG _AT_ 0xE6EC; // EP8 FIFO Trigger
|
||||
EXTERN xdata volatile BYTE XGPIFSGLDATH _AT_ 0xE6F0; // GPIF Data H (16-bit mode only)
|
||||
EXTERN xdata volatile BYTE XGPIFSGLDATLX _AT_ 0xE6F1; // Read/Write GPIF Data L & trigger transac
|
||||
EXTERN xdata volatile BYTE XGPIFSGLDATLNOX _AT_ 0xE6F2; // Read GPIF Data L, no transac trigger
|
||||
EXTERN xdata volatile BYTE GPIFREADYCFG _AT_ 0xE6F3; // Internal RDY,Sync/Async, RDY5CFG
|
||||
EXTERN xdata volatile BYTE GPIFREADYSTAT _AT_ 0xE6F4; // RDY pin states
|
||||
EXTERN xdata volatile BYTE GPIFABORT _AT_ 0xE6F5; // Abort GPIF cycles
|
||||
|
||||
// UDMA
|
||||
|
||||
EXTERN xdata volatile BYTE FLOWSTATE _AT_ 0xE6C6; //Defines GPIF flow state
|
||||
EXTERN xdata volatile BYTE FLOWLOGIC _AT_ 0xE6C7; //Defines flow/hold decision criteria
|
||||
EXTERN xdata volatile BYTE FLOWEQ0CTL _AT_ 0xE6C8; //CTL states during active flow state
|
||||
EXTERN xdata volatile BYTE FLOWEQ1CTL _AT_ 0xE6C9; //CTL states during hold flow state
|
||||
EXTERN xdata volatile BYTE FLOWHOLDOFF _AT_ 0xE6CA;
|
||||
EXTERN xdata volatile BYTE FLOWSTB _AT_ 0xE6CB; //CTL/RDY Signal to use as master data strobe
|
||||
EXTERN xdata volatile BYTE FLOWSTBEDGE _AT_ 0xE6CC; //Defines active master strobe edge
|
||||
EXTERN xdata volatile BYTE FLOWSTBHPERIOD _AT_ 0xE6CD; //Half Period of output master strobe
|
||||
EXTERN xdata volatile BYTE GPIFHOLDAMOUNT _AT_ 0xE60C; //Data delay shift
|
||||
EXTERN xdata volatile BYTE UDMACRCH _AT_ 0xE67D; //CRC Upper byte
|
||||
EXTERN xdata volatile BYTE UDMACRCL _AT_ 0xE67E; //CRC Lower byte
|
||||
EXTERN xdata volatile BYTE UDMACRCQUAL _AT_ 0xE67F; //UDMA In only, host terminated use only
|
||||
|
||||
|
||||
// Debug/Test
|
||||
// The following registers are for Cypress's internal testing purposes only.
|
||||
// These registers are not documented in the datasheet or the Technical Reference
|
||||
// Manual as they were not designed for end user application usage
|
||||
EXTERN xdata volatile BYTE DBUG _AT_ 0xE6F8; // Debug
|
||||
EXTERN xdata volatile BYTE TESTCFG _AT_ 0xE6F9; // Test configuration
|
||||
EXTERN xdata volatile BYTE USBTEST _AT_ 0xE6FA; // USB Test Modes
|
||||
EXTERN xdata volatile BYTE CT1 _AT_ 0xE6FB; // Chirp Test--Override
|
||||
EXTERN xdata volatile BYTE CT2 _AT_ 0xE6FC; // Chirp Test--FSM
|
||||
EXTERN xdata volatile BYTE CT3 _AT_ 0xE6FD; // Chirp Test--Control Signals
|
||||
EXTERN xdata volatile BYTE CT4 _AT_ 0xE6FE; // Chirp Test--Inputs
|
||||
|
||||
// Endpoint Buffers
|
||||
|
||||
EXTERN xdata volatile BYTE EP0BUF[64] _AT_ 0xE740; // EP0 IN-OUT buffer
|
||||
EXTERN xdata volatile BYTE EP1OUTBUF[64] _AT_ 0xE780; // EP1-OUT buffer
|
||||
EXTERN xdata volatile BYTE EP1INBUF[64] _AT_ 0xE7C0; // EP1-IN buffer
|
||||
EXTERN xdata volatile BYTE EP2FIFOBUF[1024] _AT_ 0xF000; // 512/1024-byte EP2 buffer (IN or OUT)
|
||||
EXTERN xdata volatile BYTE EP4FIFOBUF[1024] _AT_ 0xF400; // 512 byte EP4 buffer (IN or OUT)
|
||||
EXTERN xdata volatile BYTE EP6FIFOBUF[1024] _AT_ 0xF800; // 512/1024-byte EP6 buffer (IN or OUT)
|
||||
EXTERN xdata volatile BYTE EP8FIFOBUF[1024] _AT_ 0xFC00; // 512 byte EP8 buffer (IN or OUT)
|
||||
|
||||
// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
|
||||
|
||||
EXTERN xdata volatile BYTE ECCCFG _AT_ 0xE628; // ECC Configuration
|
||||
EXTERN xdata volatile BYTE ECCRESET _AT_ 0xE629; // ECC Reset
|
||||
EXTERN xdata volatile BYTE ECC1B0 _AT_ 0xE62A; // ECC1 Byte 0
|
||||
EXTERN xdata volatile BYTE ECC1B1 _AT_ 0xE62B; // ECC1 Byte 1
|
||||
EXTERN xdata volatile BYTE ECC1B2 _AT_ 0xE62C; // ECC1 Byte 2
|
||||
EXTERN xdata volatile BYTE ECC2B0 _AT_ 0xE62D; // ECC2 Byte 0
|
||||
EXTERN xdata volatile BYTE ECC2B1 _AT_ 0xE62E; // ECC2 Byte 1
|
||||
EXTERN xdata volatile BYTE ECC2B2 _AT_ 0xE62F; // ECC2 Byte 2
|
||||
|
||||
// Feature Registers (FX2LP/FX1 only)
|
||||
EXTERN xdata volatile BYTE GPCR2 _AT_ 0xE50D; // Chip Features
|
||||
|
||||
#undef EXTERN
|
||||
#undef _AT_
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Special Function Registers (SFRs)
|
||||
The byte registers and bits defined in the following list are based
|
||||
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
|
||||
If you modify the register definitions below, please regenerate the file
|
||||
"ezregs.inc" which includes the same basic information for assembly inclusion.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
sfr IOA = 0x80;
|
||||
/* IOA */
|
||||
sbit PA0 = 0x80 + 0;
|
||||
sbit PA1 = 0x80 + 1;
|
||||
sbit PA2 = 0x80 + 2;
|
||||
sbit PA3 = 0x80 + 3;
|
||||
|
||||
sbit PA4 = 0x80 + 4;
|
||||
sbit PA5 = 0x80 + 5;
|
||||
sbit PA6 = 0x80 + 6;
|
||||
sbit PA7 = 0x80 + 7;
|
||||
sfr SP = 0x81;
|
||||
sfr DPL = 0x82;
|
||||
sfr DPH = 0x83;
|
||||
sfr DPL1 = 0x84;
|
||||
sfr DPH1 = 0x85;
|
||||
sfr DPS = 0x86;
|
||||
/* DPS */
|
||||
// sbit SEL = 0x86+0;
|
||||
sfr PCON = 0x87;
|
||||
/* PCON */
|
||||
//sbit IDLE = 0x87+0;
|
||||
//sbit STOP = 0x87+1;
|
||||
//sbit GF0 = 0x87+2;
|
||||
//sbit GF1 = 0x87+3;
|
||||
//sbit SMOD0 = 0x87+7;
|
||||
sfr TCON = 0x88;
|
||||
/* TCON */
|
||||
sbit IT0 = 0x88+0;
|
||||
sbit IE0 = 0x88+1;
|
||||
sbit IT1 = 0x88+2;
|
||||
sbit IE1 = 0x88+3;
|
||||
sbit TR0 = 0x88+4;
|
||||
sbit TF0 = 0x88+5;
|
||||
sbit TR1 = 0x88+6;
|
||||
sbit TF1 = 0x88+7;
|
||||
sfr TMOD = 0x89;
|
||||
/* TMOD */
|
||||
//sbit M00 = 0x89+0;
|
||||
//sbit M10 = 0x89+1;
|
||||
//sbit CT0 = 0x89+2;
|
||||
//sbit GATE0 = 0x89+3;
|
||||
//sbit M01 = 0x89+4;
|
||||
//sbit M11 = 0x89+5;
|
||||
//sbit CT1 = 0x89+6;
|
||||
//sbit GATE1 = 0x89+7;
|
||||
sfr TL0 = 0x8A;
|
||||
sfr TL1 = 0x8B;
|
||||
sfr TH0 = 0x8C;
|
||||
sfr TH1 = 0x8D;
|
||||
sfr CKCON = 0x8E;
|
||||
/* CKCON */
|
||||
//sbit MD0 = 0x89+0;
|
||||
//sbit MD1 = 0x89+1;
|
||||
//sbit MD2 = 0x89+2;
|
||||
//sbit T0M = 0x89+3;
|
||||
//sbit T1M = 0x89+4;
|
||||
//sbit T2M = 0x89+5;
|
||||
sfr SPC_FNC = 0x8F; // Was WRS in Reg320
|
||||
/* CKCON */
|
||||
//sbit WRS = 0x8F+0;
|
||||
sfr IOB = 0x90;
|
||||
/* IOB */
|
||||
sbit PB0 = 0x90 + 0;
|
||||
sbit PB1 = 0x90 + 1;
|
||||
sbit PB2 = 0x90 + 2;
|
||||
sbit PB3 = 0x90 + 3;
|
||||
|
||||
sbit PB4 = 0x90 + 4;
|
||||
sbit PB5 = 0x90 + 5;
|
||||
sbit PB6 = 0x90 + 6;
|
||||
sbit PB7 = 0x90 + 7;
|
||||
sfr EXIF = 0x91; // EXIF Bit Values differ from Reg320
|
||||
/* EXIF */
|
||||
//sbit USBINT = 0x91+4;
|
||||
//sbit I2CINT = 0x91+5;
|
||||
//sbit IE4 = 0x91+6;
|
||||
//sbit IE5 = 0x91+7;
|
||||
sfr MPAGE = 0x92;
|
||||
sfr SCON0 = 0x98;
|
||||
/* SCON0 */
|
||||
sbit RI = 0x98+0;
|
||||
sbit TI = 0x98+1;
|
||||
sbit RB8 = 0x98+2;
|
||||
sbit TB8 = 0x98+3;
|
||||
sbit REN = 0x98+4;
|
||||
sbit SM2 = 0x98+5;
|
||||
sbit SM1 = 0x98+6;
|
||||
sbit SM0 = 0x98+7;
|
||||
sfr SBUF0 = 0x99;
|
||||
|
||||
#define AUTOPTR1H AUTOPTRH1 // for backwards compatibility with examples
|
||||
#define AUTOPTR1L AUTOPTRL1 // for backwards compatibility with examples
|
||||
#define APTR1H AUTOPTRH1 // for backwards compatibility with examples
|
||||
#define APTR1L AUTOPTRL1 // for backwards compatibility with examples
|
||||
|
||||
// this is how they are defined in the TRM
|
||||
sfr AUTOPTRH1 = 0x9A;
|
||||
sfr AUTOPTRL1 = 0x9B;
|
||||
sfr AUTOPTRH2 = 0x9D;
|
||||
sfr AUTOPTRL2 = 0x9E;
|
||||
|
||||
sfr IOC = 0xA0;
|
||||
/* IOC */
|
||||
sbit PC0 = 0xA0 + 0;
|
||||
sbit PC1 = 0xA0 + 1;
|
||||
sbit PC2 = 0xA0 + 2;
|
||||
sbit PC3 = 0xA0 + 3;
|
||||
|
||||
sbit PC4 = 0xA0 + 4;
|
||||
sbit PC5 = 0xA0 + 5;
|
||||
sbit PC6 = 0xA0 + 6;
|
||||
sbit PC7 = 0xA0 + 7;
|
||||
sfr INT2CLR = 0xA1;
|
||||
sfr INT4CLR = 0xA2;
|
||||
|
||||
sfr IE = 0xA8;
|
||||
/* IE */
|
||||
sbit EX0 = 0xA8+0;
|
||||
sbit ET0 = 0xA8+1;
|
||||
sbit EX1 = 0xA8+2;
|
||||
sbit ET1 = 0xA8+3;
|
||||
sbit ES0 = 0xA8+4;
|
||||
sbit ET2 = 0xA8+5;
|
||||
sbit ES1 = 0xA8+6;
|
||||
sbit EA = 0xA8+7;
|
||||
|
||||
sfr EP2468STAT = 0xAA;
|
||||
/* EP2468STAT */
|
||||
//sbit EP2E = 0xAA+0;
|
||||
//sbit EP2F = 0xAA+1;
|
||||
//sbit EP4E = 0xAA+2;
|
||||
//sbit EP4F = 0xAA+3;
|
||||
//sbit EP6E = 0xAA+4;
|
||||
//sbit EP6F = 0xAA+5;
|
||||
//sbit EP8E = 0xAA+6;
|
||||
//sbit EP8F = 0xAA+7;
|
||||
|
||||
sfr EP24FIFOFLGS = 0xAB;
|
||||
sfr EP68FIFOFLGS = 0xAC;
|
||||
sfr AUTOPTRSETUP = 0xAF;
|
||||
/* AUTOPTRSETUP */
|
||||
// sbit EXTACC = 0xAF+0;
|
||||
// sbit APTR1FZ = 0xAF+1;
|
||||
// sbit APTR2FZ = 0xAF+2;
|
||||
|
||||
sfr IOD = 0xB0;
|
||||
/* IOD */
|
||||
sbit PD0 = 0xB0 + 0;
|
||||
sbit PD1 = 0xB0 + 1;
|
||||
sbit PD2 = 0xB0 + 2;
|
||||
sbit PD3 = 0xB0 + 3;
|
||||
|
||||
sbit PD4 = 0xB0 + 4;
|
||||
sbit PD5 = 0xB0 + 5;
|
||||
sbit PD6 = 0xB0 + 6;
|
||||
sbit PD7 = 0xB0 + 7;
|
||||
sfr IOE = 0xB1;
|
||||
sfr OEA = 0xB2;
|
||||
sfr OEB = 0xB3;
|
||||
sfr OEC = 0xB4;
|
||||
sfr OED = 0xB5;
|
||||
sfr OEE = 0xB6;
|
||||
|
||||
sfr IP = 0xB8;
|
||||
/* IP */
|
||||
sbit PX0 = 0xB8+0;
|
||||
sbit PT0 = 0xB8+1;
|
||||
sbit PX1 = 0xB8+2;
|
||||
sbit PT1 = 0xB8+3;
|
||||
sbit PS0 = 0xB8+4;
|
||||
sbit PT2 = 0xB8+5;
|
||||
sbit PS1 = 0xB8+6;
|
||||
|
||||
sfr EP01STAT = 0xBA;
|
||||
sfr GPIFTRIG = 0xBB;
|
||||
|
||||
sfr GPIFSGLDATH = 0xBD;
|
||||
sfr GPIFSGLDATLX = 0xBE;
|
||||
sfr GPIFSGLDATLNOX = 0xBF;
|
||||
|
||||
sfr SCON1 = 0xC0;
|
||||
/* SCON1 */
|
||||
sbit RI1 = 0xC0+0;
|
||||
sbit TI1 = 0xC0+1;
|
||||
sbit RB81 = 0xC0+2;
|
||||
sbit TB81 = 0xC0+3;
|
||||
sbit REN1 = 0xC0+4;
|
||||
sbit SM21 = 0xC0+5;
|
||||
sbit SM11 = 0xC0+6;
|
||||
sbit SM01 = 0xC0+7;
|
||||
sfr SBUF1 = 0xC1;
|
||||
sfr T2CON = 0xC8;
|
||||
/* T2CON */
|
||||
sbit CP_RL2 = 0xC8+0;
|
||||
sbit C_T2 = 0xC8+1;
|
||||
sbit TR2 = 0xC8+2;
|
||||
sbit EXEN2 = 0xC8+3;
|
||||
sbit TCLK = 0xC8+4;
|
||||
sbit RCLK = 0xC8+5;
|
||||
sbit EXF2 = 0xC8+6;
|
||||
sbit TF2 = 0xC8+7;
|
||||
sfr RCAP2L = 0xCA;
|
||||
sfr RCAP2H = 0xCB;
|
||||
sfr TL2 = 0xCC;
|
||||
sfr TH2 = 0xCD;
|
||||
sfr PSW = 0xD0;
|
||||
/* PSW */
|
||||
sbit P = 0xD0+0;
|
||||
sbit FL = 0xD0+1;
|
||||
sbit OV = 0xD0+2;
|
||||
sbit RS0 = 0xD0+3;
|
||||
sbit RS1 = 0xD0+4;
|
||||
sbit F0 = 0xD0+5;
|
||||
sbit AC = 0xD0+6;
|
||||
sbit CY = 0xD0+7;
|
||||
sfr EICON = 0xD8; // Was WDCON in DS80C320; Bit Values differ from Reg320
|
||||
/* EICON */
|
||||
sbit INT6 = 0xD8+3;
|
||||
sbit RESI = 0xD8+4;
|
||||
sbit ERESI = 0xD8+5;
|
||||
sbit SMOD1 = 0xD8+7;
|
||||
sfr ACC = 0xE0;
|
||||
sfr EIE = 0xE8; // EIE Bit Values differ from Reg320
|
||||
/* EIE */
|
||||
sbit EUSB = 0xE8+0;
|
||||
sbit EI2C = 0xE8+1;
|
||||
sbit EIEX4 = 0xE8+2;
|
||||
sbit EIEX5 = 0xE8+3;
|
||||
sbit EIEX6 = 0xE8+4;
|
||||
sfr B = 0xF0;
|
||||
sfr EIP = 0xF8; // EIP Bit Values differ from Reg320
|
||||
/* EIP */
|
||||
sbit PUSB = 0xF8+0;
|
||||
sbit PI2C = 0xF8+1;
|
||||
sbit EIPX4 = 0xF8+2;
|
||||
sbit EIPX5 = 0xF8+3;
|
||||
sbit EIPX6 = 0xF8+4;
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Bit Masks
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
/* CPU Control & Status Register (CPUCS) */
|
||||
#define bmPRTCSTB bmBIT5
|
||||
#define bmCLKSPD (bmBIT4 | bmBIT3)
|
||||
#define bmCLKSPD1 bmBIT4
|
||||
#define bmCLKSPD0 bmBIT3
|
||||
#define bmCLKINV bmBIT2
|
||||
#define bmCLKOE bmBIT1
|
||||
#define bm8051RES bmBIT0
|
||||
/* Port Alternate Configuration Registers */
|
||||
/* Port A (PORTACFG) */
|
||||
#define bmFLAGD bmBIT7
|
||||
#define bmINT1 bmBIT1
|
||||
#define bmINT0 bmBIT0
|
||||
/* Port C (PORTCCFG) */
|
||||
#define bmGPIFA7 bmBIT7
|
||||
#define bmGPIFA6 bmBIT6
|
||||
#define bmGPIFA5 bmBIT5
|
||||
#define bmGPIFA4 bmBIT4
|
||||
#define bmGPIFA3 bmBIT3
|
||||
#define bmGPIFA2 bmBIT2
|
||||
#define bmGPIFA1 bmBIT1
|
||||
#define bmGPIFA0 bmBIT0
|
||||
/* Port E (PORTECFG) */
|
||||
#define bmGPIFA8 bmBIT7
|
||||
#define bmT2EX bmBIT6
|
||||
#define bmINT6 bmBIT5
|
||||
#define bmRXD1OUT bmBIT4
|
||||
#define bmRXD0OUT bmBIT3
|
||||
#define bmT2OUT bmBIT2
|
||||
#define bmT1OUT bmBIT1
|
||||
#define bmT0OUT bmBIT0
|
||||
|
||||
/* I2C Control & Status Register (I2CS) */
|
||||
#define bmSTART bmBIT7
|
||||
#define bmSTOP bmBIT6
|
||||
#define bmLASTRD bmBIT5
|
||||
#define bmID (bmBIT4 | bmBIT3)
|
||||
#define bmBERR bmBIT2
|
||||
#define bmACK bmBIT1
|
||||
#define bmDONE bmBIT0
|
||||
/* I2C Control Register (I2CTL) */
|
||||
#define bmSTOPIE bmBIT1
|
||||
#define bm400KHZ bmBIT0
|
||||
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
|
||||
#define bmIV4 bmBIT6
|
||||
#define bmIV3 bmBIT5
|
||||
#define bmIV2 bmBIT4
|
||||
#define bmIV1 bmBIT3
|
||||
#define bmIV0 bmBIT2
|
||||
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
|
||||
#define bmEP0ACK bmBIT6
|
||||
#define bmHSGRANT bmBIT5
|
||||
#define bmURES bmBIT4
|
||||
#define bmSUSP bmBIT3
|
||||
#define bmSUTOK bmBIT2
|
||||
#define bmSOF bmBIT1
|
||||
#define bmSUDAV bmBIT0
|
||||
/* Breakpoint register (BREAKPT) */
|
||||
#define bmBREAK bmBIT3
|
||||
#define bmBPPULSE bmBIT2
|
||||
#define bmBPEN bmBIT1
|
||||
/* Interrupt 2 & 4 Setup (INTSETUP) */
|
||||
#define bmAV2EN bmBIT3
|
||||
#define INT4IN bmBIT1
|
||||
#define bmAV4EN bmBIT0
|
||||
/* USB Control & Status Register (USBCS) */
|
||||
#define bmHSM bmBIT7
|
||||
#define bmDISCON bmBIT3
|
||||
#define bmNOSYNSOF bmBIT2
|
||||
#define bmRENUM bmBIT1
|
||||
#define bmSIGRESUME bmBIT0
|
||||
/* Wakeup Control and Status Register (WAKEUPCS) */
|
||||
#define bmWU2 bmBIT7
|
||||
#define bmWU bmBIT6
|
||||
#define bmWU2POL bmBIT5
|
||||
#define bmWUPOL bmBIT4
|
||||
#define bmDPEN bmBIT2
|
||||
#define bmWU2EN bmBIT1
|
||||
#define bmWUEN bmBIT0
|
||||
/* End Point 0 Control & Status Register (EP0CS) */
|
||||
#define bmHSNAK bmBIT7
|
||||
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
|
||||
#define bmEPBUSY bmBIT1
|
||||
#define bmEPSTALL bmBIT0
|
||||
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
|
||||
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
|
||||
#define bmEPFULL bmBIT3
|
||||
#define bmEPEMPTY bmBIT2
|
||||
/* Endpoint Status (EP2468STAT) SFR bits */
|
||||
#define bmEP8FULL bmBIT7
|
||||
#define bmEP8EMPTY bmBIT6
|
||||
#define bmEP6FULL bmBIT5
|
||||
#define bmEP6EMPTY bmBIT4
|
||||
#define bmEP4FULL bmBIT3
|
||||
#define bmEP4EMPTY bmBIT2
|
||||
#define bmEP2FULL bmBIT1
|
||||
#define bmEP2EMPTY bmBIT0
|
||||
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
|
||||
#define bmSDPAUTO bmBIT0
|
||||
/* Endpoint Data Toggle Control (TOGCTL) */
|
||||
#define bmQUERYTOGGLE bmBIT7
|
||||
#define bmSETTOGGLE bmBIT6
|
||||
#define bmRESETTOGGLE bmBIT5
|
||||
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
|
||||
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
|
||||
#define bmEP8IBN bmBIT5
|
||||
#define bmEP6IBN bmBIT4
|
||||
#define bmEP4IBN bmBIT3
|
||||
#define bmEP2IBN bmBIT2
|
||||
#define bmEP1IBN bmBIT1
|
||||
#define bmEP0IBN bmBIT0
|
||||
|
||||
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
|
||||
#define bmEP8PING bmBIT7
|
||||
#define bmEP6PING bmBIT6
|
||||
#define bmEP4PING bmBIT5
|
||||
#define bmEP2PING bmBIT4
|
||||
#define bmEP1PING bmBIT3
|
||||
#define bmEP0PING bmBIT2
|
||||
#define bmIBN bmBIT0
|
||||
|
||||
/* Interface Configuration bits (IFCONFIG) */
|
||||
#define bmIFCLKSRC bmBIT7
|
||||
#define bm3048MHZ bmBIT6
|
||||
#define bmIFCLKOE bmBIT5
|
||||
#define bmIFCLKPOL bmBIT4
|
||||
#define bmASYNC bmBIT3
|
||||
#define bmGSTATE bmBIT2
|
||||
#define bmIFCFG1 bmBIT1
|
||||
#define bmIFCFG0 bmBIT0
|
||||
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
|
||||
#define bmIFGPIF bmIFCFG1
|
||||
|
||||
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
|
||||
#define bmINFM bmBIT6
|
||||
#define bmOEP bmBIT5
|
||||
#define bmAUTOOUT bmBIT4
|
||||
#define bmAUTOIN bmBIT3
|
||||
#define bmZEROLENIN bmBIT2
|
||||
#define bmWORDWIDE bmBIT0
|
||||
|
||||
/* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
|
||||
features */
|
||||
#define bmNOAUTOARM bmBIT1
|
||||
#define bmSKIPCOMMIT bmBIT0
|
||||
|
||||
/* Fifo Reset bits (FIFORESET) */
|
||||
#define bmNAKALL bmBIT7
|
||||
|
||||
/* Chip Feature Register (GPCR2) */
|
||||
#define bmFULLSPEEDONLY bmBIT4
|
||||
|
||||
#endif /* FX2REGS_H */
|
||||
@@ -0,0 +1,242 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: fx2sdly.h
|
||||
// Contents: EZ-USB FX2 Synchronization Delay (SYNCDELAY) Macro
|
||||
//
|
||||
// Enter with _IFREQ = IFCLK in kHz
|
||||
// Enter with _CFREQ = CLKOUT in kHz
|
||||
//
|
||||
// Copyright (c) 2001 Cypress Semiconductor, All rights reserved
|
||||
//
|
||||
// $Id: fx2sdly.h 15170 2010-04-30 06:27:56Z ritt $
|
||||
//-----------------------------------------------------------------------------
|
||||
#include "intrins.h"
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
// _IFREQ can be in the range of: 5000 to 48000
|
||||
#ifndef _IFREQ
|
||||
#define _IFREQ 48000 // IFCLK frequency in kHz
|
||||
#endif
|
||||
|
||||
// CFREQ can be any one of: 48000, 24000, or 12000
|
||||
#ifndef _CFREQ
|
||||
#define _CFREQ 48000 // CLKOUT frequency in kHz
|
||||
#endif
|
||||
|
||||
#if( _IFREQ < 5000 )
|
||||
#error "_IFREQ too small! Valid Range: 5000 to 48000..."
|
||||
#endif
|
||||
|
||||
#if( _IFREQ > 48000 )
|
||||
#error "_IFREQ too large! Valid Range: 5000 to 48000..."
|
||||
#endif
|
||||
|
||||
#if( _CFREQ != 48000 )
|
||||
#if( _CFREQ != 24000 )
|
||||
#if( _CFREQ != 12000 )
|
||||
#error "_CFREQ invalid! Valid values: 48000, 24000, 12000..."
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Synchronization Delay formula: see TRM section 15-14
|
||||
#define _SCYCL ( 3*(_CFREQ) + 5*(_IFREQ) - 1 ) / ( 2*(_IFREQ) )
|
||||
|
||||
#if( _SCYCL == 1 )
|
||||
#define SYNCDELAY _nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 2 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 3 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 4 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 5 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 6 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 7 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 8 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 9 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 10 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 11 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 12 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 13 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 14 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 15 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 16 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,928 @@
|
||||
; Copyright 1991-2007 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
|
||||
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
|
||||
|
||||
UNISIMS_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\unisims_ver
|
||||
UNI9000_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\uni9000_ver
|
||||
SIMPRIMS_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\simprims_ver
|
||||
XILINXCORELIB_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\XilinxCoreLib_ver
|
||||
AIM_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\abel_ver\aim_ver
|
||||
CPLD_VER = c:\Modeltech_6.2f\xilinx_ise_acutal\cpld_ver
|
||||
UNISIM = c:\Modeltech_6.2f\xilinx_ise_acutal\unisim
|
||||
SIMPRIM = c:\Modeltech_6.2f\xilinx_ise_acutal\simprim
|
||||
XILINXCORELIB = c:\Modeltech_6.2f\xilinx_ise_acutal\XilinxCoreLib
|
||||
AIM = c:\Modeltech_6.2f\xilinx_ise_acutal\abel\aim
|
||||
PLS = c:\Modeltech_6.2f\xilinx_ise_acutal\abel\pls
|
||||
CPLD = c:\Modeltech_6.2f\xilinx_ise_acutal\cpld
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Turn off PSL assertion warning messages. Default is to show warnings.
|
||||
; Show_PslChecksWarnings = 0
|
||||
|
||||
; Enable parsing of embedded PSL assertions. Default is enabled.
|
||||
; EmbeddedPsl = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Treat as errors:
|
||||
; case statement static warnings
|
||||
; warnings caused by aggregates that are not locally static
|
||||
; Overrides NoCaseStaticError, NoOthersStaticError settings.
|
||||
; PedanticErrors = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Perform default binding at compile time.
|
||||
; Default is to do default binding at load time.
|
||||
; BindAtCompile=1;
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
; Run the 0in tools from within the simulator.
|
||||
; Default value set to 0. Please set it to 1 to invoke 0in.
|
||||
; VcomZeroIn = 1
|
||||
|
||||
; Set the options to be passed to the 0in tools.
|
||||
; Default value set to "". Please set it to appropriate options needed.
|
||||
; VcomZeroInOptions = ""
|
||||
|
||||
; Turn off code coverage in VHDL subprograms. Default is on.
|
||||
; CoverageNoSub = 0
|
||||
|
||||
; Automatically exclude VHDL case statement default branches.
|
||||
; Default is to not exclude.
|
||||
; CoverExcludeDefault = 1
|
||||
|
||||
; Turn on code coverage in VHDL generate blocks. Default is off.
|
||||
; CoverGenerate = 1
|
||||
|
||||
; Use this directory for compiler temporary files instead of "work/_temp"
|
||||
; CompilerTempDir = /tmp
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn on `protect compiler directive processing.
|
||||
; Default is to ignore `protect directives.
|
||||
; Protect = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn on bad option warning. Default is off.
|
||||
; Show_BadOptionWarning = 1
|
||||
|
||||
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
|
||||
vlog95compat = 0
|
||||
|
||||
; Turn off PSL warning messages. Default is to show warnings.
|
||||
; Show_PslChecksWarnings = 0
|
||||
|
||||
; Enable parsing of embedded PSL assertions. Default is enabled.
|
||||
; EmbeddedPsl = 0
|
||||
|
||||
; Set the threshold for automatically identifying sparse Verilog memories.
|
||||
; A memory with depth equal to or more than the sparse memory threshold gets
|
||||
; marked as sparse automatically, unless specified otherwise in source code.
|
||||
; The default is 0 (i.e. no memory is automatically given sparse status)
|
||||
; SparseMemThreshold = 1048576
|
||||
|
||||
; Set the maximum number of iterations permitted for a generate loop.
|
||||
; Restricting this permits the implementation to recognize infinite
|
||||
; generate loops.
|
||||
; GenerateLoopIterationMax = 100000
|
||||
|
||||
; Set the maximum depth permitted for a recursive generate instantiation.
|
||||
; Restricting this permits the implementation to recognize infinite
|
||||
; recursions.
|
||||
; GenerateRecursionDepthMax = 200
|
||||
|
||||
; Run the 0in tools from within the simulator.
|
||||
; Default value set to 0. Please set it to 1 to invoke 0in.
|
||||
; VlogZeroIn = 1
|
||||
|
||||
; Set the options to be passed to the 0in tools.
|
||||
; Default value set to "". Please set it to appropriate options needed.
|
||||
; VlogZeroInOptions = ""
|
||||
|
||||
; Run the 0in tools from within the simulator.
|
||||
; Default value set to 0. Please set it to 1 to invoke 0in.
|
||||
; VoptZeroIn = 1
|
||||
|
||||
; Set the options to be passed to the 0in tools.
|
||||
; Default value set to "". Please set it to appropriate options needed.
|
||||
; VoptZeroInOptions = ""
|
||||
|
||||
; Set the option to treat all files specified in a vlog invocation as a
|
||||
; single compilation unit. The default value is set to 0 which will treat
|
||||
; each file as a separate compilation unit as specified in the P1800 draft standard.
|
||||
; MultiFileCompilationUnit = 1
|
||||
|
||||
; Automatically exclude Verilog case statement default branches.
|
||||
; Default is to not exclude.
|
||||
; CoverExcludeDefault = 1
|
||||
|
||||
; Turn on code coverage in VLOG generate blocks. Default is off.
|
||||
; CoverGenerate = 1
|
||||
|
||||
; Specify the override for the default value of "cross_num_print_missing"
|
||||
; option for the Cross in Covergroups. If not specified then LRM default
|
||||
; value of 0 (zero) is used. This is a compile time option.
|
||||
; SVCrossNumPrintMissingDefault = 0
|
||||
|
||||
; Setting following to 1 would cause creation of variables which
|
||||
; would represent the value of Coverpoint expressions. This is used
|
||||
; in conjunction with "SVCoverpointExprVariablePrefix" option
|
||||
; in the modelsim.ini
|
||||
; EnableSVCoverpointExprVariable = 0
|
||||
|
||||
; Specify the override for the prefix used in forming the variable names
|
||||
; which represent the Coverpoint expressions. This is used in conjunction with
|
||||
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
|
||||
; The default prefix is "expr".
|
||||
; The variable name is
|
||||
; variable name => <prefix>_<coverpoint name>
|
||||
; SVCoverpointExprVariablePrefix = expr
|
||||
|
||||
; Override for the default value of the SystemVerilog covergroup,
|
||||
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
|
||||
; NOTE: It does not override specific assignments in SystemVerilog
|
||||
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
|
||||
; can override this value.
|
||||
; SVCovergroupGoalDefault = 100
|
||||
|
||||
; Override for the default value of the SystemVerilog covergroup,
|
||||
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
|
||||
; NOTE: It does not override specific assignments in SystemVerilog
|
||||
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
|
||||
; can override this value.
|
||||
; SVCovergroupTypeGoalDefault = 100
|
||||
|
||||
; Specify the override for the default value of "strobe" option for the
|
||||
; Covergroup Type. This is a compile time option which forces "strobe" to
|
||||
; a user specified default value and supersedes SystemVerilog specified
|
||||
; default value of '0'(zero). NOTE: This can be overriden by a runtime
|
||||
; modelsim.ini variable "SVCovergroupStrobeDefault".
|
||||
; SVCovergroupStrobeDefault = 0
|
||||
|
||||
[sccom]
|
||||
; Enable use of SCV include files and library. Default is off.
|
||||
; UseScv = 1
|
||||
|
||||
; Add C++ compiler options to the sccom command line by using this variable.
|
||||
; CppOptions = -g
|
||||
|
||||
; Use custom C++ compiler located at this path rather than the default path.
|
||||
; The path should point directly at a compiler executable.
|
||||
; CppPath = /usr/bin/g++
|
||||
|
||||
; Enable verbose messages from sccom. Default is off.
|
||||
; SccomVerbose = 1
|
||||
|
||||
; sccom logfile. Default is no logfile.
|
||||
; SccomLogfile = sccom.log
|
||||
|
||||
; Enable use of SC_MS include files and library. Default is off.
|
||||
; UseScMs = 1
|
||||
|
||||
[vsim]
|
||||
|
||||
; vopt flow
|
||||
; Set to turn on automatic optimization of a design.
|
||||
; Default is on
|
||||
VoptFlow = 1
|
||||
|
||||
; vopt automatic SDF
|
||||
; If automatic design optimization is on, enables automatic compilation
|
||||
; of SDF files.
|
||||
; Default is on, uncomment to turn off.
|
||||
; VoptAutoSDFCompile = 0
|
||||
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
resolution = 1ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 0 ps
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Control PSL and Verilog Assume directives during simulation
|
||||
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
|
||||
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
|
||||
; SimulateAssumeDirectives = 1
|
||||
|
||||
; Control the simulation of PSL and SVA
|
||||
; These switches can be overridden by the vsim command line switches:
|
||||
; -psl, -nopsl, -sva, -nosva.
|
||||
; Set SimulatePSL = 0 to disable PSL simulation
|
||||
; Set SimulatePSL = 1 to enable PSL simulation (default)
|
||||
; SimulatePSL = 1
|
||||
; Set SimulateSVA = 0 to disable SVA simulation
|
||||
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
|
||||
; SimulateSVA = 1
|
||||
|
||||
; Directives to license manager can be set either as single value or as
|
||||
; space separated multi-values:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license is not available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license (PE ONLY)
|
||||
; noviewer Disable checkout of msimviewer and vsim-viewer license
|
||||
; features (PE ONLY)
|
||||
; noslvhdl Disable checkout of qhsimvh and vsim license features
|
||||
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
|
||||
; nomix Disable checkout of msimhdlmix and hdlmix license features
|
||||
; nolnl Disable checkout of msimhdlsim and hdlsim license features
|
||||
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
|
||||
; features
|
||||
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
|
||||
; hdlmix license features
|
||||
; Single value:
|
||||
; License = plus
|
||||
; Multi-value:
|
||||
; License = noqueue plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog immediate assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; VHDL assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %i - Instance pathname with process
|
||||
; %O - Process name
|
||||
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
|
||||
; %P - Instance or Region path without leaf process
|
||||
; %F - File
|
||||
; %L - Line number of assertion or, if assertion is in a subprogram, line
|
||||
; from which the call is made
|
||||
; %% - Print '%' character
|
||||
; If specific format for assertion level is defined, use its format.
|
||||
; If specific format is not defined for assertion level:
|
||||
; - and if failure occurs during elaboration, use AssertionFormatBreakLine;
|
||||
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
|
||||
; level), use AssertionFormatBreak;
|
||||
; - otherwise, use AssertionFormat.
|
||||
; AssertionFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
|
||||
; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
|
||||
; Simulation Breakpoint messages
|
||||
; This flag controls the display of function names when reporting the location
|
||||
; where the simulator stops do to a breakpoint or fatal error.
|
||||
; Example w/function name: # Break in Process ctr at counter.vhd line 44
|
||||
; Example wo/function name: # Break at counter.vhd line 44
|
||||
ShowFunctions = 1
|
||||
|
||||
|
||||
; Default radix for all windows and commands.
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example: sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Specify a unique path separator for the Signal Spy set of functions.
|
||||
; The default will be to use the PathSeparator variable.
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
; SignalSpyPathSeparator = /
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Disable System Verilog assertion messages
|
||||
; Info and Warning are disabled by default
|
||||
; IgnoreSVAInfo = 0
|
||||
; IgnoreSVAWarning = 0
|
||||
; IgnoreSVAError = 1
|
||||
; IgnoreSVAFatal = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings when changing VHDL constants and generics
|
||||
; Default is 1 to generate warning messages
|
||||
; WarnConstantChange = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; Specify whether to enable SystemVerilog DPI out-of-the-blue call.
|
||||
; Out-of-the-blue call refers to a SystemVerilog export function call
|
||||
; directly from a C function that don't have the proper context setup
|
||||
; as done in DPI-C import C functions. When this is enabled, one can
|
||||
; call a DPI export function (but not task) from any C code.
|
||||
; The default is 0 (disabled).
|
||||
; DpiOutOfTheBlue = 1
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
|
||||
; This is necessary when C++ files have been compiled with aCC's -AA option.
|
||||
; The default behavior is to use /usr/lib/libCsup.sl.
|
||||
; UseCsupV2 = 1
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Specify whether or not a WLF file should be optimized during
|
||||
; simulation. If set to 0, the WLF file will not be optimized.
|
||||
; The default is 1, optimize the WLF file.
|
||||
; WLFOptimize = 0
|
||||
|
||||
; Specify the name of the WLF file.
|
||||
; The default is vsim.wlf
|
||||
; WLFFilename = vsim.wlf
|
||||
|
||||
; WLF reader cache size limit. Specifies the internal WLF file cache size,
|
||||
; in megabytes, for EACH open WLF file. A value of 0 turns off the
|
||||
; WLF cache.
|
||||
; The default setting is enabled to 256M per open WLF file.
|
||||
; WLFCacheSize = 1000
|
||||
|
||||
; Specify the WLF file event collapse mode.
|
||||
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
|
||||
; 1 = Only record values of logged objects at the end of a simulator iteration.
|
||||
; (same as -wlfcollapsedelta)
|
||||
; 2 = Only record values of logged objects at the end of a simulator time step.
|
||||
; (same as -wlfcollapsetime)
|
||||
; The default is 1.
|
||||
; WLFCollapseMode = 0
|
||||
|
||||
; Turn on/off undebuggable SystemC type warnings. Default is on.
|
||||
; ShowUndebuggableScTypeWarning = 0
|
||||
|
||||
; Turn on/off unassociated SystemC name warnings. Default is off.
|
||||
; ShowUnassociatedScNameWarning = 1
|
||||
|
||||
; Set SystemC default time unit.
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional
|
||||
; prefix of 1, 10, or 100. The default is 1 ns.
|
||||
; The ScTimeUnit value is honored if it is coarser than Resolution.
|
||||
; If ScTimeUnit is finer than Resolution, it is set to the value
|
||||
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
|
||||
; then the default time unit will be 1 ns. However if Resolution
|
||||
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
|
||||
ScTimeUnit = ns
|
||||
|
||||
; Set the SCV relationship name that will be used to identify phase
|
||||
; relations. If the name given to a transactor relation matches this
|
||||
; name, the transactions involved will be treated as phase transactions
|
||||
ScvPhaseRelationName = mti_phase
|
||||
|
||||
; Customize the vsim kernel shutdown behavior at the end of the simulation.
|
||||
; Some common causes of the end of simulation are $finish (implicit or explicit),
|
||||
; sc_stop(), tf_dofinish(), and assertion failures.
|
||||
; This should be set to "ask", "exit", or "stop". The default is "ask".
|
||||
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
|
||||
; In GUI mode, a dialog box will pop up and ask for user confirmation
|
||||
; whether or not to quit the simulation.
|
||||
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
|
||||
; post-simulation tasks easier.
|
||||
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
|
||||
; Note: these ini variables can be overriden by the vsim command
|
||||
; line switch "-onfinish <ask|stop|exit>".
|
||||
OnFinish = ask
|
||||
|
||||
; Print "simstats" result at the end of simulation before shutdown.
|
||||
; If this is enabled, the simstats result will be printed out before shutdown.
|
||||
; The default is off.
|
||||
; PrintSimStats = 1
|
||||
|
||||
; Run simulator in assertion debug mode. Default is off.
|
||||
; AssertionDebug = 1
|
||||
|
||||
; Turn on/off PSL/SVA concurrent assertion pass enable. Default is on.
|
||||
; AssertionPassEnable = 0
|
||||
|
||||
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
|
||||
; AssertionFailEnable = 0
|
||||
|
||||
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
|
||||
; Any positive integer, -1 for infinity.
|
||||
; AssertionPassLimit = 1
|
||||
|
||||
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
|
||||
; Any positive integer, -1 for infinity.
|
||||
; AssertionFailLimit = 1
|
||||
|
||||
; Turn on/off PSL concurrent assertion pass log. Default is off.
|
||||
; The flag does not affect SVA
|
||||
; AssertionPassLog = 1
|
||||
|
||||
; Turn on/off PSL concurrent assertion fail log. Default is on.
|
||||
; The flag does not affect SVA
|
||||
; AssertionFailLog = 0
|
||||
|
||||
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
|
||||
; 0 = Continue 1 = Break 2 = Exit
|
||||
; AssertionFailAction = 1
|
||||
|
||||
; Turn on/off code coverage
|
||||
; CodeCoverage = 0
|
||||
|
||||
; Count all code coverage condition and expression truth table rows that match.
|
||||
; CoverCountAll = 1
|
||||
|
||||
; Turn on/off all PSL/SVA cover directive enables. Default is on.
|
||||
; CoverEnable = 0
|
||||
|
||||
; Turn on/off PSL/SVA cover log. Default is off.
|
||||
; CoverLog = 1
|
||||
|
||||
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
|
||||
; CoverAtLeast = 2
|
||||
|
||||
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
|
||||
; Any positive integer, -1 for infinity.
|
||||
; CoverLimit = 1
|
||||
|
||||
; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close).
|
||||
; UCDBFilename = vsim.ucdb
|
||||
|
||||
; Specify the maximum limit for the number of Cross (bin) products reported
|
||||
; in XML and UCDB report against a Cross. A warning is issued if the limit
|
||||
; is crossed.
|
||||
; MaxReportRhsSVCrossProducts = 1000
|
||||
|
||||
; Specify the override for the "auto_bin_max" option for the Covergroups.
|
||||
; If not specified then value from Covergroup "option" is used.
|
||||
; SVCoverpointAutoBinMax = 64
|
||||
|
||||
; Specify the override for the value of "cross_num_print_missing"
|
||||
; option for the Cross in Covergroups. If not specified then value
|
||||
; specified in the "option.cross_num_print_missing" is used. This
|
||||
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
|
||||
; value specified by user in source file and any SVCrossNumPrintMissingDefault
|
||||
; specified in modelsim.ini.
|
||||
; SVCrossNumPrintMissing = 0
|
||||
|
||||
; Specify the override for the value of "strobe" option for the
|
||||
; Covergroup Type. If not specified then value in "type_option.strobe"
|
||||
; will be used. This is runtime option which forces "strobe" to
|
||||
; user specified value and supersedes user specified values in the
|
||||
; SystemVerilog Code. NOTE: This also overrides the compile time
|
||||
; default value override specified using "SVCovergroupStrobeDefault"
|
||||
; SVCovergroupStrobe = 0
|
||||
|
||||
; Override for explicit assignments in source code to "option.goal" of
|
||||
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
|
||||
; default value of "option.goal" (defined to be 100 in the SystemVerilog
|
||||
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
|
||||
; SVCovergroupGoal = 100
|
||||
|
||||
; Override for explicit assignments in source code to "type_option.goal" of
|
||||
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
|
||||
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
|
||||
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
|
||||
; SVCovergroupTypeGoal = 100
|
||||
|
||||
; Specify the maximum number of Coverpoint bins in whole design for
|
||||
; all Covergroups.
|
||||
; MaxSVCoverpointBinsDesign = 2147483648
|
||||
|
||||
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
|
||||
; MaxSVCoverpointBinsInst = 2147483648
|
||||
|
||||
; Specify the maximum number of Cross bins in whole design for
|
||||
; all Covergroups.
|
||||
; MaxSVCrossBinsDesign = 2147483648
|
||||
|
||||
; Specify maximum number of Cross bins in any instance of a Covergroup
|
||||
; MaxSVCrossBinsInst = 2147483648
|
||||
|
||||
; Set weight for all PSL/SVA cover directives. Default is 1.
|
||||
; CoverWeight = 2
|
||||
|
||||
; Check vsim plusargs. Default is 0 (off).
|
||||
; 0 = Don't check plusargs
|
||||
; 1 = Warning on unrecognized plusarg
|
||||
; 2 = Error and exit on unrecognized plusarg
|
||||
; CheckPlusargs = 1
|
||||
|
||||
; Load the specified shared objects with the RTLD_GLOBAL flag.
|
||||
; This gives global visibility to all symbols in the shared objects,
|
||||
; meaning that subsequently loaded shared objects can bind to symbols
|
||||
; in the global shared objects. The list of shared objects should
|
||||
; be whitespace delimited. This option is not supported on the
|
||||
; Windows or AIX platforms.
|
||||
; GlobalSharedObjectList = example1.so example2.so example3.so
|
||||
|
||||
; Run the 0in tools from within the simulator.
|
||||
; Default value set to 0. Please set it to 1 to invoke 0in.
|
||||
; VsimZeroIn = 1
|
||||
|
||||
; Set the options to be passed to the 0in tools.
|
||||
; Default value set to "". Please set it to appropriate options needed.
|
||||
; VsimZeroInOptions = ""
|
||||
|
||||
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
|
||||
; Sv_Seed = 0
|
||||
|
||||
; Maximum size of dynamic arrays that are resized during randomize().
|
||||
; The default is 1000. A value of 0 indicates no limit.
|
||||
; SolveArrayResizeMax = 1000
|
||||
|
||||
; Error message severity when randomize() failure is detected (SystemVerilog).
|
||||
; The default is 0 (no error).
|
||||
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
; SolveFailSeverity = 0
|
||||
|
||||
; Enable/disable debug information for randomize() failures (SystemVerilog).
|
||||
; The default is 0 (disabled). Set to 1 to enable.
|
||||
; SolveFailDebug = 0
|
||||
|
||||
; When SolveFailDebug is enabled, this value specifies the maximum number of
|
||||
; constraint subsets that will be tested for conflicts.
|
||||
; The default is 0 (no limit).
|
||||
; SolveFailDebugLimit = 0
|
||||
|
||||
; When SolveFailDebug is enabled, this value specifies the maximum size of
|
||||
; constraint subsets that will be tested for conflicts.
|
||||
; The default value is 0 (no limit).
|
||||
; SolveFailDebugMaxSet = 0
|
||||
|
||||
; Maximum size of the solution graph that may be generated during randomize().
|
||||
; This value can be used to force randomize() to abort if the complexity of
|
||||
; the constraint scenario (both in memory and time spent during evaluation)
|
||||
; exceeds the specified limit. This value is specified in 1000s of nodes.
|
||||
; The default is 10000. A value of 0 indicates no limit.
|
||||
; SolveGraphMaxSize = 10000
|
||||
|
||||
; Use SolveFlags to specify options that will guide the behavior of the
|
||||
; constraint solver. These options may improve the performance of the
|
||||
; constraint solver for some testcases, and decrease the performance of
|
||||
; the constraint solver for others.
|
||||
; The default value is "" (no options).
|
||||
;
|
||||
; Valid flags are:
|
||||
; i = disable bit interleaving for >, >=, <, <= constraints
|
||||
; r = reverse bit interleaving
|
||||
;
|
||||
; SolveFlags =
|
||||
|
||||
; Specify random sequence compatiblity with a prior letter release. This
|
||||
; option is used to get the same random sequences during simulation as
|
||||
; as a prior letter release. Only prior letter releases (of the current
|
||||
; number release) are allowed.
|
||||
; Note: To achieve the same random sequences, solver optimizations and/or
|
||||
; bug fixes introduced since the specified release may be disabled -
|
||||
; yielding the performance / behavior of the prior release.
|
||||
; Default value set to "" (random compatibility not required).
|
||||
; SolveRev =
|
||||
|
||||
; Environment variable expansion of command line arguments has been depricated
|
||||
; in favor shell level expansion. Universal environment variable expansion
|
||||
; inside -f files is support and continued support for MGC Location Maps provide
|
||||
; alternative methods for handling flexible pathnames.
|
||||
; The following line may be uncommented and the value set to 1 to re-enable this
|
||||
; deprecated behavior. The default value is 0.
|
||||
; DeprecatedEnvironmentVariableExpansion = 0
|
||||
|
||||
; Retroactive Recording uses a limited number of private data channels in the WLF
|
||||
; file. Too many channels degrade WLF performance. If the limit is reached,
|
||||
; simulation ends with a fatal error. You may change this limit as needed, but be
|
||||
; aware of the implications of too many channels. The value must be an integer
|
||||
; greater than or equal to zero, where zero disables all retroactive recording.
|
||||
; RetroChannelLimit = 20
|
||||
|
||||
; Options to give vopt when code coverage is turned on.
|
||||
; Default is "+acc=lprnb -opt=-merge -opt=-suppressAlways"
|
||||
; VoptCoverageOptions = +acc=lprnb -opt=-merge -opt=-suppressAlways
|
||||
|
||||
; Turn on/off collapsing of bus ports in VCD dumpports output
|
||||
DumpportsCollapse = 0
|
||||
|
||||
[lmc]
|
||||
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
|
||||
libsm = $MODEL_TECH/libsm.sl
|
||||
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libsm = $MODEL_TECH/libsm.dll
|
||||
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
||||
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
||||
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
||||
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
||||
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
||||
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
||||
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
||||
; Logic Modeling's SmartModel SWIFT software (Linux)
|
||||
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
|
||||
|
||||
; The simulator's interface to Logic Modeling's hardware modeler SFI software
|
||||
libhm = $MODEL_TECH/libhm.sl
|
||||
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
||||
; libhm = $MODEL_TECH/libhm.dll
|
||||
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
||||
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
|
||||
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
||||
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
|
||||
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
||||
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
|
||||
; Logic Modeling's hardware modeler SFI software (Windows NT)
|
||||
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
|
||||
; Logic Modeling's hardware modeler SFI software (Linux)
|
||||
; libsfi = <sfi_dir>/lib/linux/libsfi.so
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ReOpenSourceFiles = 1
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
EditorState = {tabbed horizontal 1} {C:/meg/online/VPC/drs4/src/usr_clocks.vhd 0 0} {C:/meg/online/VPC/drs4/sim/drs4_eval1_tb.vhd 0 0} {C:/meg/online/VPC/drs4/src/drs4_eval1.vhd 0 0} {C:/meg/online/VPC/drs4/src/usb2_racc.vhd 0 1}
|
||||
Project_Major_Version = 6
|
||||
Project_Minor_Version = 2
|
||||
@@ -0,0 +1,289 @@
|
||||
-- Xilinx Testbench Template produced by program netgen J.39
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
library WORK;
|
||||
library SIMPRIM;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use WORK.ALL;
|
||||
use SIMPRIM.VCOMPONENTS.ALL;
|
||||
use SIMPRIM.VPACKAGE.ALL;
|
||||
|
||||
entity TBX_drs4_eval1 is
|
||||
end TBX_drs4_eval1;
|
||||
|
||||
architecture TBX_ARCH of TBX_drs4_eval1 is
|
||||
component drs4_eval1
|
||||
port (
|
||||
P_IO_UC_SLWR : inout STD_LOGIC;
|
||||
P_IO_UC_PKTEND : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGA : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGB : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGC : inout STD_LOGIC;
|
||||
P_I_UC_PA0 : in STD_LOGIC;
|
||||
P_IO_UC_SLCS : inout STD_LOGIC;
|
||||
P_IO_UC_FIFOADR0 : inout STD_LOGIC;
|
||||
P_IO_UC_FIFOADR1 : inout STD_LOGIC;
|
||||
P_IO_UC_SLOE : inout STD_LOGIC;
|
||||
P_IO_UC_SLRD : inout STD_LOGIC;
|
||||
P_I_CLK33 : in STD_LOGIC := 'X';
|
||||
P_I_CLK66 : in STD_LOGIC := 'X';
|
||||
P_I_LEMO1 : in STD_LOGIC;
|
||||
P_I_J36 : in STD_LOGIC;
|
||||
P_I_J37 : in STD_LOGIC;
|
||||
P_IO_J38 : inout STD_LOGIC;
|
||||
P_IO_J39 : inout STD_LOGIC;
|
||||
P_I_ATRG : in STD_LOGIC;
|
||||
P_O_LED0 : out STD_LOGIC;
|
||||
P_O_LED1 : out STD_LOGIC;
|
||||
P_IO_PMC_USR : inout STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
P_IO_UC_FD : inout STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
end component;
|
||||
|
||||
signal P_IO_UC_SLWR : STD_LOGIC;
|
||||
signal P_IO_UC_PKTEND : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGA : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGB : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGC : STD_LOGIC;
|
||||
signal P_I_UC_PA0 : STD_LOGIC;
|
||||
signal P_IO_UC_SLCS : STD_LOGIC;
|
||||
signal P_IO_UC_FIFOADR0 : STD_LOGIC;
|
||||
signal P_IO_UC_FIFOADR1 : STD_LOGIC;
|
||||
signal P_IO_UC_SLOE : STD_LOGIC;
|
||||
signal P_IO_UC_SLRD : STD_LOGIC;
|
||||
signal P_I_CLK33 : STD_LOGIC;
|
||||
signal P_I_CLK66 : STD_LOGIC;
|
||||
signal P_I_J36 : STD_LOGIC;
|
||||
signal P_I_J37 : STD_LOGIC;
|
||||
signal P_IO_J38 : STD_LOGIC;
|
||||
signal P_IO_J39 : STD_LOGIC;
|
||||
signal P_I_ATRG : STD_LOGIC;
|
||||
signal P_O_LED0 : STD_LOGIC;
|
||||
signal P_O_LED1 : STD_LOGIC;
|
||||
signal P_I_LEMO1 : STD_LOGIC;
|
||||
signal P_IO_PMC_USR : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal P_IO_UC_FD : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
|
||||
begin
|
||||
UUT : drs4_eval1
|
||||
port map (
|
||||
P_IO_UC_SLWR => P_IO_UC_SLWR,
|
||||
P_IO_UC_PKTEND => P_IO_UC_PKTEND,
|
||||
P_IO_UC_FLAGA => P_IO_UC_FLAGA,
|
||||
P_IO_UC_FLAGB => P_IO_UC_FLAGB,
|
||||
P_IO_UC_FLAGC => P_IO_UC_FLAGC,
|
||||
P_I_UC_PA0 => P_I_UC_PA0,
|
||||
P_IO_UC_SLCS => P_IO_UC_SLCS,
|
||||
P_IO_UC_FIFOADR0 => P_IO_UC_FIFOADR0,
|
||||
P_IO_UC_FIFOADR1 => P_IO_UC_FIFOADR1,
|
||||
P_IO_UC_SLOE => P_IO_UC_SLOE,
|
||||
P_IO_UC_SLRD => P_IO_UC_SLRD,
|
||||
P_I_CLK33 => P_I_CLK33,
|
||||
P_I_CLK66 => P_I_CLK66,
|
||||
P_I_J36 => P_I_J36,
|
||||
P_I_J37 => P_I_J37,
|
||||
P_IO_J38 => P_IO_J38,
|
||||
P_IO_J39 => P_IO_J39,
|
||||
P_I_ATRG => P_I_ATRG,
|
||||
P_I_LEMO1 => P_I_LEMO1,
|
||||
P_O_LED0 => P_O_LED0,
|
||||
P_O_LED1 => P_O_LED1,
|
||||
P_IO_PMC_USR(63) => P_IO_PMC_USR(63),
|
||||
P_IO_PMC_USR(62) => P_IO_PMC_USR(62),
|
||||
P_IO_PMC_USR(61) => P_IO_PMC_USR(61),
|
||||
P_IO_PMC_USR(60) => P_IO_PMC_USR(60),
|
||||
P_IO_PMC_USR(59) => P_IO_PMC_USR(59),
|
||||
P_IO_PMC_USR(58) => P_IO_PMC_USR(58),
|
||||
P_IO_PMC_USR(57) => P_IO_PMC_USR(57),
|
||||
P_IO_PMC_USR(56) => P_IO_PMC_USR(56),
|
||||
P_IO_PMC_USR(55) => P_IO_PMC_USR(55),
|
||||
P_IO_PMC_USR(54) => P_IO_PMC_USR(54),
|
||||
P_IO_PMC_USR(53) => P_IO_PMC_USR(53),
|
||||
P_IO_PMC_USR(52) => P_IO_PMC_USR(52),
|
||||
P_IO_PMC_USR(51) => P_IO_PMC_USR(51),
|
||||
P_IO_PMC_USR(50) => P_IO_PMC_USR(50),
|
||||
P_IO_PMC_USR(49) => P_IO_PMC_USR(49),
|
||||
P_IO_PMC_USR(48) => P_IO_PMC_USR(48),
|
||||
P_IO_PMC_USR(47) => P_IO_PMC_USR(47),
|
||||
P_IO_PMC_USR(46) => P_IO_PMC_USR(46),
|
||||
P_IO_PMC_USR(45) => P_IO_PMC_USR(45),
|
||||
P_IO_PMC_USR(44) => P_IO_PMC_USR(44),
|
||||
P_IO_PMC_USR(43) => P_IO_PMC_USR(43),
|
||||
P_IO_PMC_USR(42) => P_IO_PMC_USR(42),
|
||||
P_IO_PMC_USR(41) => P_IO_PMC_USR(41),
|
||||
P_IO_PMC_USR(40) => P_IO_PMC_USR(40),
|
||||
P_IO_PMC_USR(39) => P_IO_PMC_USR(39),
|
||||
P_IO_PMC_USR(38) => P_IO_PMC_USR(38),
|
||||
P_IO_PMC_USR(37) => P_IO_PMC_USR(37),
|
||||
P_IO_PMC_USR(36) => P_IO_PMC_USR(36),
|
||||
P_IO_PMC_USR(35) => P_IO_PMC_USR(35),
|
||||
P_IO_PMC_USR(34) => P_IO_PMC_USR(34),
|
||||
P_IO_PMC_USR(33) => P_IO_PMC_USR(33),
|
||||
P_IO_PMC_USR(32) => P_IO_PMC_USR(32),
|
||||
P_IO_PMC_USR(31) => P_IO_PMC_USR(31),
|
||||
P_IO_PMC_USR(30) => P_IO_PMC_USR(30),
|
||||
P_IO_PMC_USR(29) => P_IO_PMC_USR(29),
|
||||
P_IO_PMC_USR(28) => P_IO_PMC_USR(28),
|
||||
P_IO_PMC_USR(27) => P_IO_PMC_USR(27),
|
||||
P_IO_PMC_USR(26) => P_IO_PMC_USR(26),
|
||||
P_IO_PMC_USR(25) => P_IO_PMC_USR(25),
|
||||
P_IO_PMC_USR(24) => P_IO_PMC_USR(24),
|
||||
P_IO_PMC_USR(23) => P_IO_PMC_USR(23),
|
||||
P_IO_PMC_USR(22) => P_IO_PMC_USR(22),
|
||||
P_IO_PMC_USR(21) => P_IO_PMC_USR(21),
|
||||
P_IO_PMC_USR(20) => P_IO_PMC_USR(20),
|
||||
P_IO_PMC_USR(19) => P_IO_PMC_USR(19),
|
||||
P_IO_PMC_USR(18) => P_IO_PMC_USR(18),
|
||||
P_IO_PMC_USR(17) => P_IO_PMC_USR(17),
|
||||
P_IO_PMC_USR(16) => P_IO_PMC_USR(16),
|
||||
P_IO_PMC_USR(15) => P_IO_PMC_USR(15),
|
||||
P_IO_PMC_USR(14) => P_IO_PMC_USR(14),
|
||||
P_IO_PMC_USR(13) => P_IO_PMC_USR(13),
|
||||
P_IO_PMC_USR(12) => P_IO_PMC_USR(12),
|
||||
P_IO_PMC_USR(11) => P_IO_PMC_USR(11),
|
||||
P_IO_PMC_USR(10) => P_IO_PMC_USR(10),
|
||||
P_IO_PMC_USR(9) => P_IO_PMC_USR(9),
|
||||
P_IO_PMC_USR(8) => P_IO_PMC_USR(8),
|
||||
P_IO_PMC_USR(7) => P_IO_PMC_USR(7),
|
||||
P_IO_PMC_USR(6) => P_IO_PMC_USR(6),
|
||||
P_IO_PMC_USR(5) => P_IO_PMC_USR(5),
|
||||
P_IO_PMC_USR(4) => P_IO_PMC_USR(4),
|
||||
P_IO_PMC_USR(3) => P_IO_PMC_USR(3),
|
||||
P_IO_PMC_USR(2) => P_IO_PMC_USR(2),
|
||||
P_IO_PMC_USR(1) => P_IO_PMC_USR(1),
|
||||
P_IO_PMC_USR(0) => P_IO_PMC_USR(0),
|
||||
P_IO_UC_FD(15) => P_IO_UC_FD(15),
|
||||
P_IO_UC_FD(14) => P_IO_UC_FD(14),
|
||||
P_IO_UC_FD(13) => P_IO_UC_FD(13),
|
||||
P_IO_UC_FD(12) => P_IO_UC_FD(12),
|
||||
P_IO_UC_FD(11) => P_IO_UC_FD(11),
|
||||
P_IO_UC_FD(10) => P_IO_UC_FD(10),
|
||||
P_IO_UC_FD(9) => P_IO_UC_FD(9),
|
||||
P_IO_UC_FD(8) => P_IO_UC_FD(8),
|
||||
P_IO_UC_FD(7) => P_IO_UC_FD(7),
|
||||
P_IO_UC_FD(6) => P_IO_UC_FD(6),
|
||||
P_IO_UC_FD(5) => P_IO_UC_FD(5),
|
||||
P_IO_UC_FD(4) => P_IO_UC_FD(4),
|
||||
P_IO_UC_FD(3) => P_IO_UC_FD(3),
|
||||
P_IO_UC_FD(2) => P_IO_UC_FD(2),
|
||||
P_IO_UC_FD(1) => P_IO_UC_FD(1),
|
||||
P_IO_UC_FD(0) => P_IO_UC_FD(0)
|
||||
);
|
||||
-- User: Put your stimulus here.
|
||||
|
||||
-- Clock generation
|
||||
proc_p_i_clk33_generator : process
|
||||
begin
|
||||
clock_loop : loop
|
||||
P_I_CLK33 <= '1';
|
||||
wait for 15 ns;
|
||||
P_I_CLK33 <= '0';
|
||||
wait for 15 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
proc_p_i_clk66_generator : process
|
||||
begin
|
||||
clock_loop : loop
|
||||
P_I_CLK66 <= '1';
|
||||
wait for 7.5 ns;
|
||||
P_I_CLK66 <= '0';
|
||||
wait for 7.5 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- Static signals
|
||||
P_I_LEMO1 <= '0';
|
||||
P_I_J36 <= '0';
|
||||
P_I_J37 <= '0';
|
||||
P_I_ATRG <= '0';
|
||||
|
||||
P_IO_UC_FLAGA <= '1';
|
||||
P_IO_UC_FLAGB <= '1';
|
||||
P_IO_UC_PKTEND <= 'Z';
|
||||
P_I_UC_PA0 <= '1';
|
||||
|
||||
-- Dynamic signals
|
||||
proc_p_io_dynamic: process
|
||||
|
||||
-- Write cycle
|
||||
-- -----------
|
||||
procedure proc_wr_cycle(
|
||||
constant I_A : in std_logic_vector(15 downto 0);
|
||||
constant I_D : in std_logic_vector(15 downto 0)
|
||||
) is
|
||||
begin
|
||||
P_IO_UC_FLAGC <= '1';
|
||||
P_IO_UC_FD <= X"0002"; -- USB2_CMD_WRITE
|
||||
wait until P_IO_UC_SLOE = '0';
|
||||
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= I_A; -- low word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= (others => '0'); -- high word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= X"0002"; -- low word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= (others => '0'); -- high word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= I_D;
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FLAGC <= '0';
|
||||
P_IO_UC_FD <= "ZZZZZZZZZZZZZZZZ"; -- tri state
|
||||
|
||||
end proc_wr_cycle;
|
||||
|
||||
begin
|
||||
|
||||
P_I_UC_PA0 <= '1';
|
||||
P_IO_UC_FD <= (others => '0');
|
||||
P_IO_UC_FLAGC <= '0';
|
||||
|
||||
wait for 990 ns; -- Until DLLs locked
|
||||
|
||||
proc_wr_cycle(X"0014", X"C000"); -- set ADC clock phase
|
||||
|
||||
wait for 70 us;
|
||||
|
||||
-- proc_wr_cycle(X"0000", X"0001"); -- start domino wave
|
||||
|
||||
-- wait for 3 us;
|
||||
|
||||
-- proc_wr_cycle(X"0000", X"0004"); -- issue soft trigger
|
||||
|
||||
-- wait for 100 us;
|
||||
|
||||
-- stop simulation
|
||||
assert false
|
||||
report "Simulation Complete (this is not a failure)"
|
||||
severity failure;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end TBX_ARCH;
|
||||
|
||||
configuration TBX_CFG_drs4_eval1_TBX_ARCH of TBX_drs4_eval1 is
|
||||
for TBX_ARCH
|
||||
end for;
|
||||
end TBX_CFG_drs4_eval1_TBX_ARCH;
|
||||
@@ -0,0 +1,263 @@
|
||||
-- Xilinx Testbench Template produced by program netgen J.39
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
library WORK;
|
||||
library SIMPRIM;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use WORK.ALL;
|
||||
use SIMPRIM.VCOMPONENTS.ALL;
|
||||
use SIMPRIM.VPACKAGE.ALL;
|
||||
|
||||
entity TBX_drs4_mezz1 is
|
||||
end TBX_drs4_mezz1;
|
||||
|
||||
architecture TBX_ARCH of TBX_drs4_mezz1 is
|
||||
component drs4_mezz1
|
||||
port (
|
||||
P_IO_UC_SLWR : inout STD_LOGIC;
|
||||
P_IO_UC_PKTEND : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGA : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGB : inout STD_LOGIC;
|
||||
P_IO_UC_FLAGC : inout STD_LOGIC;
|
||||
P_IO_UC_PA0 : in STD_LOGIC;
|
||||
P_IO_UC_SLCS : inout STD_LOGIC;
|
||||
P_IO_UC_FIFOADR0 : inout STD_LOGIC;
|
||||
P_IO_UC_FIFOADR1 : inout STD_LOGIC;
|
||||
P_IO_UC_SLOE : inout STD_LOGIC;
|
||||
P_IO_UC_SLRD : inout STD_LOGIC;
|
||||
P_I_CLK33 : in STD_LOGIC := 'X';
|
||||
P_I_CLK66 : in STD_LOGIC := 'X';
|
||||
P_I_LEMO1 : in STD_LOGIC;
|
||||
P_O_LED1 : out STD_LOGIC;
|
||||
P_O_LED2 : out STD_LOGIC;
|
||||
P_IO_PMC_USR : inout STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
P_IO_UC_FD : inout STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
end component;
|
||||
|
||||
signal P_IO_UC_SLWR : STD_LOGIC;
|
||||
signal P_IO_UC_PKTEND : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGA : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGB : STD_LOGIC;
|
||||
signal P_IO_UC_FLAGC : STD_LOGIC;
|
||||
signal P_IO_UC_PA0 : STD_LOGIC;
|
||||
signal P_IO_UC_SLCS : STD_LOGIC;
|
||||
signal P_IO_UC_FIFOADR0 : STD_LOGIC;
|
||||
signal P_IO_UC_FIFOADR1 : STD_LOGIC;
|
||||
signal P_IO_UC_SLOE : STD_LOGIC;
|
||||
signal P_IO_UC_SLRD : STD_LOGIC;
|
||||
signal P_I_CLK33 : STD_LOGIC;
|
||||
signal P_I_CLK66 : STD_LOGIC;
|
||||
signal P_O_LED1 : STD_LOGIC;
|
||||
signal P_O_LED2 : STD_LOGIC;
|
||||
signal P_I_LEMO1 : STD_LOGIC;
|
||||
signal P_IO_PMC_USR : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal P_IO_UC_FD : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
|
||||
begin
|
||||
UUT : drs4_mezz1
|
||||
port map (
|
||||
P_IO_UC_SLWR => P_IO_UC_SLWR,
|
||||
P_IO_UC_PKTEND => P_IO_UC_PKTEND,
|
||||
P_IO_UC_FLAGA => P_IO_UC_FLAGA,
|
||||
P_IO_UC_FLAGB => P_IO_UC_FLAGB,
|
||||
P_IO_UC_FLAGC => P_IO_UC_FLAGC,
|
||||
P_IO_UC_PA0 => P_IO_UC_PA0,
|
||||
P_IO_UC_SLCS => P_IO_UC_SLCS,
|
||||
P_IO_UC_FIFOADR0 => P_IO_UC_FIFOADR0,
|
||||
P_IO_UC_FIFOADR1 => P_IO_UC_FIFOADR1,
|
||||
P_IO_UC_SLOE => P_IO_UC_SLOE,
|
||||
P_IO_UC_SLRD => P_IO_UC_SLRD,
|
||||
P_I_CLK33 => P_I_CLK33,
|
||||
P_I_CLK66 => P_I_CLK66,
|
||||
P_I_LEMO1 => P_I_LEMO1,
|
||||
P_O_LED1 => P_O_LED1,
|
||||
P_O_LED2 => P_O_LED2,
|
||||
P_IO_PMC_USR(63) => P_IO_PMC_USR(63),
|
||||
P_IO_PMC_USR(62) => P_IO_PMC_USR(62),
|
||||
P_IO_PMC_USR(61) => P_IO_PMC_USR(61),
|
||||
P_IO_PMC_USR(60) => P_IO_PMC_USR(60),
|
||||
P_IO_PMC_USR(59) => P_IO_PMC_USR(59),
|
||||
P_IO_PMC_USR(58) => P_IO_PMC_USR(58),
|
||||
P_IO_PMC_USR(57) => P_IO_PMC_USR(57),
|
||||
P_IO_PMC_USR(56) => P_IO_PMC_USR(56),
|
||||
P_IO_PMC_USR(55) => P_IO_PMC_USR(55),
|
||||
P_IO_PMC_USR(54) => P_IO_PMC_USR(54),
|
||||
P_IO_PMC_USR(53) => P_IO_PMC_USR(53),
|
||||
P_IO_PMC_USR(52) => P_IO_PMC_USR(52),
|
||||
P_IO_PMC_USR(51) => P_IO_PMC_USR(51),
|
||||
P_IO_PMC_USR(50) => P_IO_PMC_USR(50),
|
||||
P_IO_PMC_USR(49) => P_IO_PMC_USR(49),
|
||||
P_IO_PMC_USR(48) => P_IO_PMC_USR(48),
|
||||
P_IO_PMC_USR(47) => P_IO_PMC_USR(47),
|
||||
P_IO_PMC_USR(46) => P_IO_PMC_USR(46),
|
||||
P_IO_PMC_USR(45) => P_IO_PMC_USR(45),
|
||||
P_IO_PMC_USR(44) => P_IO_PMC_USR(44),
|
||||
P_IO_PMC_USR(43) => P_IO_PMC_USR(43),
|
||||
P_IO_PMC_USR(42) => P_IO_PMC_USR(42),
|
||||
P_IO_PMC_USR(41) => P_IO_PMC_USR(41),
|
||||
P_IO_PMC_USR(40) => P_IO_PMC_USR(40),
|
||||
P_IO_PMC_USR(39) => P_IO_PMC_USR(39),
|
||||
P_IO_PMC_USR(38) => P_IO_PMC_USR(38),
|
||||
P_IO_PMC_USR(37) => P_IO_PMC_USR(37),
|
||||
P_IO_PMC_USR(36) => P_IO_PMC_USR(36),
|
||||
P_IO_PMC_USR(35) => P_IO_PMC_USR(35),
|
||||
P_IO_PMC_USR(34) => P_IO_PMC_USR(34),
|
||||
P_IO_PMC_USR(33) => P_IO_PMC_USR(33),
|
||||
P_IO_PMC_USR(32) => P_IO_PMC_USR(32),
|
||||
P_IO_PMC_USR(31) => P_IO_PMC_USR(31),
|
||||
P_IO_PMC_USR(30) => P_IO_PMC_USR(30),
|
||||
P_IO_PMC_USR(29) => P_IO_PMC_USR(29),
|
||||
P_IO_PMC_USR(28) => P_IO_PMC_USR(28),
|
||||
P_IO_PMC_USR(27) => P_IO_PMC_USR(27),
|
||||
P_IO_PMC_USR(26) => P_IO_PMC_USR(26),
|
||||
P_IO_PMC_USR(25) => P_IO_PMC_USR(25),
|
||||
P_IO_PMC_USR(24) => P_IO_PMC_USR(24),
|
||||
P_IO_PMC_USR(23) => P_IO_PMC_USR(23),
|
||||
P_IO_PMC_USR(22) => P_IO_PMC_USR(22),
|
||||
P_IO_PMC_USR(21) => P_IO_PMC_USR(21),
|
||||
P_IO_PMC_USR(20) => P_IO_PMC_USR(20),
|
||||
P_IO_PMC_USR(19) => P_IO_PMC_USR(19),
|
||||
P_IO_PMC_USR(18) => P_IO_PMC_USR(18),
|
||||
P_IO_PMC_USR(17) => P_IO_PMC_USR(17),
|
||||
P_IO_PMC_USR(16) => P_IO_PMC_USR(16),
|
||||
P_IO_PMC_USR(15) => P_IO_PMC_USR(15),
|
||||
P_IO_PMC_USR(14) => P_IO_PMC_USR(14),
|
||||
P_IO_PMC_USR(13) => P_IO_PMC_USR(13),
|
||||
P_IO_PMC_USR(12) => P_IO_PMC_USR(12),
|
||||
P_IO_PMC_USR(11) => P_IO_PMC_USR(11),
|
||||
P_IO_PMC_USR(10) => P_IO_PMC_USR(10),
|
||||
P_IO_PMC_USR(9) => P_IO_PMC_USR(9),
|
||||
P_IO_PMC_USR(8) => P_IO_PMC_USR(8),
|
||||
P_IO_PMC_USR(7) => P_IO_PMC_USR(7),
|
||||
P_IO_PMC_USR(6) => P_IO_PMC_USR(6),
|
||||
P_IO_PMC_USR(5) => P_IO_PMC_USR(5),
|
||||
P_IO_PMC_USR(4) => P_IO_PMC_USR(4),
|
||||
P_IO_PMC_USR(3) => P_IO_PMC_USR(3),
|
||||
P_IO_PMC_USR(2) => P_IO_PMC_USR(2),
|
||||
P_IO_PMC_USR(1) => P_IO_PMC_USR(1),
|
||||
P_IO_PMC_USR(0) => P_IO_PMC_USR(0),
|
||||
P_IO_UC_FD(15) => P_IO_UC_FD(15),
|
||||
P_IO_UC_FD(14) => P_IO_UC_FD(14),
|
||||
P_IO_UC_FD(13) => P_IO_UC_FD(13),
|
||||
P_IO_UC_FD(12) => P_IO_UC_FD(12),
|
||||
P_IO_UC_FD(11) => P_IO_UC_FD(11),
|
||||
P_IO_UC_FD(10) => P_IO_UC_FD(10),
|
||||
P_IO_UC_FD(9) => P_IO_UC_FD(9),
|
||||
P_IO_UC_FD(8) => P_IO_UC_FD(8),
|
||||
P_IO_UC_FD(7) => P_IO_UC_FD(7),
|
||||
P_IO_UC_FD(6) => P_IO_UC_FD(6),
|
||||
P_IO_UC_FD(5) => P_IO_UC_FD(5),
|
||||
P_IO_UC_FD(4) => P_IO_UC_FD(4),
|
||||
P_IO_UC_FD(3) => P_IO_UC_FD(3),
|
||||
P_IO_UC_FD(2) => P_IO_UC_FD(2),
|
||||
P_IO_UC_FD(1) => P_IO_UC_FD(1),
|
||||
P_IO_UC_FD(0) => P_IO_UC_FD(0)
|
||||
);
|
||||
-- User: Put your stimulus here.
|
||||
|
||||
-- Clock generation
|
||||
proc_p_i_clk33_generator : process
|
||||
begin
|
||||
clock_loop : loop
|
||||
P_I_CLK33 <= '1';
|
||||
wait for 15 ns;
|
||||
P_I_CLK33 <= '0';
|
||||
wait for 15 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
proc_p_i_clk66_generator : process
|
||||
begin
|
||||
clock_loop : loop
|
||||
P_I_CLK66 <= '1';
|
||||
wait for 7.5 ns;
|
||||
P_I_CLK66 <= '0';
|
||||
wait for 7.5 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- Static signals
|
||||
P_I_LEMO1 <= '0';
|
||||
|
||||
P_IO_UC_FLAGA <= '1';
|
||||
P_IO_UC_FLAGB <= '1';
|
||||
P_IO_UC_PKTEND <= 'Z';
|
||||
P_IO_UC_PA0 <= '1';
|
||||
|
||||
-- Dynamic signals
|
||||
proc_p_io_dynamic: process
|
||||
|
||||
-- Write cycle
|
||||
-- -----------
|
||||
procedure proc_wr_cycle(
|
||||
constant I_A : in std_logic_vector(15 downto 0);
|
||||
constant I_D : in std_logic_vector(15 downto 0)
|
||||
) is
|
||||
begin
|
||||
P_IO_UC_FLAGC <= '1';
|
||||
P_IO_UC_FD <= X"0002"; -- USB2_CMD_WRITE
|
||||
wait until P_IO_UC_SLOE = '0';
|
||||
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= I_A; -- low word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= (others => '0'); -- high word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= X"0002"; -- low word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= (others => '0'); -- high word
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FD <= I_D;
|
||||
wait until P_I_CLK33 = '0';
|
||||
wait until P_I_CLK33 = '1';
|
||||
wait for 4 ns;
|
||||
|
||||
P_IO_UC_FLAGC <= '0';
|
||||
P_IO_UC_FD <= "ZZZZZZZZZZZZZZZZ"; -- tri state
|
||||
|
||||
end proc_wr_cycle;
|
||||
|
||||
begin
|
||||
|
||||
P_IO_UC_FLAGC <= '0';
|
||||
P_IO_UC_FD <= (others => '1');
|
||||
|
||||
wait for 990 ns; -- Until DLLs locked
|
||||
wait for 9.5 ns; -- Clock-to-FLAGs delay of uC
|
||||
|
||||
proc_wr_cycle(X"0016", X"0008"); -- trigger phase shift change
|
||||
|
||||
wait for 300 us;
|
||||
|
||||
-- stop simulation
|
||||
assert false
|
||||
report "Simulation Complete (this is not a failure)"
|
||||
severity failure;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end TBX_ARCH;
|
||||
|
||||
configuration TBX_CFG_drs4_mezz1_TBX_ARCH of TBX_drs4_mezz1 is
|
||||
for TBX_ARCH
|
||||
end for;
|
||||
end TBX_CFG_drs4_mezz1_TBX_ARCH;
|
||||
@@ -0,0 +1,14 @@
|
||||
vlib work
|
||||
vcom -93 -explicit ../src/drs4_pack.vhd
|
||||
vcom -93 -explicit ../src/usr_lib.vhd
|
||||
vcom -93 -explicit ../src/drs4_eval1.vhd
|
||||
vcom -93 -explicit ../src/drs4_eval1_app.vhd
|
||||
vcom -93 -explicit ../src/usb2_racc.vhd
|
||||
vcom -93 -explicit ../src/usb_dpram.vhd
|
||||
vcom -93 -explicit ../src/usr_clocks.vhd
|
||||
vcom -93 -explicit ../sim/drs4_eval1_tb.vhd
|
||||
vsim TBX_drs4_eval1 -t ps
|
||||
view wave
|
||||
source wave.do
|
||||
run 2 us
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
vlib work
|
||||
vcom -93 -explicit ../src/drs4_pack.vhd
|
||||
vcom -93 -explicit ../src/usr_lib.vhd
|
||||
vcom -93 -explicit ../src/drs4_mezz1_app.vhd
|
||||
vcom -93 -explicit ../src/usr_fpga.vhd
|
||||
vcom -93 -explicit ../src/usr_racc.vhd
|
||||
vcom -93 -explicit ../src/usr_dpram.vhd
|
||||
vcom -93 -explicit ../src/usr_clocks.vhd
|
||||
vcom -93 -explicit ../sim/usr_fpga_tb.vhd
|
||||
vsim TBX_usr_fpga -t ps
|
||||
source wave.do
|
||||
run 120 us
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
vlib work
|
||||
vcom -93 -explicit ../src/drs4_pack.vhd
|
||||
vcom -93 -explicit ../src/usr_lib.vhd
|
||||
vcom -93 -explicit ../src/drs4_mezz1.vhd
|
||||
vcom -93 -explicit ../src/drs4_mezz1_app.vhd
|
||||
vcom -93 -explicit ../src/usb2_racc.vhd
|
||||
vcom -93 -explicit ../src/usb_dpram.vhd
|
||||
vcom -93 -explicit ../src/usr_clocks.vhd
|
||||
vcom -93 -explicit ../sim/drs4_mezz1_tb.vhd
|
||||
vsim TBX_drs4_mezz1 -t ps
|
||||
view wave
|
||||
source wave.do
|
||||
run 2 us
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
vcom -93 -explicit ../2vp30/usr_fpga_timesim.vhd
|
||||
vcom -93 -explicit ../sim/usr_fpga_tb.vhd
|
||||
vsim -sdfmax /uut/=../2vp30/usr_fpga_timesim.sdf -t ps TBX_usr_fpga
|
||||
|
||||
view wave
|
||||
source wave.do
|
||||
run 4.5 us
|
||||
@@ -0,0 +1,249 @@
|
||||
-- Xilinx Testbench Template produced by program netgen G.38
|
||||
|
||||
-- ATTENTION: This file was created by netgen and may therefore be overwritten
|
||||
-- by subsequent runs of netgen. Xilinx recommends that you copy this file to
|
||||
-- a new name, or 'paste' this text into another file, to avoid accidental loss
|
||||
-- of data.
|
||||
|
||||
library IEEE;
|
||||
library WORK;
|
||||
library SIMPRIM;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use WORK.ALL;
|
||||
use SIMPRIM.VCOMPONENTS.ALL;
|
||||
use SIMPRIM.VPACKAGE.ALL;
|
||||
|
||||
entity TBX_usb1_mezz1 is
|
||||
end TBX_usb1_mezz1;
|
||||
|
||||
architecture TBX_ARCH of TBX_usb1_mezz1 is
|
||||
component usb1_mezz1
|
||||
port (
|
||||
P_I_CLK33 : in STD_LOGIC := 'X';
|
||||
P_I_UC_RD_N : in STD_LOGIC := 'X';
|
||||
P_I_UC_WR_N : in STD_LOGIC := 'X';
|
||||
P_I_UC_ALE_N : in STD_LOGIC := 'X';
|
||||
P_O_LEMO0 : out STD_LOGIC;
|
||||
P_O_LEMO1 : out STD_LOGIC;
|
||||
P_I_LEMO2 : in STD_LOGIC := 'X';
|
||||
P_I_LEMO3 : in STD_LOGIC := 'X';
|
||||
P_IO_PMC_USR : inout STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
P_IO_UC_DATA : inout STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
end component;
|
||||
|
||||
signal P_I_CLK33 : STD_LOGIC;
|
||||
signal P_I_UC_RD_N : STD_LOGIC;
|
||||
signal P_I_UC_WR_N : STD_LOGIC;
|
||||
signal P_I_UC_ALE_N : STD_LOGIC;
|
||||
signal P_O_LEMO0 : STD_LOGIC;
|
||||
signal P_O_LEMO1 : STD_LOGIC;
|
||||
signal P_I_LEMO2 : STD_LOGIC;
|
||||
signal P_I_LEMO3 : STD_LOGIC;
|
||||
signal P_IO_PMC_USR : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal P_IO_UC_DATA : STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
|
||||
begin
|
||||
UUT : usb1_mezz1
|
||||
port map (
|
||||
P_I_CLK33 => P_I_CLK33,
|
||||
P_I_UC_RD_N => P_I_UC_RD_N,
|
||||
P_I_UC_WR_N => P_I_UC_WR_N,
|
||||
P_I_UC_ALE_N => P_I_UC_ALE_N,
|
||||
P_O_LEMO0 => P_O_LEMO0,
|
||||
P_O_LEMO1 => P_O_LEMO1,
|
||||
P_I_LEMO2 => P_I_LEMO2,
|
||||
P_I_LEMO3 => P_I_LEMO3,
|
||||
P_IO_PMC_USR => P_IO_PMC_USR,
|
||||
P_IO_UC_DATA => P_IO_UC_DATA
|
||||
);
|
||||
|
||||
-- Clock generation
|
||||
-- ----------------
|
||||
proc_p_i_clk33_generator : process
|
||||
begin
|
||||
clock_loop : loop
|
||||
P_I_CLK33 <= '1';
|
||||
wait for 15 ns;
|
||||
P_I_CLK33 <= '0';
|
||||
wait for 15 ns;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- Dynamic signals
|
||||
-- ###############
|
||||
proc_p_io_dynamic: process
|
||||
|
||||
-- Address cycle
|
||||
-- -------------
|
||||
procedure proc_ad_cycle(
|
||||
constant I_A : in std_logic_vector(7 downto 0)
|
||||
) is
|
||||
begin
|
||||
P_IO_UC_DATA(7 downto 0) <= I_A;
|
||||
P_I_UC_ALE_N <= '0';
|
||||
P_I_UC_WR_N <= '0';
|
||||
wait for 200 ns;
|
||||
P_IO_UC_DATA <= (others => '0');
|
||||
P_I_UC_ALE_N <= '1';
|
||||
P_I_UC_WR_N <= '1';
|
||||
wait for 100 ns;
|
||||
end proc_ad_cycle;
|
||||
|
||||
-- Data write cycle
|
||||
-- ----------------
|
||||
procedure proc_wr_cycle
|
||||
(
|
||||
constant I_DATA : in std_logic_vector(11 downto 0)
|
||||
) is
|
||||
begin
|
||||
P_IO_UC_DATA <= I_DATA;
|
||||
P_I_UC_ALE_N <= '1';
|
||||
P_I_UC_WR_N <= '0';
|
||||
wait for 200 ns;
|
||||
P_IO_UC_DATA <= (others => '0');
|
||||
P_I_UC_ALE_N <= '1';
|
||||
P_I_UC_WR_N <= '1';
|
||||
wait for 100 ns;
|
||||
end proc_wr_cycle;
|
||||
|
||||
-- Data read cycle
|
||||
-- ---------------
|
||||
procedure proc_rd_cycle is
|
||||
begin
|
||||
P_IO_UC_DATA <= (others => 'Z');
|
||||
P_I_UC_ALE_N <= '1';
|
||||
P_I_UC_RD_N <= '0';
|
||||
wait for 200 ns;
|
||||
P_I_UC_RD_N <= '1';
|
||||
wait for 300 ns;
|
||||
end proc_rd_cycle;
|
||||
|
||||
begin
|
||||
-- Initialize signals
|
||||
P_IO_UC_DATA <= (others => '0');
|
||||
P_I_UC_RD_N <= '1';
|
||||
P_I_UC_WR_N <= '1';
|
||||
P_I_UC_ALE_N <= '1';
|
||||
|
||||
P_I_LEMO2 <= '0';
|
||||
P_I_LEMO3 <= '0';
|
||||
|
||||
P_IO_PMC_USR(41) <= '0'; -- digital trigger
|
||||
P_IO_PMC_USR(43) <= '0'; -- analog trigger
|
||||
|
||||
-- Wait for DLL lock
|
||||
-- -----------------
|
||||
wait for 32 us; -- initialization of RSR
|
||||
|
||||
-- Set-up write shift register
|
||||
--proc_ad_cycle(I_A => X"16"); -- write to 0x14 (byte swapping!)
|
||||
--proc_wr_cycle(I_DATA => X"000");
|
||||
--proc_wr_cycle(I_DATA => X"008");
|
||||
|
||||
-- Enable TCALIB
|
||||
--proc_ad_cycle(I_A => X"02");
|
||||
--proc_wr_cycle(I_DATA => X"008");
|
||||
--wait for 1000 ns;
|
||||
|
||||
-- Write DAC
|
||||
--proc_ad_cycle(I_A => X"04");
|
||||
--proc_wr_cycle(I_DATA => X"034");
|
||||
--proc_wr_cycle(I_DATA => X"012");
|
||||
|
||||
-- Set demand frequency
|
||||
--proc_ad_cycle(I_A => X"14");
|
||||
--proc_wr_cycle(I_DATA => X"03E");
|
||||
--proc_wr_cycle(I_DATA => X"001");
|
||||
|
||||
-- Set readout channels
|
||||
proc_ad_cycle(I_A => X"14");
|
||||
proc_wr_cycle(I_DATA => X"008");
|
||||
|
||||
-- Start Domino
|
||||
proc_ad_cycle(I_A => X"00");
|
||||
proc_wr_cycle(I_DATA => X"001");
|
||||
wait for 3 us;
|
||||
|
||||
-- Select long start pulse
|
||||
--proc_ad_cycle(I_A => X"02");
|
||||
--proc_wr_cycle(I_DATA => X"080");
|
||||
|
||||
-- Enable external trigger
|
||||
--proc_ad_cycle(I_A => X"02");
|
||||
--proc_wr_cycle(I_DATA => X"040");
|
||||
|
||||
-- Start Domino
|
||||
--proc_ad_cycle(I_A => X"00");
|
||||
--proc_wr_cycle(I_DATA => X"001");
|
||||
--wait for 100 ns;
|
||||
|
||||
-- Supply external trigger
|
||||
--wait for 2 us;
|
||||
--P_I_LEMO2 <= '1';
|
||||
--wait for 100 ns;
|
||||
--P_I_LEMO2 <= '0';
|
||||
|
||||
--wait for 3 us; -- wait for readout
|
||||
|
||||
-- Disable external trigger
|
||||
--proc_ad_cycle(I_A => X"02");
|
||||
--proc_wr_cycle(I_DATA => X"000");
|
||||
|
||||
-- Start Domino
|
||||
--proc_ad_cycle(I_A => X"00");
|
||||
--proc_wr_cycle(I_DATA => X"001");
|
||||
--wait for 100 ns;
|
||||
|
||||
-- Supply external trigger
|
||||
--wait for 2100 ns;
|
||||
--P_I_LEMO2 <= '1';
|
||||
--wait for 100 ns;
|
||||
--P_I_LEMO2 <= '0';
|
||||
|
||||
-- Reinit
|
||||
--proc_ad_cycle(I_A => X"00");
|
||||
--proc_wr_cycle(I_DATA => X"002");
|
||||
--wait for 1000 ns;
|
||||
|
||||
-- Start Readout
|
||||
proc_ad_cycle(I_A => X"00");
|
||||
proc_wr_cycle(I_DATA => X"004");
|
||||
|
||||
-- Trigger flash write
|
||||
--proc_ad_cycle(I_A => X"00");
|
||||
--proc_wr_cycle(I_DATA => X"008");
|
||||
|
||||
-- Write DAC
|
||||
--proc_ad_cycle(I_A => X"06");
|
||||
--proc_wr_cycle(I_DATA => X"0FF");
|
||||
--proc_wr_cycle(I_DATA => X"0FF");
|
||||
|
||||
-- Access registers/RAM
|
||||
-----------------------
|
||||
--proc_ad_cycle(I_A => "10000000");
|
||||
--proc_wr_cycle(I_DATA => "000100010001");
|
||||
--proc_wr_cycle(I_DATA => "001000100010");
|
||||
--proc_wr_cycle(I_DATA => "010001000100");
|
||||
--proc_wr_cycle(I_DATA => "100010001000");
|
||||
|
||||
--proc_ad_cycle(I_A => "10000000");
|
||||
--proc_rd_cycle;
|
||||
--proc_rd_cycle;
|
||||
--proc_rd_cycle;
|
||||
--proc_rd_cycle;
|
||||
|
||||
wait for 400 us;
|
||||
-- stop simulation
|
||||
assert false
|
||||
report "Simulation Complete (this is not a failure)"
|
||||
severity failure;
|
||||
|
||||
end process;
|
||||
|
||||
end TBX_ARCH;
|
||||
|
||||
configuration TBX_CFG_usb1_mezz1_TBX_ARCH of TBX_usb1_mezz1 is
|
||||
for TBX_ARCH
|
||||
end for;
|
||||
end TBX_CFG_usb1_mezz1_TBX_ARCH;
|
||||
@@ -0,0 +1,14 @@
|
||||
vlib work
|
||||
vcom -93 -explicit ../src/drs3_pack.vhd
|
||||
vcom -93 -explicit ../src/usr_lib.vhd
|
||||
vcom -93 -explicit ../src/drs3_cmc3.vhd
|
||||
vcom -93 -explicit ../src/usb_racc.vhd
|
||||
vcom -93 -explicit ../src/usb_dpram.vhd
|
||||
vcom -93 -explicit ../src/usr_clocks.vhd
|
||||
vcom -93 -explicit ../src/usb_mezz3.vhd
|
||||
vcom -93 -explicit ../sim/usb_mezz3_tb.vhd
|
||||
vsim TBX_usb_mezz3 -t ps
|
||||
view wave
|
||||
source wave.do
|
||||
run 20 us
|
||||
|
||||
@@ -0,0 +1,404 @@
|
||||
;
|
||||
; Copyright Model Technology, a Mentor Graphics Corporation company 2003,
|
||||
; All rights reserved.
|
||||
;
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
|
||||
work = work
|
||||
UNISIM = c:\Modeltech\xilinx_ise_actual\unisim
|
||||
UNISIMS_VER = c:\Modeltech\xilinx_ise_actual\unisims_ver
|
||||
XILINXCORELIB = c:\Modeltech\xilinx_ise_actual\XilinxCoreLib
|
||||
XILINXCORELIB_VER = c:\Modeltech\xilinx_ise_actual\XilinxCoreLib_ver
|
||||
UNI9000_VER = c:\Modeltech\xilinx_ise_actual\uni9000_ver
|
||||
SIMPRIMS_VER = c:\Modeltech\xilinx_ise_actual\simprims_ver
|
||||
SIMPRIM = c:\Modeltech\xilinx_ise_actual\simprim
|
||||
PLS = c:\Modeltech\xilinx_ise_actual\abel\pls
|
||||
CPLD_VER = c:\Modeltech\xilinx_ise_actual\cpld_ver
|
||||
CPLD = c:\Modeltech\xilinx_ise_actual\cpld
|
||||
AIM_VER = c:\Modeltech\xilinx_ise_actual\abel_ver\aim_ver
|
||||
AIM = c:\Modeltech\xilinx_ise_actual\abel\aim
|
||||
[vcom]
|
||||
; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
|
||||
; VHDL93 = 1
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explict enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = false
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Treat as errors:
|
||||
; case statement static warnings
|
||||
; warnings caused by aggregates that are not locally static
|
||||
; Overrides NoCaseStaticError, NoOthersStaticError settings.
|
||||
; PedanticErrors = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn on `protect compiler directive processing.
|
||||
; Default is to ignore `protect directives.
|
||||
; Protect = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn on bad option warning. Default is off.
|
||||
; Show_BadOptionWarning = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
resolution = 1ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = ns
|
||||
|
||||
; Default run length
|
||||
RunLength = 100 us
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directives to license manager can be set either as single value or as
|
||||
; space separated multi-values:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license is not available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license (PE ONLY)
|
||||
; Single value:
|
||||
; License = plus
|
||||
; Multi-value:
|
||||
; License = noqueue plus
|
||||
|
||||
; Stop the simulator after an assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %i - Instance pathname with process
|
||||
; %O - Process name
|
||||
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
|
||||
; %P - Instance or Region path without leaf process
|
||||
; %F - File
|
||||
; %L - Line number of assertion or, if assertion is in a subprogram, line
|
||||
; from which the call is made
|
||||
; %% - Print '%' character
|
||||
; If specific format for assertion level is defined, use its format.
|
||||
; If specific format is not define for assertion level, use AssertionFormatBreak
|
||||
; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
|
||||
; otherwise use AssertionFormat.
|
||||
;
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
|
||||
|
||||
; Assertion File - alternate file for storing assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands.
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example: sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, or deposit
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control number of VHDL files open concurrently
|
||||
; This number should always be less than the
|
||||
; current ulimit setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the waveform window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of a generate statement label. Do not quote it.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (log only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
[lmc]
|
||||
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
|
||||
libsm = $MODEL_TECH/libsm.sl
|
||||
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libsm = $MODEL_TECH/libsm.dll
|
||||
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
||||
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
||||
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
||||
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
||||
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
||||
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
||||
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
||||
; Logic Modeling's SmartModel SWIFT software (Linux)
|
||||
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
|
||||
|
||||
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
|
||||
libhm = $MODEL_TECH/libhm.sl
|
||||
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
||||
; libhm = $MODEL_TECH/libhm.dll
|
||||
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
||||
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
|
||||
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
||||
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
|
||||
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
||||
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
|
||||
; Logic Modeling's hardware modeler SFI software (Windows NT)
|
||||
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
|
||||
; Logic Modeling's hardware modeler SFI software (Linux)
|
||||
; libsfi = <sfi_dir>/lib/linux/libsfi.so
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
Project_Major_Version = 6
|
||||
Project_Minor_Version = 6
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,453 @@
|
||||
--#############################################################
|
||||
-- Author : Stefan Ritt
|
||||
-- Contents : DRS4 Evaluation Board FPGA top level entity
|
||||
-- $Id: drs4_eval5.vhd 21305 2014-04-11 12:58:35Z ritt $
|
||||
--#############################################################
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use work.drs4_pack.all;
|
||||
|
||||
entity drs4_eval5 is
|
||||
port (
|
||||
-- quartz
|
||||
P_I_CLK33 : in std_logic;
|
||||
P_I_CLK66 : in std_logic;
|
||||
|
||||
-- timing calibration
|
||||
P_O_CAL : out std_logic;
|
||||
P_O_TCA_CTRL : out std_logic;
|
||||
|
||||
-- test points
|
||||
P_IO_J42 : inout std_logic;
|
||||
P_IO_J43 : inout std_logic;
|
||||
P_IO_T19 : inout std_logic;
|
||||
P_IO_T20 : inout std_logic;
|
||||
|
||||
-- configuration pin
|
||||
P_I_J44 : in std_logic;
|
||||
|
||||
-- analog triggers
|
||||
P_I_ATRG1 : in std_logic;
|
||||
P_I_ATRG2 : in std_logic;
|
||||
P_I_ATRG3 : in std_logic;
|
||||
P_I_ATRG4 : in std_logic;
|
||||
|
||||
-- external trigger
|
||||
P_IO_ETRG_IN : inout std_logic;
|
||||
P_O_ETRG_IND : out std_logic;
|
||||
|
||||
P_IO_ETRG_OUT : inout std_logic;
|
||||
P_O_ETRG_OUTD : out std_logic;
|
||||
|
||||
-- external (MMCX clock) clock
|
||||
P_IO_ECLK_IN : inout std_logic;
|
||||
P_O_ECLK_IND : out std_logic;
|
||||
P_IO_ECLK_OUT : inout std_logic;
|
||||
P_O_ECLK_OUTD : out std_logic;
|
||||
|
||||
-- LEDs
|
||||
P_O_LED_GREEN : out std_logic;
|
||||
P_O_LED_YELLOW : out std_logic;
|
||||
|
||||
-- Lines to/from Cy7C68013A microcontroller
|
||||
P_IO_UC_SLOE : inout std_logic;
|
||||
P_IO_UC_SLRD : inout std_logic;
|
||||
P_IO_UC_SLWR : inout std_logic;
|
||||
P_IO_UC_SLCS : inout std_logic;
|
||||
P_IO_UC_PKTEND : inout std_logic;
|
||||
P_IO_UC_FIFOADR0 : inout std_logic;
|
||||
P_IO_UC_FIFOADR1 : inout std_logic;
|
||||
P_IO_UC_FLAGA : inout std_logic;
|
||||
P_IO_UC_FLAGB : inout std_logic;
|
||||
P_IO_UC_FLAGC : inout std_logic;
|
||||
P_I_UC_PA0 : in std_logic;
|
||||
|
||||
P_IO_UC_FD : inout std_logic_vector(15 downto 0);
|
||||
|
||||
-- PMC connector
|
||||
P_IO_PMC_USR : inout std_logic_vector(63 downto 0)
|
||||
);
|
||||
end drs4_eval5;
|
||||
|
||||
architecture arch of drs4_eval5 is
|
||||
|
||||
component usr_clocks
|
||||
port (
|
||||
P_I_CLK33 : in std_logic;
|
||||
P_I_CLK66 : in std_logic;
|
||||
O_CLK33 : out std_logic;
|
||||
O_CLK33_NODLL : out std_logic;
|
||||
O_CLK66 : out std_logic;
|
||||
O_CLK132 : out std_logic;
|
||||
O_CLK264 : out std_logic;
|
||||
I_PS_VALUE : in std_logic_vector(7 downto 0);
|
||||
O_CLK_PS : out std_logic;
|
||||
O_LOCKED : out std_logic;
|
||||
|
||||
O_DEBUG1 : out std_logic;
|
||||
O_DEBUG2 : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component usb2_racc is
|
||||
port (
|
||||
-- Clock signals
|
||||
-- ------------------------
|
||||
I_RESET : in std_logic;
|
||||
I_CLK33 : in std_logic;
|
||||
|
||||
-- Lines to/from Cy7C68013A microcontroller
|
||||
-- -----------------------------------
|
||||
P_IO_UC_SLOE : inout std_logic;
|
||||
P_IO_UC_SLRD : inout std_logic;
|
||||
P_IO_UC_SLWR : inout std_logic;
|
||||
P_IO_UC_SLCS : inout std_logic;
|
||||
P_IO_UC_PKTEND : inout std_logic;
|
||||
P_IO_UC_FIFOADR0 : inout std_logic;
|
||||
P_IO_UC_FIFOADR1 : inout std_logic;
|
||||
P_IO_UC_FLAGA : inout std_logic;
|
||||
P_IO_UC_FLAGB : inout std_logic;
|
||||
P_IO_UC_FLAGC : inout std_logic;
|
||||
P_IO_UC_FD : inout std_logic_vector(15 downto 0);
|
||||
|
||||
-- Simple bus interface to on-chip RAM
|
||||
-- --------------------------------------------------
|
||||
O_LOCBUS_ADDR : out std_logic_vector(31 downto 0);
|
||||
I_LOCBUS_D_RD : in std_logic_vector(31 downto 0);
|
||||
O_LOCBUS_D_WR : out std_logic_vector(31 downto 0);
|
||||
O_LOCBUS_WE : out std_logic;
|
||||
|
||||
-- Status & control registers
|
||||
-----------------------------
|
||||
O_CONTROL_REG_ARR : out type_control_reg_arr;
|
||||
I_STATUS_REG_ARR : in type_status_reg_arr;
|
||||
|
||||
O_CONTROL_TRIG_ARR : out type_control_trig_arr;
|
||||
O_CONTROL0_BIT_TRIG_ARR : out std_logic_vector(31 downto 0);
|
||||
|
||||
-- Debug signals
|
||||
-- -------------
|
||||
O_DEBUG : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component usb_dpram is
|
||||
port (
|
||||
I_RESET : in std_logic;
|
||||
|
||||
I_CLK_A : in std_logic;
|
||||
I_ADDR_A : in std_logic_vector(31 downto 0);
|
||||
I_WE_A : in std_logic;
|
||||
O_D_RD_A : out std_logic_vector(31 downto 0);
|
||||
I_D_WR_A : in std_logic_vector(31 downto 0);
|
||||
|
||||
I_CLK_B : in std_logic;
|
||||
I_ADDR_B : in std_logic_vector(31 downto 0);
|
||||
I_WE_B : in std_logic;
|
||||
O_D_RD_B : out std_logic_vector(31 downto 0);
|
||||
I_D_WR_B : in std_logic_vector(31 downto 0)
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component drs4_eval5_app is
|
||||
port (
|
||||
-- clocks
|
||||
I_CLK33 : in std_logic; -- 33 MHz, sychronised to clk33_nodll
|
||||
I_CLK66 : in std_logic; -- 66 MHz, same phase as clk33
|
||||
I_CLK132 : in std_logic; -- 132 MHz, random phase in respect to clk33
|
||||
I_CLK264 : in std_logic; -- 264 MHz, random phase in respect to clk33
|
||||
O_CLK_PS_VALUE : out std_logic_vector(7 downto 0); -- value for phase shift
|
||||
I_CLK_PS : in std_logic; -- phase shifted in respect to clk33
|
||||
I_RESET : in std_logic; -- active high power-up reset
|
||||
|
||||
-- timing calibration
|
||||
O_CAL : out std_logic;
|
||||
O_TCA_CTRL : out std_logic;
|
||||
|
||||
-- analog triggers
|
||||
I_ANA_TRG : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- external trigger
|
||||
IO_ETRG_IN : inout std_logic;
|
||||
O_ETRG_IND : out std_logic;
|
||||
|
||||
IO_ETRG_OUT : inout std_logic;
|
||||
O_ETRG_OUTD : out std_logic;
|
||||
|
||||
-- external (MMCX clock) clock
|
||||
IO_ECLK_OUT : inout std_logic;
|
||||
IO_ECLK_IN : inout std_logic;
|
||||
|
||||
-- J44 pin configuration
|
||||
I_CONFIG_PIN : in std_logic;
|
||||
|
||||
-- PMC
|
||||
P_IO_PMC_USR : inout std_logic_vector(63 downto 0);
|
||||
|
||||
-- Simple bus interface to DPRAM
|
||||
O_DPRAM_CLK : out std_logic;
|
||||
O_DPRAM_ADDR : out std_logic_vector(31 downto 0);
|
||||
O_DPRAM_D_WR : out std_logic_vector(31 downto 0);
|
||||
O_DPRAM_WE : out std_logic;
|
||||
I_DPRAM_D_RD : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- Control & status registers from system FPGA interface
|
||||
I_CONTROL_REG_ARR : in type_control_reg_arr;
|
||||
O_STATUS_REG_ARR : out type_status_reg_arr;
|
||||
I_CONTROL_TRIG_ARR : in type_control_trig_arr;
|
||||
I_CONTROL0_BIT_TRIG_ARR : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- LEDs signals
|
||||
O_LED_GREEN : out std_logic;
|
||||
O_LED_YELLOW : out std_logic;
|
||||
|
||||
-- Debug signals
|
||||
O_DEBUG1 : out std_logic;
|
||||
O_DEBUG2 : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal VCC: std_logic;
|
||||
signal GND: std_logic;
|
||||
|
||||
-- reset signal
|
||||
-- -------------
|
||||
signal global_reset : std_logic; -- active high power-up reset
|
||||
|
||||
-- clocks & related signals
|
||||
-- ------------------------
|
||||
signal clk33_nodll : std_logic; -- external 33 MHz clock (global clock net)
|
||||
signal clk33 : std_logic; -- 33 MHz DLL output
|
||||
signal clk66 : std_logic;
|
||||
signal clk132 : std_logic;
|
||||
signal clk264 : std_logic;
|
||||
signal clk_ps_value : std_logic_vector(7 downto 0);
|
||||
signal clk_ps : std_logic; -- special phase shifted clock
|
||||
signal usr_clks_dlls_locked : std_logic; -- high if clock DLLs for clkxx have locked
|
||||
|
||||
-- calibration
|
||||
-- -----------
|
||||
signal o_cal : std_logic;
|
||||
signal o_tca_ctrl : std_logic;
|
||||
|
||||
-- user application signals for Locbus interface
|
||||
-- ---------------------------------------------
|
||||
signal locbus_addr : std_logic_vector(31 downto 0);
|
||||
signal locbus_d_rd : std_logic_vector(31 downto 0);
|
||||
signal locbus_d_wr : std_logic_vector(31 downto 0);
|
||||
signal locbus_we : std_logic;
|
||||
|
||||
-- user application signals for DPRAM interface
|
||||
-- --------------------------------------------
|
||||
signal dpram_clk : std_logic;
|
||||
signal dpram_addr : std_logic_vector(31 downto 0);
|
||||
signal dpram_we : std_logic;
|
||||
signal dpram_d_wr : std_logic_vector(31 downto 0);
|
||||
signal dpram_d_rd : std_logic_vector(31 downto 0);
|
||||
|
||||
-- register signals for data exchange with microcontroller
|
||||
-- -------------------------------------------------------
|
||||
signal control_reg_arr : type_control_reg_arr;
|
||||
signal status_reg_arr : type_status_reg_arr;
|
||||
|
||||
signal control_trig_arr: type_control_trig_arr;
|
||||
signal control0_bit_trig_arr : std_logic_vector(31 downto 0);
|
||||
|
||||
-- LEDs
|
||||
-- ----
|
||||
signal o_led_green : std_logic;
|
||||
signal o_led_yellow : std_logic;
|
||||
|
||||
-- Config
|
||||
-- ------
|
||||
signal i_cfg_pin : std_logic;
|
||||
|
||||
-- Trigger
|
||||
-- -------
|
||||
signal io_etrg_in : std_logic;
|
||||
signal o_etrg_ind : std_logic;
|
||||
signal io_etrg_out : std_logic;
|
||||
signal o_etrg_outd : std_logic;
|
||||
signal i_ana_trg : std_logic_vector(3 downto 0);
|
||||
signal io_eclk_out : std_logic;
|
||||
signal io_eclk_in : std_logic;
|
||||
|
||||
-- Debugging signals
|
||||
-- -----------------
|
||||
signal o_racc_debug : std_logic;
|
||||
signal o_debug1 : std_logic;
|
||||
signal o_debug2 : std_logic;
|
||||
|
||||
begin
|
||||
VCC <= '1';
|
||||
GND <= '0';
|
||||
|
||||
-- map LEDs
|
||||
P_O_LED_GREEN <= o_led_green;
|
||||
P_O_LED_YELLOW <= o_led_yellow;
|
||||
|
||||
-- debug outputs
|
||||
P_IO_J42 <= GND;
|
||||
P_IO_J43 <= GND;
|
||||
P_IO_T19 <= o_debug1;
|
||||
P_IO_T20 <= o_debug2;
|
||||
|
||||
-- triggers
|
||||
i_ana_trg(0) <= P_I_ATRG1;
|
||||
i_ana_trg(1) <= P_I_ATRG2;
|
||||
i_ana_trg(2) <= P_I_ATRG3;
|
||||
i_ana_trg(3) <= P_I_ATRG4;
|
||||
|
||||
io_etrg_in <= P_IO_ETRG_IN;
|
||||
P_O_ETRG_IND <= o_etrg_ind;
|
||||
P_IO_ETRG_OUT <= io_etrg_out;
|
||||
P_O_ETRG_OUTD <= o_etrg_outd;
|
||||
|
||||
i_cfg_pin <= P_I_J44;
|
||||
|
||||
-- external clock
|
||||
P_IO_ECLK_OUT <= io_eclk_out;
|
||||
P_O_ECLK_OUTD <= '1';
|
||||
io_eclk_in <= P_IO_ECLK_IN;
|
||||
P_O_ECLK_IND <= '0';
|
||||
|
||||
-- calibration
|
||||
P_O_CAL <= o_cal;
|
||||
P_O_TCA_CTRL <= o_tca_ctrl;
|
||||
|
||||
clocks : usr_clocks port map (
|
||||
P_I_CLK33 => P_I_CLK33,
|
||||
P_I_CLK66 => P_I_CLK66,
|
||||
O_CLK33 => clk33,
|
||||
O_CLK33_NODLL => clk33_nodll,
|
||||
O_CLK66 => clk66,
|
||||
O_CLK132 => clk132,
|
||||
O_CLK264 => clk264,
|
||||
I_PS_VALUE => clk_ps_value,
|
||||
O_CLK_PS => clk_ps,
|
||||
O_LOCKED => usr_clks_dlls_locked,
|
||||
|
||||
O_DEBUG1 => open,
|
||||
O_DEBUG2 => open
|
||||
);
|
||||
|
||||
-- global system FPGA reset (synchronous): Assert reset until DLL
|
||||
-- for clock DLLs have locked
|
||||
proc_reset: process(clk33_nodll, usr_clks_dlls_locked)
|
||||
begin
|
||||
if (usr_clks_dlls_locked = '0') then
|
||||
global_reset <= '1';
|
||||
elsif rising_edge(clk33_nodll) then
|
||||
if (P_I_UC_PA0 = '0') then -- reset with uC PA0 line
|
||||
global_reset <= '1';
|
||||
else
|
||||
global_reset <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- interface to status & control registers
|
||||
-- ---------------------------------------
|
||||
usb2_racc_interface: usb2_racc
|
||||
port map (
|
||||
I_RESET => global_reset,
|
||||
I_CLK33 => clk33,
|
||||
|
||||
P_IO_UC_SLOE => P_IO_UC_SLOE,
|
||||
P_IO_UC_SLRD => P_IO_UC_SLRD,
|
||||
P_IO_UC_SLWR => P_IO_UC_SLWR,
|
||||
P_IO_UC_SLCS => P_IO_UC_SLCS,
|
||||
P_IO_UC_PKTEND => P_IO_UC_PKTEND,
|
||||
P_IO_UC_FIFOADR0 => P_IO_UC_FIFOADR0,
|
||||
P_IO_UC_FIFOADR1 => P_IO_UC_FIFOADR1,
|
||||
P_IO_UC_FLAGA => P_IO_UC_FLAGA,
|
||||
P_IO_UC_FLAGB => P_IO_UC_FLAGB,
|
||||
P_IO_UC_FLAGC => P_IO_UC_FLAGC,
|
||||
P_IO_UC_FD => P_IO_UC_FD,
|
||||
|
||||
O_LOCBUS_ADDR => locbus_addr,
|
||||
I_LOCBUS_D_RD => locbus_d_rd,
|
||||
O_LOCBUS_D_WR => locbus_d_wr,
|
||||
O_LOCBUS_WE => locbus_we,
|
||||
|
||||
O_CONTROL_REG_ARR => control_reg_arr,
|
||||
I_STATUS_REG_ARR => status_reg_arr,
|
||||
|
||||
O_CONTROL_TRIG_ARR => control_trig_arr,
|
||||
O_CONTROL0_BIT_TRIG_ARR => control0_bit_trig_arr,
|
||||
|
||||
O_DEBUG => o_racc_debug
|
||||
);
|
||||
|
||||
-- DPRAM (FIFO) for waveform storage
|
||||
-- ---------------------------------
|
||||
drs_dpram : usb_dpram
|
||||
port map (
|
||||
I_RESET => global_reset,
|
||||
|
||||
I_CLK_A => clk66,
|
||||
I_ADDR_A => locbus_addr,
|
||||
I_WE_A => locbus_we,
|
||||
O_D_RD_A => locbus_d_rd,
|
||||
I_D_WR_A => locbus_d_wr,
|
||||
|
||||
I_CLK_B => dpram_clk,
|
||||
I_ADDR_B => dpram_addr,
|
||||
I_WE_B => dpram_we,
|
||||
O_D_RD_B => dpram_d_rd,
|
||||
I_D_WR_B => dpram_d_wr
|
||||
|
||||
);
|
||||
|
||||
-- user PMC application
|
||||
-- --------------------
|
||||
app : drs4_eval5_app
|
||||
port map (
|
||||
I_RESET => global_reset,
|
||||
I_CLK33 => clk33,
|
||||
I_CLK66 => clk66,
|
||||
I_CLK132 => clk132,
|
||||
I_CLK264 => clk264,
|
||||
O_CLK_PS_VALUE => clk_ps_value,
|
||||
I_CLK_PS => clk_ps,
|
||||
|
||||
O_CAL => o_cal,
|
||||
O_TCA_CTRL => o_tca_ctrl,
|
||||
|
||||
IO_ETRG_IN => io_etrg_in,
|
||||
O_ETRG_IND => o_etrg_ind,
|
||||
IO_ETRG_OUT => io_etrg_out,
|
||||
O_ETRG_OUTD => o_etrg_outd,
|
||||
I_ANA_TRG => i_ana_trg,
|
||||
|
||||
IO_ECLK_OUT => io_eclk_out,
|
||||
IO_ECLK_IN => io_eclk_in,
|
||||
|
||||
I_CONFIG_PIN => i_cfg_pin,
|
||||
|
||||
P_IO_PMC_USR => P_IO_PMC_USR,
|
||||
|
||||
O_DPRAM_CLK => dpram_clk,
|
||||
O_DPRAM_ADDR => dpram_addr,
|
||||
O_DPRAM_D_WR => dpram_d_wr,
|
||||
O_DPRAM_WE => dpram_we,
|
||||
I_DPRAM_D_RD => dpram_d_rd,
|
||||
|
||||
I_CONTROL_REG_ARR => control_reg_arr,
|
||||
O_STATUS_REG_ARR => status_reg_arr,
|
||||
|
||||
I_CONTROL_TRIG_ARR => control_trig_arr,
|
||||
I_CONTROL0_BIT_TRIG_ARR => control0_bit_trig_arr,
|
||||
|
||||
O_LED_GREEN => o_led_green,
|
||||
O_LED_YELLOW => o_led_yellow,
|
||||
|
||||
O_DEBUG1 => o_debug1,
|
||||
O_DEBUG2 => o_debug2
|
||||
);
|
||||
|
||||
end arch;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
--#############################################################
|
||||
-- Author : Boris Keil, Stefan Ritt
|
||||
-- Contents : Status and control register definition for drs2_cmc2
|
||||
-- $Id$
|
||||
--#############################################################
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
|
||||
package drs4_pack is
|
||||
|
||||
-- Constant definitions
|
||||
-- ####################
|
||||
constant const_no_of_control_reg_addr_bits : integer := 4;
|
||||
constant const_no_of_status_reg_addr_bits : integer := 4;
|
||||
constant const_pmc1_pmc2_diff_bit: integer := 19;
|
||||
|
||||
-- number of control registers
|
||||
constant const_no_of_control_regs: integer := (2**(const_no_of_control_reg_addr_bits));
|
||||
-- number of status registers
|
||||
constant const_no_of_status_regs: integer := (2**(const_no_of_status_reg_addr_bits));
|
||||
-- Register width. Do not modify.
|
||||
constant const_reg_width: integer := 32;
|
||||
|
||||
-- reinit bit in control register #0
|
||||
constant const_reinit_bit: integer := 1;
|
||||
|
||||
-- size of DPRAM per PMC minus 4
|
||||
constant const_dpram_size_m4: std_logic_vector(31 downto 0) := X"0000_9FFC"; -- 10 channels @ 1024 samples @ 2x12bits
|
||||
--constant const_dpram_size_m4: std_logic_vector(31 downto 0) := X"0000_0008"; -- for simulation
|
||||
|
||||
-- Type definitions
|
||||
-- ################
|
||||
subtype type_reg is std_logic_vector(31 downto 0);
|
||||
type type_control_reg_arr is array (const_no_of_control_regs - 1 downto 0) of type_reg;
|
||||
type type_status_reg_arr is array (const_no_of_status_regs - 1 downto 0) of type_reg;
|
||||
subtype type_control_reg_no is integer range 0 to (const_no_of_control_regs - 1);
|
||||
subtype type_status_reg_no is integer range 0 to (const_no_of_status_regs - 1);
|
||||
type type_control_trig_arr is array (const_no_of_control_regs - 1 downto 0) of std_logic_vector(3 downto 0);
|
||||
|
||||
end drs4_pack;
|
||||
@@ -0,0 +1 @@
|
||||
@..\..\revision_convert\Debug\revision_convert drs3_cmc1.vhd
|
||||
@@ -0,0 +1,498 @@
|
||||
--#############################################################
|
||||
-- Author : Stefan Ritt
|
||||
-- Contents : Register & FIFO Access through Cy7C68013A uC
|
||||
-- $Id: usb2_racc.vhd 6983 2007-03-12 09:26:06Z ritt $
|
||||
--#############################################################
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use work.drs4_pack.all;
|
||||
|
||||
entity usb2_racc is
|
||||
port (
|
||||
I_RESET : in std_logic;
|
||||
I_CLK33 : in std_logic;
|
||||
|
||||
-- Lines to from C8051 microcontroller
|
||||
-- -----------------------------------
|
||||
P_IO_UC_SLOE : inout std_logic;
|
||||
P_IO_UC_SLRD : inout std_logic;
|
||||
P_IO_UC_SLWR : inout std_logic;
|
||||
P_IO_UC_SLCS : inout std_logic;
|
||||
P_IO_UC_PKTEND : inout std_logic;
|
||||
P_IO_UC_FIFOADR0 : inout std_logic;
|
||||
P_IO_UC_FIFOADR1 : inout std_logic;
|
||||
P_IO_UC_FLAGA : inout std_logic;
|
||||
P_IO_UC_FLAGB : inout std_logic;
|
||||
P_IO_UC_FLAGC : inout std_logic;
|
||||
P_IO_UC_FD : inout std_logic_vector(15 downto 0);
|
||||
|
||||
-- Simple bus interface to on-chip RAM
|
||||
-- --------------------------------------------------
|
||||
O_LOCBUS_ADDR : out std_logic_vector(31 downto 0);
|
||||
I_LOCBUS_D_RD : in std_logic_vector(31 downto 0);
|
||||
O_LOCBUS_D_WR : out std_logic_vector(31 downto 0);
|
||||
O_LOCBUS_WE : out std_logic;
|
||||
|
||||
-- Status & control registers
|
||||
-- --------------------------
|
||||
O_CONTROL_REG_ARR : out type_control_reg_arr;
|
||||
I_STATUS_REG_ARR : in type_status_reg_arr;
|
||||
|
||||
O_CONTROL_TRIG_ARR : out type_control_trig_arr;
|
||||
O_CONTROL0_BIT_TRIG_ARR : out std_logic_vector(31 downto 0);
|
||||
|
||||
-- Debug signal
|
||||
-- ------------
|
||||
O_DEBUG : out std_logic
|
||||
);
|
||||
end usb2_racc;
|
||||
|
||||
architecture arch of usb2_racc is
|
||||
|
||||
-- I/O pad tri-state flip-flops
|
||||
component USR_LIB_VEC_IOFD_CPE_NALL
|
||||
generic (
|
||||
width : integer := 1;
|
||||
init_val_to_pad : string := "0";
|
||||
init_val_from_pad : string := "0"
|
||||
);
|
||||
port (
|
||||
O_C : in std_logic_vector (width-1 downto 0);
|
||||
O_CE : in std_logic_vector (width-1 downto 0);
|
||||
O_CLR : in std_logic_vector (width-1 downto 0);
|
||||
O_PRE : in std_logic_vector (width-1 downto 0);
|
||||
O : out std_logic_vector (width-1 downto 0);
|
||||
|
||||
I_C : in std_logic_vector (width-1 downto 0);
|
||||
I_CE : in std_logic_vector (width-1 downto 0);
|
||||
I_CLR : in std_logic_vector (width-1 downto 0);
|
||||
I_PRE : in std_logic_vector (width-1 downto 0);
|
||||
I : in std_logic_vector (width-1 downto 0);
|
||||
|
||||
IO : inout std_logic_vector (width-1 downto 0);
|
||||
T : in std_logic_vector (width-1 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
-- UC I/O pin control signals
|
||||
signal uc_o : std_logic_vector(25 downto 0); -- output FF data
|
||||
signal uc_i : std_logic_vector(25 downto 0); -- input FF data
|
||||
signal uc_clk_i : std_logic_vector(25 downto 0); -- input FF clock
|
||||
signal uc_clr_i : std_logic_vector(25 downto 0); -- input FF async clear
|
||||
signal uc_ce_i : std_logic_vector(25 downto 0); -- input FF clock enable
|
||||
signal uc_pre_i : std_logic_vector(25 downto 0); -- input FF async preset
|
||||
signal uc_clk_o : std_logic_vector(25 downto 0); -- output FF clock
|
||||
signal uc_ce_o : std_logic_vector(25 downto 0); -- output FF clock enable
|
||||
signal uc_clr_o : std_logic_vector(25 downto 0); -- output FF async clear
|
||||
signal uc_pre_o : std_logic_vector(25 downto 0); -- output FF async preset
|
||||
signal uc_ts : std_logic_vector(25 downto 0); -- output FF 3state
|
||||
|
||||
-- internal control/status registers
|
||||
subtype type_byte_sel is integer range 0 to 3;
|
||||
subtype type_pkt_size is integer range 0 to 256;
|
||||
signal control_reg_arr : type_control_reg_arr;
|
||||
signal status_reg_arr : type_status_reg_arr;
|
||||
signal control_reg_no : type_control_reg_no;
|
||||
signal status_reg_no : type_status_reg_no;
|
||||
signal usrbus_byte_sel : type_byte_sel;
|
||||
signal usrbus_pkt_size : type_pkt_size;
|
||||
signal usrbus_status_sel : std_logic;
|
||||
signal usrbus_ram_sel : std_logic;
|
||||
signal usrbus_size : std_logic_vector(31 downto 0);
|
||||
signal locbus_addr : std_logic_vector(31 downto 0);
|
||||
|
||||
-- microcontroller interface signals
|
||||
type type_uc_state is (idle, oe1, oe2, cmd, adr0, adr1, size0, size1,
|
||||
write_word, read_word, read_ram,
|
||||
read_pause1, read_pause2, read_pause3, read_pause4,
|
||||
read_end1, read_end2, read_end3);
|
||||
type type_uc_cmd is (cmd_read, cmd_write);
|
||||
|
||||
signal uc_state : type_uc_state;
|
||||
signal uc_cmd : type_uc_cmd;
|
||||
signal uc_data_i : std_logic_vector(15 downto 0);
|
||||
signal uc_data_o : std_logic_vector(15 downto 0);
|
||||
signal uc_pktend : std_logic;
|
||||
signal uc_flaga : std_logic;
|
||||
signal uc_flagb : std_logic;
|
||||
signal uc_flagc : std_logic;
|
||||
signal uc_fdts : std_logic;
|
||||
signal uc_fdts_pl : std_logic;
|
||||
signal uc_slcs : std_logic;
|
||||
signal uc_fifoadr0 : std_logic;
|
||||
signal uc_fifoadr1 : std_logic;
|
||||
signal uc_sloe : std_logic;
|
||||
signal uc_slrd : std_logic;
|
||||
signal uc_slwr : std_logic;
|
||||
|
||||
signal debug : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
O_CONTROL_REG_ARR <= control_reg_arr;
|
||||
status_reg_arr <= I_STATUS_REG_ARR;
|
||||
O_DEBUG <= debug;
|
||||
|
||||
uc_iofds_inst : USR_LIB_VEC_IOFD_CPE_NALL
|
||||
generic map (
|
||||
width => 26,
|
||||
init_val_to_pad => "1",
|
||||
init_val_from_pad => "1"
|
||||
)
|
||||
port map (
|
||||
O_C => uc_clk_i(25 downto 0),
|
||||
O_CE => uc_ce_i(25 downto 0),
|
||||
O_CLR => uc_clr_i(25 downto 0),
|
||||
O_PRE => uc_pre_i(25 downto 0),
|
||||
O => uc_i(25 downto 0),
|
||||
I_C => uc_clk_o(25 downto 0),
|
||||
I_CE => uc_ce_o(25 downto 0),
|
||||
I_CLR => uc_clr_o(25 downto 0),
|
||||
I_PRE => uc_pre_o(25 downto 0),
|
||||
I => uc_o(25 downto 0),
|
||||
IO(15 downto 0) => P_IO_UC_FD(15 downto 0),
|
||||
IO(16) => P_IO_UC_PKTEND,
|
||||
IO(17) => P_IO_UC_SLOE,
|
||||
IO(18) => P_IO_UC_SLRD,
|
||||
IO(19) => P_IO_UC_SLWR,
|
||||
IO(20) => P_IO_UC_SLCS,
|
||||
IO(21) => P_IO_UC_FIFOADR0,
|
||||
IO(22) => P_IO_UC_FIFOADR1,
|
||||
IO(23) => P_IO_UC_FLAGA,
|
||||
IO(24) => P_IO_UC_FLAGB,
|
||||
IO(25) => P_IO_UC_FLAGC,
|
||||
T => uc_ts(25 downto 0)
|
||||
);
|
||||
|
||||
-- Connection for I/O pad flipflops
|
||||
-- --------------------------------
|
||||
|
||||
-- control signals
|
||||
uc_clk_i <= (others => I_CLK33);
|
||||
uc_ce_i <= (others => '1');
|
||||
uc_clr_i(24 downto 0) <= (others => '0');
|
||||
uc_clr_i(25) <= I_RESET;
|
||||
uc_pre_i(24 downto 0) <= (others => I_RESET) ;
|
||||
uc_pre_i(25) <= '0';
|
||||
uc_clk_o <= (others => I_CLK33);
|
||||
uc_ce_o <= (others => '1') ;
|
||||
uc_clr_o <= (others => '0') ;
|
||||
uc_pre_o <= (others => I_RESET) ;
|
||||
|
||||
-- port direction
|
||||
uc_ts(15 downto 0) <= (others => uc_fdts);
|
||||
uc_ts(22 downto 16) <= (others => '0'); -- fixed output
|
||||
uc_ts(25 downto 23) <= (others => '1'); -- fixed input
|
||||
|
||||
-- FF connection
|
||||
uc_data_i <= uc_i(15 downto 0);
|
||||
uc_flaga <= uc_i(23);
|
||||
uc_flagb <= uc_i(24);
|
||||
uc_flagc <= uc_i(25);
|
||||
|
||||
uc_o(15 downto 0) <= uc_data_o;
|
||||
uc_o(16) <= uc_pktend;
|
||||
uc_o(17) <= uc_sloe;
|
||||
uc_o(18) <= uc_slrd;
|
||||
uc_o(19) <= uc_slwr;
|
||||
uc_o(20) <= uc_slcs;
|
||||
uc_o(21) <= uc_fifoadr0;
|
||||
uc_o(22) <= uc_fifoadr1;
|
||||
|
||||
debug <= '0';
|
||||
|
||||
process(I_RESET, I_CLK33)
|
||||
begin
|
||||
if (I_RESET = '1') then
|
||||
|
||||
control_reg_arr <= (others => X"00000000");
|
||||
|
||||
control_reg_no <= 0;
|
||||
status_reg_no <= 0;
|
||||
locbus_addr <= (others => '0');
|
||||
|
||||
usrbus_byte_sel <= 0;
|
||||
usrbus_pkt_size <= 0;
|
||||
usrbus_status_sel <= '0';
|
||||
usrbus_ram_sel <= '0';
|
||||
usrbus_size <= (others => '0');
|
||||
|
||||
locbus_addr <= (others => '0');
|
||||
O_LOCBUS_ADDR <= (others => '0');
|
||||
O_LOCBUS_D_WR <= (others => '0');
|
||||
O_LOCBUS_WE <= '0';
|
||||
|
||||
O_CONTROL_TRIG_ARR <= (others => "0000");
|
||||
O_CONTROL0_BIT_TRIG_ARR <= (others => '0');
|
||||
|
||||
-- CY7C68013 configuration
|
||||
-- -----------------------
|
||||
uc_slcs <= '0'; -- FIFO interface always on
|
||||
uc_fifoadr0 <= '1'; -- Select EP 4
|
||||
uc_fifoadr1 <= '0';
|
||||
|
||||
uc_fdts_pl <= '1'; -- Tri-state data lines driven by uC
|
||||
uc_fdts <= '1'; -- Tri-state data lines driven by uC
|
||||
|
||||
uc_pktend <= '1';
|
||||
uc_sloe <= '1';
|
||||
uc_slrd <= '1';
|
||||
uc_slwr <= '1';
|
||||
|
||||
uc_data_o <= (others => '0');
|
||||
uc_state <= idle;
|
||||
|
||||
elsif rising_edge(I_CLK33) then
|
||||
|
||||
-- pipeline for syncronization with I/O-FFs
|
||||
uc_fdts <= uc_fdts_pl;
|
||||
|
||||
-- reset trigger signals
|
||||
O_CONTROL_TRIG_ARR <= (others => "0000");
|
||||
O_CONTROL0_BIT_TRIG_ARR <= (others => '0');
|
||||
|
||||
-- default values for RAM access
|
||||
O_LOCBUS_WE <= '0';
|
||||
|
||||
-- put ram address on bus on each clock cycle
|
||||
O_LOCBUS_ADDR <= locbus_addr;
|
||||
|
||||
-- Transfer buffers:
|
||||
-- 1. buffer:
|
||||
-- fd(0) : USB2_CMD_READ
|
||||
-- fd(1) : USB2_CMD_WRITE
|
||||
-- 2. buffer:
|
||||
-- fd(15:0) : addreess LSB
|
||||
-- 3. buffer:
|
||||
-- fd(15:0) : addreess MSB
|
||||
-- 4. buffer:
|
||||
-- fd(15:0) : byte size LSB
|
||||
-- 5. buffer:
|
||||
-- fd(15:0) : bytes size MSB
|
||||
--
|
||||
-- Address offsets:
|
||||
-- 0x00000 : CTRL
|
||||
-- 0x10000 : STATUS
|
||||
-- 0x20000 : FIFO
|
||||
-- 0x40000 : RAM BUF1
|
||||
-- 0x50000 : RAM BUF2
|
||||
-- ----------------
|
||||
case (uc_state) is
|
||||
|
||||
when idle =>
|
||||
uc_fifoadr0 <= '1'; -- Select EP 4
|
||||
uc_fifoadr1 <= '0';
|
||||
|
||||
uc_sloe <= '1';
|
||||
uc_slrd <= '1';
|
||||
uc_slwr <= '1';
|
||||
uc_fdts_pl <= '1';
|
||||
uc_pktend <= '1';
|
||||
|
||||
if (uc_flagc = '1') then
|
||||
uc_sloe <= '0';
|
||||
uc_slrd <= '0';
|
||||
uc_state <= oe1;
|
||||
end if;
|
||||
|
||||
-- wait until sloe signal propagates to pin and uc_data_i propagates in
|
||||
when oe1 =>
|
||||
uc_state <= oe2;
|
||||
when oe2 =>
|
||||
uc_state <= cmd;
|
||||
|
||||
when cmd =>
|
||||
if (uc_data_i(0) = '1') then
|
||||
uc_cmd <= cmd_read;
|
||||
else
|
||||
uc_cmd <= cmd_write;
|
||||
end if;
|
||||
uc_state <= adr0;
|
||||
|
||||
when adr0 =>
|
||||
locbus_addr(15 downto 0) <= uc_data_i;
|
||||
uc_state <= adr1;
|
||||
when adr1 =>
|
||||
locbus_addr(31 downto 16) <= uc_data_i;
|
||||
uc_state <= size0;
|
||||
when size0 =>
|
||||
usrbus_size(15 downto 0) <= uc_data_i;
|
||||
uc_state <= size1;
|
||||
when size1 =>
|
||||
usrbus_size(31 downto 16) <= uc_data_i;
|
||||
|
||||
usrbus_status_sel <= locbus_addr(16);
|
||||
usrbus_ram_sel <= locbus_addr(18);
|
||||
usrbus_pkt_size <= 0;
|
||||
|
||||
if (uc_cmd = cmd_read) then
|
||||
if (locbus_addr(18) = '1') then
|
||||
uc_state <= read_ram;
|
||||
else
|
||||
uc_state <= read_word;
|
||||
end if;
|
||||
uc_fifoadr0 <= '1'; -- Select EP 8
|
||||
uc_fifoadr1 <= '1';
|
||||
uc_sloe <= '1';
|
||||
uc_slrd <= '1';
|
||||
else
|
||||
uc_state <= write_word;
|
||||
end if;
|
||||
|
||||
usrbus_byte_sel <= conv_integer(locbus_addr(1))*2; -- only word boundary access
|
||||
control_reg_no <= conv_integer(locbus_addr(const_no_of_control_reg_addr_bits + 1 downto 2));
|
||||
status_reg_no <= conv_integer(locbus_addr(const_no_of_status_reg_addr_bits + 1 downto 2));
|
||||
|
||||
when read_ram =>
|
||||
-- one wait state until RAM data is available
|
||||
uc_state <= read_word;
|
||||
locbus_addr <= locbus_addr + "10"; -- increment 2 bytes
|
||||
|
||||
when read_word =>
|
||||
uc_slwr <= '0'; -- assert write line
|
||||
uc_fdts_pl <= '0'; -- remove tri-state for FD lines
|
||||
|
||||
if (usrbus_ram_sel = '0') then
|
||||
-- Register access
|
||||
if (usrbus_status_sel = '0') then
|
||||
-- Control register
|
||||
if (usrbus_byte_sel = 0) then
|
||||
uc_data_o <= control_reg_arr(control_reg_no)(15 downto 0);
|
||||
else
|
||||
uc_data_o <= control_reg_arr(control_reg_no)(31 downto 16);
|
||||
end if;
|
||||
else
|
||||
-- Status register
|
||||
if (usrbus_byte_sel = 0) then
|
||||
uc_data_o <= status_reg_arr(status_reg_no)(15 downto 0);
|
||||
else
|
||||
uc_data_o <= status_reg_arr(status_reg_no)(31 downto 16);
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
-- RAM access
|
||||
if (locbus_addr(1) = '1') then -- locbus_addr already got incremented!
|
||||
-- first 16-bit word
|
||||
uc_data_o(15 downto 0) <= I_LOCBUS_D_RD(15 downto 0);
|
||||
else
|
||||
-- second 16-bit word
|
||||
uc_data_o(15 downto 0) <= I_LOCBUS_D_RD(31 downto 16);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
-- auto increment register
|
||||
if (usrbus_ram_sel = '0') then
|
||||
if (usrbus_byte_sel = 0) then
|
||||
usrbus_byte_sel <= 2;
|
||||
else
|
||||
usrbus_byte_sel <= 0;
|
||||
status_reg_no <= status_reg_no + 1;
|
||||
control_reg_no <= control_reg_no + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- increment packet size, pause after 256 packets
|
||||
usrbus_pkt_size <= usrbus_pkt_size + 1;
|
||||
if (usrbus_pkt_size = 255) then
|
||||
uc_state <= read_pause1;
|
||||
else
|
||||
if (usrbus_ram_sel = '1') then
|
||||
locbus_addr <= locbus_addr + "10"; -- increment 2 bytes
|
||||
end if;
|
||||
usrbus_size <= usrbus_size - 2;
|
||||
end if;
|
||||
|
||||
-- finish when all words are written
|
||||
if (usrbus_size = X"00000002") then
|
||||
uc_pktend <= '0';
|
||||
uc_state <= read_end1;
|
||||
end if;
|
||||
|
||||
when read_pause1 =>
|
||||
uc_slwr <= '1'; -- de-assert write line
|
||||
-- one wait state until flagb is available
|
||||
uc_state <= read_pause2;
|
||||
when read_pause2 =>
|
||||
uc_state <= read_pause3;
|
||||
when read_pause3 =>
|
||||
uc_state <= read_pause4;
|
||||
when read_pause4 =>
|
||||
-- wait until full flag is de-asserted
|
||||
if (uc_flagb = '1') then
|
||||
uc_state <= read_word;
|
||||
usrbus_pkt_size <= 0;
|
||||
locbus_addr <= locbus_addr + "10"; -- increment 2 bytes
|
||||
usrbus_size <= usrbus_size - 2;
|
||||
end if;
|
||||
|
||||
when read_end1 =>
|
||||
uc_fifoadr0 <= '1'; -- Select EP 4
|
||||
uc_fifoadr1 <= '0';
|
||||
uc_slwr <= '1';
|
||||
uc_fdts_pl <= '1';
|
||||
uc_pktend <= '1';
|
||||
uc_state <= read_end2;
|
||||
when read_end2 =>
|
||||
uc_state <= read_end3;
|
||||
when read_end3 =>
|
||||
uc_state <= idle;
|
||||
|
||||
when write_word =>
|
||||
if (usrbus_ram_sel = '0') then
|
||||
-- Register access
|
||||
if (usrbus_byte_sel = 0) then
|
||||
control_reg_arr(control_reg_no)(15 downto 0) <= uc_data_i;
|
||||
O_CONTROL_TRIG_ARR(control_reg_no)(1) <= '1';
|
||||
O_CONTROL_TRIG_ARR(control_reg_no)(0) <= '1';
|
||||
if (control_reg_no = 0) then
|
||||
O_CONTROL0_BIT_TRIG_ARR(15 downto 0) <= uc_data_i;
|
||||
end if;
|
||||
usrbus_byte_sel <= 2;
|
||||
else
|
||||
control_reg_arr(control_reg_no)(31 downto 16) <= uc_data_i;
|
||||
O_CONTROL_TRIG_ARR(control_reg_no)(3) <= '1';
|
||||
O_CONTROL_TRIG_ARR(control_reg_no)(2) <= '1';
|
||||
if (control_reg_no = 0) then
|
||||
O_CONTROL0_BIT_TRIG_ARR(31 downto 16) <= uc_data_i;
|
||||
end if;
|
||||
usrbus_byte_sel <= 0;
|
||||
control_reg_no <= control_reg_no + 1;
|
||||
end if;
|
||||
else
|
||||
-- RAM access
|
||||
|
||||
if (locbus_addr(1) = '0') then
|
||||
-- first 16-bit word
|
||||
O_LOCBUS_D_WR(15 downto 0) <= uc_data_i;
|
||||
else
|
||||
-- second 16-bit word
|
||||
O_LOCBUS_D_WR(31 downto 16) <= uc_data_i;
|
||||
O_LOCBUS_WE <= '1'; -- writes require multiples of 4
|
||||
end if;
|
||||
|
||||
if (uc_flagc = '1') then
|
||||
locbus_addr <= locbus_addr + "10"; -- increment 2 bytes
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- continue until all words are written
|
||||
if (usrbus_size = X"00000002") then
|
||||
uc_state <= idle;
|
||||
end if;
|
||||
|
||||
if (uc_flagc = '1') then
|
||||
usrbus_size <= usrbus_size - 2;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
uc_state <= idle;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arch;
|
||||
@@ -0,0 +1,113 @@
|
||||
--#############################################################
|
||||
-- Author : Stefan Ritt
|
||||
-- Contents : Waveform memory for DRS4 board
|
||||
-- $Id: usb_dpram.vhd 7194 2007-04-04 13:08:16Z ritt@PSI.CH $
|
||||
--#############################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
-- use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
-- synopsys translate_off
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.ALL;
|
||||
-- synopsys translate_on
|
||||
use work.drs4_pack.all;
|
||||
|
||||
-- ##########################################################################################
|
||||
|
||||
entity usb_dpram is
|
||||
port (
|
||||
|
||||
I_RESET : in std_logic;
|
||||
|
||||
I_CLK_A : in std_logic;
|
||||
I_ADDR_A : in std_logic_vector(31 downto 0);
|
||||
I_WE_A : in std_logic;
|
||||
O_D_RD_A : out std_logic_vector(31 downto 0);
|
||||
I_D_WR_A : in std_logic_vector(31 downto 0);
|
||||
|
||||
I_CLK_B : in std_logic;
|
||||
I_ADDR_B : in std_logic_vector(31 downto 0);
|
||||
I_WE_B : in std_logic;
|
||||
O_D_RD_B : out std_logic_vector(31 downto 0);
|
||||
I_D_WR_B : in std_logic_vector(31 downto 0)
|
||||
|
||||
);
|
||||
end usb_dpram;
|
||||
|
||||
-- ##########################################################################################
|
||||
|
||||
architecture arch of usb_dpram is
|
||||
|
||||
attribute BOX_TYPE : string;
|
||||
|
||||
component RAMB16_S36_S36
|
||||
port(
|
||||
DOA : out std_logic_vector(31 downto 0);
|
||||
DOPA : out std_logic_vector(3 downto 0);
|
||||
DOB : out std_logic_vector(31 downto 0);
|
||||
DOPB : out std_logic_vector(3 downto 0);
|
||||
ADDRA : in std_logic_vector(8 downto 0);
|
||||
ADDRB : in std_logic_vector(8 downto 0);
|
||||
CLKA : in std_ulogic;
|
||||
CLKB : in std_ulogic;
|
||||
DIA : in std_logic_vector(31 downto 0);
|
||||
DIPA : in std_logic_vector(3 downto 0);
|
||||
DIB : in std_logic_vector(31 downto 0);
|
||||
DIPB : in std_logic_vector(3 downto 0);
|
||||
ENA : in std_ulogic;
|
||||
ENB : in std_ulogic;
|
||||
SSRA : in std_ulogic;
|
||||
SSRB : in std_ulogic;
|
||||
WEA : in std_ulogic;
|
||||
WEB : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
attribute BOX_TYPE of RAMB16_S36_S36: component is "PRIMITIVE";
|
||||
|
||||
signal block_we_a : std_logic_vector(15 downto 0);
|
||||
signal block_we_b : std_logic_vector(15 downto 0);
|
||||
|
||||
type block_do_type is array (15 downto 0) of std_logic_vector(31 downto 0);
|
||||
signal block_do_a : block_do_type;
|
||||
signal block_do_b : block_do_type;
|
||||
|
||||
begin
|
||||
|
||||
dpram_gen : for block_no in 0 to 15 generate
|
||||
|
||||
block_we_a(block_no) <= I_WE_A when I_ADDR_A(14 downto 11) = block_no else '0';
|
||||
block_we_b(block_no) <= I_WE_B when I_ADDR_B(14 downto 11) = block_no else '0';
|
||||
|
||||
ramb16_s36_s36_inst: RAMB16_S36_S36
|
||||
port map (
|
||||
CLKA => I_CLK_A,
|
||||
ADDRA => I_ADDR_A(10 downto 2),
|
||||
ENA => '1',
|
||||
WEA => block_we_a(block_no),
|
||||
DIA => I_D_WR_A,
|
||||
DIPA => (others => '0'),
|
||||
DOA => block_do_a(block_no),
|
||||
DOPA => open,
|
||||
SSRA => '0', -- output reset unused
|
||||
|
||||
CLKB => I_CLK_B,
|
||||
ADDRB => I_ADDR_B(10 downto 2),
|
||||
ENB => '1',
|
||||
WEB => block_we_b(block_no),
|
||||
DIB => I_D_WR_B,
|
||||
DIPB => (others => '0'),
|
||||
DOB => block_do_b(block_no),
|
||||
DOPB => open,
|
||||
SSRB => '0'
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
O_D_RD_A <= block_do_a(conv_integer(I_ADDR_A(14 downto 11)));
|
||||
O_D_RD_B <= block_do_b(conv_integer(I_ADDR_B(14 downto 11)));
|
||||
|
||||
end arch;
|
||||
@@ -0,0 +1,359 @@
|
||||
--#############################################################
|
||||
-- Author : Boris Keil, Stefan Ritt
|
||||
-- Contents : Use external 33 MHz to generate internal clocks
|
||||
-- via DCMs
|
||||
-- $Id: usr_clocks.vhd 8369 2007-07-06 14:47:25Z ritt@PSI.CH $
|
||||
--#############################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
-- synopsys translate_off
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.all;
|
||||
-- synopsys translate_on
|
||||
|
||||
entity usr_clocks is
|
||||
port (
|
||||
P_I_CLK33 : in std_logic;
|
||||
P_I_CLK66 : in std_logic;
|
||||
O_CLK33 : out std_logic;
|
||||
O_CLK33_NODLL : out std_logic;
|
||||
O_CLK66 : out std_logic;
|
||||
O_CLK132 : out std_logic;
|
||||
O_CLK264 : out std_logic;
|
||||
I_PS_VALUE : in std_logic_vector(7 downto 0);
|
||||
O_CLK_PS : out std_logic;
|
||||
O_LOCKED : out std_logic;
|
||||
O_DEBUG1 : out std_logic;
|
||||
O_DEBUG2 : out std_logic
|
||||
);
|
||||
end usr_clocks;
|
||||
|
||||
architecture arch of usr_clocks is
|
||||
attribute BOX_TYPE : STRING ;
|
||||
|
||||
-- xilinx cores
|
||||
|
||||
component IBUFGDS_LVDS_25
|
||||
port(
|
||||
O : out std_ulogic;
|
||||
I : in std_ulogic;
|
||||
IB : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of IBUFGDS_LVDS_25 : component is "PRIMITIVE";
|
||||
|
||||
component BUFG
|
||||
port(
|
||||
O : out std_ulogic;
|
||||
I : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of BUFG : component is "PRIMITIVE";
|
||||
|
||||
-- !!! WARNING !!! : The Virtex2Pro has a bug in the DCM
|
||||
-- (a silicon bug, i.e. real hardware), the PLL does not
|
||||
-- lock properly if the CLK2x output is used for
|
||||
-- feedback -> always use CLK1x !!! (Call from Memec,
|
||||
-- C. Grivet, 17.12.03)
|
||||
|
||||
component DCM
|
||||
generic (
|
||||
CLKDV_DIVIDE : real := 2.0;
|
||||
CLKFX_DIVIDE : integer := 1;
|
||||
CLKFX_MULTIPLY : integer := 4;
|
||||
CLKIN_DIVIDE_BY_2 : boolean := false;
|
||||
CLKIN_PERIOD : real := 0.0; --non-simulatable, in nanoseconds
|
||||
CLKOUT_PHASE_SHIFT : string := "NONE";
|
||||
CLK_FEEDBACK : string := "1X";
|
||||
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
|
||||
DFS_FREQUENCY_MODE : string := "LOW";
|
||||
DLL_FREQUENCY_MODE : string := "LOW";
|
||||
DSS_MODE : string := "NONE"; --non-simulatable
|
||||
DUTY_CYCLE_CORRECTION : boolean := true;
|
||||
-- MAXPERCLKIN : time := 1000000 ps; --simulation parameter
|
||||
-- MAXPERPSCLK : time := 100000000 ps; --simulation parameter
|
||||
PHASE_SHIFT : integer := 0;
|
||||
-- SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --simulation parameter
|
||||
-- SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --simulation parameter
|
||||
STARTUP_WAIT : boolean := false --non-simulatable
|
||||
);
|
||||
port (
|
||||
CLK0 : out std_ulogic := '0';
|
||||
CLK180 : out std_ulogic := '0';
|
||||
CLK270 : out std_ulogic := '0';
|
||||
CLK2X : out std_ulogic := '0';
|
||||
CLK2X180 : out std_ulogic := '0';
|
||||
CLK90 : out std_ulogic := '0';
|
||||
CLKDV : out std_ulogic := '0';
|
||||
CLKFX : out std_ulogic := '0';
|
||||
CLKFX180 : out std_ulogic := '0';
|
||||
LOCKED : out std_ulogic := '0';
|
||||
PSDONE : out std_ulogic := '0';
|
||||
STATUS : out std_logic_vector(7 downto 0) := "00000000";
|
||||
|
||||
CLKFB : in std_ulogic := '0';
|
||||
CLKIN : in std_ulogic := '0';
|
||||
DSSEN : in std_ulogic := '0';
|
||||
PSCLK : in std_ulogic := '0';
|
||||
PSEN : in std_ulogic := '0';
|
||||
PSINCDEC : in std_ulogic := '0';
|
||||
RST : in std_ulogic := '0'
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of DCM : component is "PRIMITIVE";
|
||||
|
||||
signal clk33_i, clk33, clk66_dcm1, clk66_dcm2, clk132, clk_ps : std_logic;
|
||||
signal clk33_tmp, clk66_dcm1_tmp, clk66_dcm2_tmp, clk132_tmp, clk_ps_tmp : std_logic;
|
||||
signal locked_dcm1, locked_dcm2, locked_dcm3: std_logic;
|
||||
signal dcm2_reset, dcm2_reset_n: std_logic;
|
||||
signal dcm2_reset_delay_n: std_logic_vector(4 downto 0);
|
||||
|
||||
type type_ps_state is (idle, incdec);
|
||||
signal ps_state : type_ps_state;
|
||||
signal ps_enable, ps_incdec, ps_done: std_logic;
|
||||
signal ps_shadow: std_logic_vector(7 downto 0);
|
||||
|
||||
signal GND: std_logic;
|
||||
signal VCC: std_logic;
|
||||
|
||||
begin
|
||||
GND <= '0';
|
||||
VCC <= '1';
|
||||
|
||||
-- Drive clock buffer with input pad oscillator signal
|
||||
|
||||
inst_bufg_clk33_i: BUFG
|
||||
port map (
|
||||
I => P_I_CLK33,
|
||||
O => clk33_i
|
||||
);
|
||||
|
||||
O_CLK33_NODLL <= clk33_i;
|
||||
|
||||
-- Use clock buffers for DCM outputs
|
||||
|
||||
inst_bufg_clk33_dcm1: BUFG
|
||||
port map (
|
||||
I => clk33_tmp,
|
||||
O => clk33
|
||||
);
|
||||
|
||||
inst_bufg_clk66_dcm1: BUFG
|
||||
port map (
|
||||
I => clk66_dcm1_tmp,
|
||||
O => clk66_dcm1
|
||||
);
|
||||
|
||||
inst_bufg_clk66_dcm2: BUFG
|
||||
port map (
|
||||
I => clk66_dcm2_tmp,
|
||||
O => clk66_dcm2
|
||||
);
|
||||
|
||||
inst_bufg_clk132: BUFG
|
||||
port map (
|
||||
I => clk132_tmp,
|
||||
O => clk132
|
||||
);
|
||||
|
||||
inst_bufg_clk_ps: BUFG
|
||||
port map (
|
||||
I => clk_ps_tmp,
|
||||
O => clk_ps
|
||||
);
|
||||
|
||||
Inst_dcm1_clk132: DCM
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0,
|
||||
CLKFX_DIVIDE => 1,
|
||||
CLKFX_MULTIPLY => 4,
|
||||
CLKIN_DIVIDE_BY_2 => false,
|
||||
CLKIN_PERIOD => 30.0, -- in nanoseconds
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
CLK_FEEDBACK => "1X", -- 2X has a silicon bug ...
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- OK ?? non-simulatable
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DSS_MODE => "NONE", --non-simulatable
|
||||
DUTY_CYCLE_CORRECTION => true,
|
||||
-- MAXPERCLKIN => 1000000 ps, --simulation parameter
|
||||
-- MAXPERPSCLK => 100000000 ps, --simulation parameter
|
||||
PHASE_SHIFT => 0,
|
||||
-- SIM_CLKIN_CYCLE_JITTER => 300 ps, --simulation parameter
|
||||
-- SIM_CLKIN_PERIOD_JITTER => 1000 ps, --simulation parameter
|
||||
STARTUP_WAIT => true --non-simulatable
|
||||
)
|
||||
port map (
|
||||
-- inputs
|
||||
CLKFB => clk33,
|
||||
CLKIN => clk33_i,
|
||||
DSSEN => GND,
|
||||
PSCLK => GND,
|
||||
PSEN => GND,
|
||||
PSINCDEC => GND,
|
||||
RST => GND,
|
||||
-- outputs
|
||||
CLK0 => clk33_tmp,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => clk66_dcm1_tmp,
|
||||
CLK2X180 => open,
|
||||
CLK90 => open,
|
||||
CLKDV => open,
|
||||
CLKFX => open,
|
||||
CLKFX180 => open,
|
||||
LOCKED => locked_dcm1,
|
||||
PSDONE => open,
|
||||
STATUS => open
|
||||
|
||||
);
|
||||
|
||||
Inst_dcm2_clk132: DCM
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0,
|
||||
CLKFX_DIVIDE => 1,
|
||||
CLKFX_MULTIPLY => 2,
|
||||
CLKIN_DIVIDE_BY_2 => false,
|
||||
CLKIN_PERIOD => 15.0, -- in nanoseconds
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
CLK_FEEDBACK => "1X", -- 2X has a silicon bug ...
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- OK ?? non-simulatable
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "HIGH",
|
||||
DSS_MODE => "NONE", --non-simulatable
|
||||
DUTY_CYCLE_CORRECTION => true,
|
||||
-- MAXPERCLKIN => 1000000 ps, --simulation parameter
|
||||
-- MAXPERPSCLK => 100000000 ps, --simulation parameter
|
||||
PHASE_SHIFT => 0,
|
||||
-- SIM_CLKIN_CYCLE_JITTER => 300 ps, --simulation parameter
|
||||
-- SIM_CLKIN_PERIOD_JITTER => 1000 ps, --simulation parameter
|
||||
STARTUP_WAIT => false --non-simulatable
|
||||
)
|
||||
port map (
|
||||
-- inputs
|
||||
CLKFB => clk66_dcm2,
|
||||
CLKIN => P_I_CLK66,
|
||||
DSSEN => GND,
|
||||
PSCLK => GND,
|
||||
PSEN => GND,
|
||||
PSINCDEC => GND,
|
||||
RST => dcm2_reset,
|
||||
-- outputs
|
||||
CLK0 => clk66_dcm2_tmp,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLK90 => open,
|
||||
CLKDV => open,
|
||||
CLKFX => clk132_tmp,
|
||||
CLKFX180 => open,
|
||||
LOCKED => locked_dcm2,
|
||||
PSDONE => open,
|
||||
STATUS => open
|
||||
|
||||
);
|
||||
|
||||
Inst_dcm3_clk_ps: DCM
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0,
|
||||
CLKFX_DIVIDE => 1,
|
||||
CLKFX_MULTIPLY => 2,
|
||||
CLKIN_DIVIDE_BY_2 => false,
|
||||
CLKIN_PERIOD => 30.0, -- in nanoseconds
|
||||
CLKOUT_PHASE_SHIFT => "VARIABLE", -- turn on phase shifting
|
||||
CLK_FEEDBACK => "1X",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DSS_MODE => "NONE",
|
||||
DUTY_CYCLE_CORRECTION => true,
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => true
|
||||
)
|
||||
port map (
|
||||
-- inputs
|
||||
CLKFB => clk_ps,
|
||||
CLKIN => clk33_i,
|
||||
DSSEN => GND,
|
||||
PSCLK => P_I_CLK33,
|
||||
PSEN => ps_enable,
|
||||
PSINCDEC => ps_incdec,
|
||||
RST => GND,
|
||||
-- outputs
|
||||
CLK0 => clk_ps_tmp,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLK90 => open,
|
||||
CLKDV => open,
|
||||
CLKFX => open,
|
||||
CLKFX180 => open,
|
||||
LOCKED => locked_dcm3,
|
||||
PSDONE => ps_done,
|
||||
STATUS => open
|
||||
|
||||
);
|
||||
|
||||
-- DCM2 is reset while DCM1 is not locked, because DCM1 feeds DCM2.
|
||||
-- A shift register guarantees a decent (i.e. long) reset pulse.
|
||||
proc_delayed_reset: process (P_I_CLK33)
|
||||
begin
|
||||
if rising_edge(P_I_CLK33) then
|
||||
if (locked_dcm1 = '0') then
|
||||
dcm2_reset_delay_n <= (others => '0');
|
||||
dcm2_reset_n <= '0';
|
||||
else
|
||||
dcm2_reset_delay_n <= dcm2_reset_delay_n(dcm2_reset_delay_n'high-1 downto 0) & '1';
|
||||
dcm2_reset_n <= dcm2_reset_delay_n(dcm2_reset_delay_n'high);
|
||||
dcm2_reset <= not dcm2_reset_n;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_phase_shift: process (P_I_CLK33)
|
||||
begin
|
||||
if (locked_dcm1 = '0') then
|
||||
ps_state <= idle;
|
||||
ps_enable <= '0';
|
||||
ps_shadow <= (others => '0');
|
||||
elsif rising_edge(P_I_CLK33) then
|
||||
case (ps_state) is
|
||||
when idle =>
|
||||
if (TO_SIGNED(CONV_INTEGER(I_PS_VALUE), 8) > TO_SIGNED(CONV_INTEGER(ps_shadow), 8)) then
|
||||
ps_enable <= '1';
|
||||
ps_incdec <= '1';
|
||||
ps_state <= incdec;
|
||||
ps_shadow <= ps_shadow + 1;
|
||||
elsif (TO_SIGNED(CONV_INTEGER(I_PS_VALUE), 8) < TO_SIGNED(CONV_INTEGER(ps_shadow), 8)) then
|
||||
ps_enable <= '1';
|
||||
ps_incdec <= '0';
|
||||
ps_state <= incdec;
|
||||
ps_shadow <= ps_shadow - 1;
|
||||
end if;
|
||||
when incdec =>
|
||||
ps_enable <= '0';
|
||||
if (ps_done = '1') then
|
||||
ps_state <= idle;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Debug outputs
|
||||
O_DEBUG1 <= clk66_dcm1;
|
||||
O_DEBUG2 <= clk132;
|
||||
|
||||
-- DCM outputs
|
||||
O_CLK33 <= clk33;
|
||||
O_CLK66 <= clk66_dcm1;
|
||||
O_CLK132 <= clk132;
|
||||
O_CLK264 <= '0';
|
||||
O_CLK_PS <= clk_ps;
|
||||
O_LOCKED <= locked_dcm1 and locked_dcm3;
|
||||
end arch;
|
||||
@@ -0,0 +1,172 @@
|
||||
--##################################################################
|
||||
-- Author : Boris Keil, Stefan Ritt
|
||||
-- Contents : User FPGA library with various components
|
||||
-- $Id: usr_lib.vhd 6908 2007-03-06 07:15:16Z ritt $
|
||||
--##################################################################
|
||||
|
||||
--------------------------------------------------------------------
|
||||
------------------------ USR_LIB_VEC_IOFD_CPE_NALL -----------------
|
||||
--------------------------------------------------------------------
|
||||
|
||||
-- FFs with CE & asynchr. clear (precedence, act. high), preset
|
||||
-- (active high) and threestate (act. high)
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.ALL;
|
||||
--use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.ALL;
|
||||
-- synopsys translate_off
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.ALL;
|
||||
-- synopsys translate_on
|
||||
|
||||
entity USR_LIB_VEC_IOFD_CPE_NALL is
|
||||
generic (
|
||||
width : integer := 1;
|
||||
init_val_to_pad : string := "0";
|
||||
init_val_from_pad : string := "0"
|
||||
);
|
||||
port (
|
||||
O_C : in std_logic_vector (width-1 downto 0);
|
||||
O_CE : in std_logic_vector (width-1 downto 0);
|
||||
O_CLR : in std_logic_vector (width-1 downto 0);
|
||||
O_PRE : in std_logic_vector (width-1 downto 0);
|
||||
O : out std_logic_vector (width-1 downto 0);
|
||||
|
||||
I_C : in std_logic_vector (width-1 downto 0);
|
||||
I_CE : in std_logic_vector (width-1 downto 0);
|
||||
I_CLR : in std_logic_vector (width-1 downto 0);
|
||||
I_PRE : in std_logic_vector (width-1 downto 0);
|
||||
I : in std_logic_vector (width-1 downto 0);
|
||||
|
||||
IO : inout std_logic_vector (width-1 downto 0);
|
||||
T : in std_logic_vector (width-1 downto 0)
|
||||
);
|
||||
end USR_LIB_VEC_IOFD_CPE_NALL;
|
||||
|
||||
architecture arch of USR_LIB_VEC_IOFD_CPE_NALL is
|
||||
attribute BOX_TYPE : STRING ;
|
||||
attribute INIT : STRING ;
|
||||
attribute IOB : STRING ;
|
||||
|
||||
component IOBUF
|
||||
port(
|
||||
O : out std_logic;
|
||||
IO : inout std_logic;
|
||||
I : in std_logic;
|
||||
T : in std_logic
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of IOBUF : component is "PRIMITIVE";
|
||||
|
||||
component FDCPE -- FF with CE & asynchronous clear (precedence) and preset
|
||||
generic(
|
||||
INIT : bit := '0'
|
||||
);
|
||||
port(
|
||||
Q : out std_logic;
|
||||
C : in std_logic;
|
||||
CE : in std_logic;
|
||||
D : in std_logic;
|
||||
CLR : in std_logic;
|
||||
PRE : in std_logic
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of FDCPE : component is "PRIMITIVE";
|
||||
|
||||
signal data_to_pad: std_logic_vector (width-1 downto 0);
|
||||
signal data_from_pad: std_logic_vector (width-1 downto 0);
|
||||
begin
|
||||
gen : for count in 0 to width-1 generate
|
||||
attribute INIT of FF1 : label is init_val_to_pad;
|
||||
attribute IOB of FF1 : label is "true";
|
||||
attribute INIT of FF2 : label is init_val_from_pad;
|
||||
attribute IOB of FF2 : label is "true";
|
||||
begin
|
||||
U1 : IOBUF
|
||||
port map (
|
||||
I => data_to_pad(count),
|
||||
O => data_from_pad(count),
|
||||
IO => IO(count),
|
||||
T => T(count)
|
||||
);
|
||||
FF1 : FDCPE
|
||||
port map (
|
||||
C => I_C(count),
|
||||
CE => I_CE(count),
|
||||
D => I(count),
|
||||
CLR => I_CLR(count),
|
||||
PRE => I_PRE(count),
|
||||
Q => data_to_pad(count)
|
||||
);
|
||||
FF2 : FDCPE
|
||||
port map (
|
||||
C => O_C(count),
|
||||
CE => O_CE(count),
|
||||
D => data_from_pad(count),
|
||||
CLR => O_CLR(count),
|
||||
PRE => O_PRE(count),
|
||||
Q => O(count)
|
||||
);
|
||||
end generate;
|
||||
end arch;
|
||||
|
||||
--------------------------------------------------------------------
|
||||
------------------------ USR_LIB_VEC_FDC ---------------------------
|
||||
--------------------------------------------------------------------
|
||||
|
||||
-- Input FFs with asynchr. clear (precedence, act. high)
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.ALL;
|
||||
--use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.ALL;
|
||||
-- synopsys translate_off
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.ALL;
|
||||
-- synopsys translate_on
|
||||
|
||||
entity USR_LIB_VEC_FDC is
|
||||
generic (
|
||||
width : integer := 1
|
||||
);
|
||||
port (
|
||||
I_CLK : in std_logic_vector (width-1 downto 0);
|
||||
I_CLR : in std_logic_vector (width-1 downto 0);
|
||||
I : in std_logic_vector (width-1 downto 0);
|
||||
O : out std_logic_vector (width-1 downto 0)
|
||||
);
|
||||
end USR_LIB_VEC_FDC;
|
||||
|
||||
architecture arch of USR_LIB_VEC_FDC is
|
||||
attribute IOB : STRING ;
|
||||
attribute BOX_TYPE : STRING ;
|
||||
|
||||
component FDC -- FF with asynchronous clear (precedence)
|
||||
generic(
|
||||
INIT : bit := '0'
|
||||
);
|
||||
port(
|
||||
C : in std_logic;
|
||||
CLR : in std_logic;
|
||||
D : in std_logic;
|
||||
Q : out std_logic
|
||||
);
|
||||
end component;
|
||||
attribute BOX_TYPE of FDC : component is "PRIMITIVE";
|
||||
|
||||
begin
|
||||
gen : for count in 0 to width-1 generate
|
||||
attribute IOB of FF : label is "true";
|
||||
begin
|
||||
FF : FDC
|
||||
port map (
|
||||
C => I_CLK(count),
|
||||
CLR => I_CLR(count),
|
||||
D => I(count),
|
||||
Q => O(count)
|
||||
);
|
||||
end generate;
|
||||
end arch;
|
||||
@@ -0,0 +1,183 @@
|
||||
###############################################################
|
||||
## Author : Stefan Ritt
|
||||
## Contents : DRS4_EVAL4 FPGA constraint file
|
||||
## $Id: drs4_eval5.ucf 21696 2015-05-13 13:15:31Z ritt $
|
||||
###############################################################
|
||||
|
||||
CONFIG PART = XC3S400-4TQ144 ;
|
||||
|
||||
###############################################################
|
||||
# Timing constraints
|
||||
###############################################################
|
||||
|
||||
# Timing group definitions
|
||||
# ------------------------
|
||||
NET "P_I_CLK33" TNM_NET = "P_I_CLK33";
|
||||
NET "P_I_*" TNM = PADS:P_I_PADS_ALL;
|
||||
NET "P_I_CLK33" TNM = PADS:P_I_CLK33_PAD;
|
||||
NET "P_O_*" TNM = PADS:P_O_PADS;
|
||||
NET "P_IO_*" TNM = PADS:P_IO_PADS;
|
||||
|
||||
NET "P_O_LED*" TNM = PADS:P_O_LED_PADS;
|
||||
|
||||
NET "P_I_J*" TNM = PADS:P_I_EXT_PADS;
|
||||
NET "P_I_ATRG*" TNM = PADS:P_I_EXT_PADS;
|
||||
NET "P_O_CAL" TNM = PADS:P_I_EXT_PADS;
|
||||
NET "P_O_TCA_CTRL" TNM = PADS:P_I_EXT_PADS;
|
||||
|
||||
NET "P_IO_PMC_USR(28)" TNM = PADS:P_IO_PMC_USR28_PADS;
|
||||
|
||||
TIMEGRP "P_I_PADS" = "P_I_PADS_ALL" EXCEPT "P_I_CLK33_PAD";
|
||||
|
||||
# IFCLK is not connected to dedicated clock input
|
||||
# Following statement suppresses the error abort
|
||||
NET "P_I_CLK33" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
# Same for external trigger input
|
||||
NET "P_IO_ETRG_IN" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
# Fix Hold-Time-Violations
|
||||
# ------------------------
|
||||
NET "P_I_*" IOBDELAY = IFD;
|
||||
NET "P_IO_*" IOBDELAY = IFD;
|
||||
|
||||
# Period constraint for 30 MHz main board clock oscillator
|
||||
# --------------------------------------------------------
|
||||
# 33 ns needed, 32 ns used -> 1 ns safety margin
|
||||
TIMESPEC "TS_P_I_CLK33" = PERIOD "P_I_CLK33" 32 ns HIGH 50 % INPUT_JITTER 100 ps;
|
||||
|
||||
# Input pad setup/hold time constraints
|
||||
# -------------------------------------
|
||||
TIMEGRP "P_I_PADS" OFFSET = IN 20 ns BEFORE "P_I_CLK33";
|
||||
TIMEGRP "P_IO_PADS" OFFSET = IN 20 ns BEFORE "P_I_CLK33";
|
||||
|
||||
# Output pad clock to output timing constraints
|
||||
# ---------------------------------------------
|
||||
TIMEGRP "P_O_PADS" OFFSET = OUT 22 ns AFTER "P_I_CLK33";
|
||||
TIMEGRP "P_IO_PADS" OFFSET = OUT 22 ns AFTER "P_I_CLK33";
|
||||
|
||||
# remove noncritical contraints
|
||||
# -------------------------------
|
||||
TIMESPEC "TS_TIG_I_MMCX" = FROM "P_I_EXT_PADS" TO "FFS" TIG;
|
||||
TIMESPEC "TS_TIG_O_LED" = FROM "FFS" TO "P_O_LED_PADS" TIG;
|
||||
TIMESPEC "TS_TIG_O_EXT" = FROM "FFS" TO "P_O_EXT_PADS" TIG;
|
||||
TIMESPEC "TS_TIG_O_ADCCLK" = FROM "FFS" TO "P_IO_PMC_USR28_PADS" TIG;
|
||||
|
||||
###############################################################
|
||||
# IOSTANDARD & pin drive speed constraints
|
||||
###############################################################
|
||||
|
||||
NET "P_IO_*" IOSTANDARD = LVCMOS33;
|
||||
NET "P_I_*" IOSTANDARD = LVCMOS33;
|
||||
NET "P_O_*" IOSTANDARD = LVCMOS33;
|
||||
|
||||
###############################################################
|
||||
# Pin location constraints
|
||||
###############################################################
|
||||
|
||||
# 42 out of 64 PMC IOs
|
||||
# --------------------
|
||||
|
||||
NET "P_I_CLK33" LOC = "P40"; # IFCLK input
|
||||
NET "P_I_CLK66" LOC = "P56"; # calibration quarz input
|
||||
|
||||
NET "P_O_CAL" LOC = "P97" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_O_TCA_CTRL" LOC = "P53"; # timing calibration control
|
||||
|
||||
NET "P_IO_J42" LOC = "P141"; # J42
|
||||
NET "P_IO_J43" LOC = "P140"; # J43
|
||||
NET "P_IO_T19" LOC = "P108" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # T19
|
||||
NET "P_IO_T20" LOC = "P103" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # T20
|
||||
|
||||
NET "P_I_J44" LOC = "P69";
|
||||
|
||||
NET "P_I_ATRG1" LOC = "P70"; # analog trigger CH1
|
||||
NET "P_I_ATRG1" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "P_I_ATRG2" LOC = "P68"; # analog trigger CH2
|
||||
NET "P_I_ATRG2" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "P_I_ATRG3" LOC = "P60"; # analog trigger CH3
|
||||
NET "P_I_ATRG3" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "P_I_ATRG4" LOC = "P59"; # analog trigger CH4
|
||||
NET "P_I_ATRG4" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "P_IO_ETRG_IN" LOC = "P107" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external trigger in
|
||||
NET "P_O_ETRG_IND" LOC = "P105" | IOSTANDARD = LVCMOS25; # external trigger in direciton
|
||||
|
||||
NET "P_IO_ETRG_OUT" LOC = "P104" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external trigger out
|
||||
NET "P_O_ETRG_OUTD" LOC = "P102" | IOSTANDARD = LVCMOS25; # external trigger out direction
|
||||
|
||||
NET "P_IO_ECLK_IN" LOC = "P100" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external clock input
|
||||
NET "P_IO_ECLK_IN" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "P_O_ECLK_IND" LOC = "P99" | IOSTANDARD = LVCMOS25; # external clock input direction
|
||||
|
||||
NET "P_IO_ECLK_OUT" LOC = "P98" | IOSTANDARD = LVCMOS25 | SLEW = FAST ; # external clock output
|
||||
NET "P_O_ECLK_OUTD" LOC = "P93" | IOSTANDARD = LVCMOS25; # external clock output direction
|
||||
|
||||
NET "P_O_LED_GREEN" LOC = "P132";
|
||||
NET "P_O_LED_YELLOW" LOC = "P137";
|
||||
|
||||
NET "P_IO_UC_SLOE" LOC = "P17";
|
||||
NET "P_IO_UC_SLRD" LOC = "P35";
|
||||
NET "P_IO_UC_SLWR" LOC = "P36";
|
||||
NET "P_IO_UC_SLCS" LOC = "P11";
|
||||
NET "P_IO_UC_PKTEND" LOC = "P12";
|
||||
NET "P_IO_UC_FIFOADR0" LOC = "P14";
|
||||
NET "P_IO_UC_FIFOADR1" LOC = "P13";
|
||||
NET "P_IO_UC_FLAGA" LOC = "P24";
|
||||
NET "P_IO_UC_FLAGB" LOC = "P23";
|
||||
NET "P_IO_UC_FLAGC" LOC = "P21";
|
||||
NET "P_I_UC_PA0" LOC = "P20";
|
||||
|
||||
NET "P_IO_UC_FD(0)" LOC = "P30";
|
||||
NET "P_IO_UC_FD(1)" LOC = "P31";
|
||||
NET "P_IO_UC_FD(2)" LOC = "P32";
|
||||
NET "P_IO_UC_FD(3)" LOC = "P33";
|
||||
NET "P_IO_UC_FD(4)" LOC = "P28";
|
||||
NET "P_IO_UC_FD(5)" LOC = "P27";
|
||||
NET "P_IO_UC_FD(6)" LOC = "P26";
|
||||
NET "P_IO_UC_FD(7)" LOC = "P25";
|
||||
NET "P_IO_UC_FD(8)" LOC = "P10";
|
||||
NET "P_IO_UC_FD(9)" LOC = "P8";
|
||||
NET "P_IO_UC_FD(10)" LOC = "P7";
|
||||
NET "P_IO_UC_FD(11)" LOC = "P6";
|
||||
NET "P_IO_UC_FD(12)" LOC = "P5";
|
||||
NET "P_IO_UC_FD(13)" LOC = "P1";
|
||||
NET "P_IO_UC_FD(14)" LOC = "P2";
|
||||
NET "P_IO_UC_FD(15)" LOC = "P4";
|
||||
|
||||
NET "P_IO_PMC_USR(0)" LOC = "P131";
|
||||
NET "P_IO_PMC_USR(2)" LOC = "P130";
|
||||
NET "P_IO_PMC_USR(4)" LOC = "P129";
|
||||
NET "P_IO_PMC_USR(6)" LOC = "P128";
|
||||
NET "P_IO_PMC_USR(8)" LOC = "P127";
|
||||
NET "P_IO_PMC_USR(10)" LOC = "P125";
|
||||
NET "P_IO_PMC_USR(12)" LOC = "P124";
|
||||
NET "P_IO_PMC_USR(14)" LOC = "P123";
|
||||
NET "P_IO_PMC_USR(16)" LOC = "P122";
|
||||
NET "P_IO_PMC_USR(18)" LOC = "P119";
|
||||
NET "P_IO_PMC_USR(20)" LOC = "P118";
|
||||
NET "P_IO_PMC_USR(22)" LOC = "P116";
|
||||
NET "P_IO_PMC_USR(24)" LOC = "P113";
|
||||
NET "P_IO_PMC_USR(26)" LOC = "P112";
|
||||
NET "P_IO_PMC_USR(28)" LOC = "P135";
|
||||
NET "P_IO_PMC_USR(29)" LOC = "P50";
|
||||
NET "P_IO_PMC_USR(30)" LOC = "P80" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(31)" LOC = "P51";
|
||||
NET "P_IO_PMC_USR(33)" LOC = "P52";
|
||||
NET "P_IO_PMC_USR(35)" LOC = "P44";
|
||||
NET "P_IO_PMC_USR(37)" LOC = "P46";
|
||||
NET "P_IO_PMC_USR(39)" LOC = "P47";
|
||||
NET "P_IO_PMC_USR(40)" LOC = "P74" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(41)" LOC = "P92" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(42)" LOC = "P76" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(48)" LOC = "P89" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(50)" LOC = "P87" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(51)" LOC = "P90" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(52)" LOC = "P86" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(53)" LOC = "P79" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(54)" LOC = "P78" | IOSTANDARD = LVDS_25;
|
||||
NET "P_IO_PMC_USR(55)" LOC = "P77" | IOSTANDARD = LVDS_25;
|
||||
NET "P_IO_PMC_USR(56)" LOC = "P85" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(58)" LOC = "P84" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(60)" LOC = "P83" | IOSTANDARD = LVCMOS25;
|
||||
NET "P_IO_PMC_USR(62)" LOC = "P82" | IOSTANDARD = LVCMOS25;
|
||||
Executable
+61
@@ -0,0 +1,61 @@
|
||||
########################################################
|
||||
# Makefile for drscl executable under linux
|
||||
#
|
||||
# S. Ritt, Nov. 2016
|
||||
########################################################
|
||||
|
||||
# determine OS
|
||||
OSTYPE = $(shell uname)
|
||||
|
||||
FLAGS = -g -O3 -Wall -Wuninitialized -Wno-unused-result -DOS_LINUX
|
||||
FLAGS += -I../include -I/usr/local/include
|
||||
LIBS = -lpthread -lutil -lusb-1.0
|
||||
|
||||
OBJECTS = DRS.o averager.o musbstd.o mxml.o strlcpy.o
|
||||
EXECS = drscl drs_exam drs_exam_multi
|
||||
|
||||
ifeq ($(OSTYPE),Darwin)
|
||||
FLAGS += -DHAVE_USB -DHAVE_LIBUSB10
|
||||
LIBS += -framework IOKit -framework CoreFoundation -lobjc
|
||||
else
|
||||
FLAGS += -DHAVE_USB -DHAVE_LIBUSB10
|
||||
endif
|
||||
|
||||
all: $(EXECS)
|
||||
|
||||
drscl: $(OBJECTS) drscl.o
|
||||
$(CXX) $(FLAGS) $(OBJECTS) drscl.o -o drscl $(LIBS)
|
||||
|
||||
drs_exam: $(OBJECTS) drs_exam.o
|
||||
$(CXX) $(FLAGS) $(OBJECTS) drs_exam.o -o drs_exam $(LIBS)
|
||||
|
||||
drs_exam_multi: $(OBJECTS) drs_exam_multi.o
|
||||
$(CXX) $(FLAGS) $(OBJECTS) drs_exam_multi.o -o drs_exam_multi $(LIBS)
|
||||
|
||||
drscl.o: drscl.cpp ../include/DRS.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
drs_exam.o: drs_exam.cpp ../include/DRS.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
drs_exam_multi.o: drs_exam_multi.cpp ../include/DRS.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
musbstd.o: ../src//musbstd.c ../include/musbstd.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
DRS.o: ../src/DRS.cpp ../include/DRS.h
|
||||
$(CXX) $(FLAGS) -c $<
|
||||
|
||||
mxml.o: ../src/mxml.c ../include/mxml.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
strlcpy.o: ../src/strlcpy.c ../include/strlcpy.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
averager.o: ../src/averager.cpp ../include/averager.h
|
||||
$(CC) $(FLAGS) -c $<
|
||||
|
||||
clean:
|
||||
rm -f *.o $(EXECS)
|
||||
|
||||
@@ -0,0 +1,166 @@
|
||||
/********************************************************************\
|
||||
|
||||
Name: drs_exam.cpp
|
||||
Created by: Stefan Ritt
|
||||
|
||||
Contents: Simple example application to read out a DRS4
|
||||
evaluation board
|
||||
|
||||
$Id: drs_exam.cpp 21308 2014-04-11 14:50:16Z ritt $
|
||||
|
||||
\********************************************************************/
|
||||
|
||||
#include <math.h>
|
||||
|
||||
#ifdef _MSC_VER
|
||||
|
||||
#include <windows.h>
|
||||
|
||||
#elif defined(OS_LINUX)
|
||||
|
||||
#define O_BINARY 0
|
||||
|
||||
#include <unistd.h>
|
||||
#include <ctype.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <errno.h>
|
||||
|
||||
#define DIR_SEPARATOR '/'
|
||||
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "strlcpy.h"
|
||||
#include "DRS.h"
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
int main()
|
||||
{
|
||||
int i, j, nBoards;
|
||||
DRS *drs;
|
||||
DRSBoard *b;
|
||||
float time_array[8][1024];
|
||||
float wave_array[8][1024];
|
||||
FILE *f;
|
||||
|
||||
/* do initial scan */
|
||||
drs = new DRS();
|
||||
|
||||
/* show any found board(s) */
|
||||
for (i=0 ; i<drs->GetNumberOfBoards() ; i++) {
|
||||
b = drs->GetBoard(i);
|
||||
printf("Found DRS4 evaluation board, serial #%d, firmware revision %d\n",
|
||||
b->GetBoardSerialNumber(), b->GetFirmwareVersion());
|
||||
}
|
||||
|
||||
/* exit if no board found */
|
||||
nBoards = drs->GetNumberOfBoards();
|
||||
if (nBoards == 0) {
|
||||
printf("No DRS4 evaluation board found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* continue working with first board only */
|
||||
b = drs->GetBoard(0);
|
||||
|
||||
/* initialize board */
|
||||
b->Init();
|
||||
|
||||
/* set sampling frequency */
|
||||
b->SetFrequency(5, true);
|
||||
|
||||
/* enable transparent mode needed for analog trigger */
|
||||
b->SetTranspMode(1);
|
||||
|
||||
/* set input range to -0.5V ... +0.5V */
|
||||
b->SetInputRange(0);
|
||||
|
||||
/* use following line to set range to 0..1V */
|
||||
//b->SetInputRange(0.5);
|
||||
|
||||
/* use following line to turn on the internal 100 MHz clock connected to all channels */
|
||||
b->EnableTcal(1);
|
||||
|
||||
/* use following lines to enable hardware trigger on CH1 at 50 mV positive edge */
|
||||
if (b->GetBoardType() >= 8) { // Evaluaiton Board V4&5
|
||||
b->EnableTrigger(1, 0); // enable hardware trigger
|
||||
b->SetTriggerSource(1<<0); // set CH1 as source
|
||||
} else if (b->GetBoardType() == 7) { // Evaluation Board V3
|
||||
b->EnableTrigger(0, 1); // lemo off, analog trigger on
|
||||
b->SetTriggerSource(0); // use CH1 as source
|
||||
}
|
||||
b->SetTriggerLevel(0.05); // 0.05 V
|
||||
b->SetTriggerPolarity(false); // positive edge
|
||||
|
||||
/* use following lines to set individual trigger elvels */
|
||||
//b->SetIndividualTriggerLevel(1, 0.1);
|
||||
//b->SetIndividualTriggerLevel(2, 0.2);
|
||||
//b->SetIndividualTriggerLevel(3, 0.3);
|
||||
//b->SetIndividualTriggerLevel(4, 0.4);
|
||||
//b->SetTriggerSource(15);
|
||||
|
||||
b->SetTriggerDelayNs(0); // zero ns trigger delay
|
||||
|
||||
/* use following lines to enable the external trigger */
|
||||
//if (b->GetBoardType() == 8) { // Evaluaiton Board V4
|
||||
// b->EnableTrigger(1, 0); // enable hardware trigger
|
||||
// b->SetTriggerSource(1<<4); // set external trigger as source
|
||||
//} else { // Evaluation Board V3
|
||||
// b->EnableTrigger(1, 0); // lemo on, analog trigger off
|
||||
// }
|
||||
|
||||
/* open file to save waveforms */
|
||||
f = fopen("data.txt", "w");
|
||||
if (f == NULL) {
|
||||
perror("ERROR: Cannot open file \"data.txt\"");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* repeat ten times */
|
||||
for (j=0 ; j<10 ; j++) {
|
||||
|
||||
/* start board (activate domino wave) */
|
||||
b->StartDomino();
|
||||
|
||||
/* wait for trigger */
|
||||
printf("Waiting for trigger...");
|
||||
|
||||
fflush(stdout);
|
||||
while (b->IsBusy());
|
||||
|
||||
/* read all waveforms */
|
||||
b->TransferWaves(0, 8);
|
||||
|
||||
/* read time (X) array of first channel in ns */
|
||||
b->GetTime(0, 0, b->GetTriggerCell(0), time_array[0]);
|
||||
|
||||
/* decode waveform (Y) array of first channel in mV */
|
||||
b->GetWave(0, 0, wave_array[0]);
|
||||
|
||||
/* read time (X) array of second channel in ns
|
||||
Note: On the evaluation board input #1 is connected to channel 0 and 1 of
|
||||
the DRS chip, input #2 is connected to channel 2 and 3 and so on. So to
|
||||
get the input #2 we have to read DRS channel #2, not #1. */
|
||||
b->GetTime(0, 2, b->GetTriggerCell(0), time_array[1]);
|
||||
|
||||
/* decode waveform (Y) array of second channel in mV */
|
||||
b->GetWave(0, 2, wave_array[1]);
|
||||
|
||||
/* Save waveform: X=time_array[i], Yn=wave_array[n][i] */
|
||||
fprintf(f, "Event #%d ----------------------\n t1[ns] u1[mV] t2[ns] u2[mV]\n", j);
|
||||
for (i=0 ; i<1024 ; i++)
|
||||
fprintf(f, "%7.3f %7.1f %7.3f %7.1f\n", time_array[0][i], wave_array[0][i], time_array[1][i], wave_array[1][i]);
|
||||
|
||||
/* print some progress indication */
|
||||
printf("\rEvent #%d read successfully\n", j);
|
||||
}
|
||||
|
||||
fclose(f);
|
||||
|
||||
/* delete DRS object -> close USB connection */
|
||||
delete drs;
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
|
||||
Microsoft Visual Studio Solution File, Format Version 11.00
|
||||
# Visual Studio 2010
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "drs_exam", "drs_exam.vcxproj", "{0A260864-8525-423F-984D-34C5BE6EDE0A}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
Release|Win32 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{0A260864-8525-423F-984D-34C5BE6EDE0A}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{0A260864-8525-423F-984D-34C5BE6EDE0A}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{0A260864-8525-423F-984D-34C5BE6EDE0A}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{0A260864-8525-423F-984D-34C5BE6EDE0A}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
@@ -0,0 +1,249 @@
|
||||
<?xml version="1.0" encoding="Windows-1252"?>
|
||||
<VisualStudioProject
|
||||
ProjectType="Visual C++"
|
||||
Version="9.00"
|
||||
Name="drs_exam"
|
||||
ProjectGUID="{0A260864-8525-423F-984D-34C5BE6EDE0A}"
|
||||
TargetFrameworkVersion="131072"
|
||||
>
|
||||
<Platforms>
|
||||
<Platform
|
||||
Name="Win32"
|
||||
/>
|
||||
</Platforms>
|
||||
<ToolFiles>
|
||||
</ToolFiles>
|
||||
<Configurations>
|
||||
<Configuration
|
||||
Name="Release|Win32"
|
||||
OutputDirectory=".\Release"
|
||||
IntermediateDirectory=".\Release"
|
||||
ConfigurationType="1"
|
||||
InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
|
||||
UseOfMFC="0"
|
||||
ATLMinimizesCRunTimeLibraryUsage="false"
|
||||
CharacterSet="2"
|
||||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXMLDataGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCWebServiceProxyGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCMIDLTool"
|
||||
TypeLibraryName=".\Release/drs_exam.tlb"
|
||||
HeaderFileName=""
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
Optimization="2"
|
||||
InlineFunctionExpansion="1"
|
||||
AdditionalIncludeDirectories="C:\meg\online\drivers\drs;c:\midas\include;c:\mxml;c:\midas\drivers\vme\sis3100\windows\;c:\meg\online\drivers\ace\;c:\meg\online\drivers\drs\libusb\include;"
|
||||
PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE;HAVE_USB;HAVE_LIBUSB;CF_VIA_USBx;_CRT_SECURE_NO_DEPRECATE;_CRT_NONSTDC_NO_DEPRECATE"
|
||||
StringPooling="true"
|
||||
RuntimeLibrary="0"
|
||||
EnableFunctionLevelLinking="true"
|
||||
UsePrecompiledHeader="0"
|
||||
PrecompiledHeaderFile=".\Release/drs_exam.pch"
|
||||
AssemblerListingLocation=".\Release/"
|
||||
ObjectFile=".\Release/"
|
||||
ProgramDataBaseFileName=".\Release/"
|
||||
WarningLevel="3"
|
||||
SuppressStartupBanner="true"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManagedResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCResourceCompilerTool"
|
||||
PreprocessorDefinitions="NDEBUG"
|
||||
Culture="2055"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPreLinkEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCLinkerTool"
|
||||
OutputFile=".\Release/drs_exam.exe"
|
||||
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@@ -0,0 +1,178 @@
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||||
/********************************************************************\
|
||||
|
||||
Name: drs_exam_multi.cpp
|
||||
Created by: Stefan Ritt
|
||||
|
||||
Contents: Simple example application to read out a several
|
||||
DRS4 evaluation board in daisy-chain mode
|
||||
|
||||
$Id: drs_exam_multi.cpp 21509 2014-10-15 10:11:36Z ritt $
|
||||
|
||||
\********************************************************************/
|
||||
|
||||
#include <math.h>
|
||||
|
||||
#ifdef _MSC_VER
|
||||
|
||||
#include <windows.h>
|
||||
|
||||
#elif defined(OS_LINUX)
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||||
|
||||
#define O_BINARY 0
|
||||
|
||||
#include <unistd.h>
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||||
#include <ctype.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <errno.h>
|
||||
|
||||
#define DIR_SEPARATOR '/'
|
||||
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "strlcpy.h"
|
||||
#include "DRS.h"
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
int main()
|
||||
{
|
||||
int i, j, k;
|
||||
DRS *drs;
|
||||
DRSBoard *b, *mb;
|
||||
float time_array[8][1024];
|
||||
float wave_array[8][1024];
|
||||
FILE *f;
|
||||
|
||||
/* do initial scan, sort boards accordning to their serial numbers */
|
||||
drs = new DRS();
|
||||
drs->SortBoards();
|
||||
|
||||
/* show any found board(s) */
|
||||
for (i=0 ; i<drs->GetNumberOfBoards() ; i++) {
|
||||
b = drs->GetBoard(i);
|
||||
printf("Found DRS4 evaluation board, serial #%d, firmware revision %d\n",
|
||||
b->GetBoardSerialNumber(), b->GetFirmwareVersion());
|
||||
if (b->GetBoardType() < 8) {
|
||||
printf("Found pre-V4 board, aborting\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* exit if no board found */
|
||||
if (drs->GetNumberOfBoards() == 0) {
|
||||
printf("No DRS4 evaluation board found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* exit if only one board found */
|
||||
if (drs->GetNumberOfBoards() == 1) {
|
||||
printf("Only one DRS4 evaluation board found, please use drs_exam program\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* use first board with highest serial number as the master board */
|
||||
mb = drs->GetBoard(0);
|
||||
|
||||
/* common configuration for all boards */
|
||||
for (i=0 ; i<drs->GetNumberOfBoards() ; i++) {
|
||||
b = drs->GetBoard(i);
|
||||
|
||||
/* initialize board */
|
||||
b->Init();
|
||||
|
||||
/* select external reference clock for slave modules */
|
||||
/* NOTE: this only works if the clock chain is connected */
|
||||
if (i > 0) {
|
||||
if (b->GetFirmwareVersion() >= 21260) { // this only works with recent firmware versions
|
||||
if (b->GetScaler(5) > 300000) // check if external clock is connected
|
||||
b->SetRefclk(true); // switch to external reference clock
|
||||
}
|
||||
}
|
||||
|
||||
/* set sampling frequency */
|
||||
b->SetFrequency(5, true);
|
||||
|
||||
/* set input range to -0.5V ... +0.5V */
|
||||
b->SetInputRange(0);
|
||||
|
||||
/* enable hardware trigger */
|
||||
b->EnableTrigger(1, 0);
|
||||
|
||||
if (i == 0) {
|
||||
/* master board: enable hardware trigger on CH1 at 50 mV positive edge */
|
||||
b->SetTranspMode(1);
|
||||
b->SetTriggerSource(1<<0); // set CH1 as source
|
||||
b->SetTriggerLevel(0.05); // 50 mV
|
||||
b->SetTriggerPolarity(false); // positive edge
|
||||
b->SetTriggerDelayNs(0); // zero ns trigger delay
|
||||
} else {
|
||||
/* slave boards: enable hardware trigger on Trigger IN */
|
||||
b->SetTriggerSource(1<<4); // set Trigger IN as source
|
||||
b->SetTriggerPolarity(false); // positive edge
|
||||
}
|
||||
}
|
||||
|
||||
/* open file to save waveforms */
|
||||
f = fopen("data.txt", "w");
|
||||
if (f == NULL) {
|
||||
perror("ERROR: Cannot open file \"data.txt\"");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* repeat ten times */
|
||||
for (i=0 ; i<10 ; i++) {
|
||||
|
||||
/* start boards (activate domino wave), master is last */
|
||||
for (j=drs->GetNumberOfBoards()-1 ; j>=0 ; j--)
|
||||
drs->GetBoard(j)->StartDomino();
|
||||
|
||||
/* wait for trigger on master board */
|
||||
printf("Waiting for trigger...");
|
||||
fflush(stdout);
|
||||
while (mb->IsBusy());
|
||||
|
||||
fprintf(f, "Event #%d =====================================================\n", j);
|
||||
|
||||
for (j=0 ; j<drs->GetNumberOfBoards() ; j++) {
|
||||
b = drs->GetBoard(j);
|
||||
if (b->IsBusy()) {
|
||||
i--; /* skip that event, must be some fake trigger */
|
||||
break;
|
||||
}
|
||||
|
||||
/* read all waveforms from all boards */
|
||||
b->TransferWaves(0, 8);
|
||||
|
||||
for (k=0 ; k<4 ; k++) {
|
||||
/* read time (X) array in ns */
|
||||
b->GetTime(0, k*2, b->GetTriggerCell(0), time_array[k]);
|
||||
|
||||
/* decode waveform (Y) arrays in mV */
|
||||
b->GetWave(0, k*2, wave_array[k]);
|
||||
}
|
||||
|
||||
/* Save waveform: X=time_array[i], Channel_n=wave_array[n][i] */
|
||||
fprintf(f, "Board #%d ---------------------------------------------------\n t1[ns] u1[mV] t2[ns] u2[mV] t3[ns] u3[mV] t4[ns] u4[mV]\n", b->GetBoardSerialNumber());
|
||||
for (k=0 ; k<1024 ; k++)
|
||||
fprintf(f, "%7.3f %7.1f %7.3f %7.1f %7.3f %7.1f %7.3f %7.1f\n",
|
||||
time_array[0][k], wave_array[0][k],
|
||||
time_array[1][k], wave_array[1][k],
|
||||
time_array[2][k], wave_array[2][k],
|
||||
time_array[3][k], wave_array[3][k]);
|
||||
}
|
||||
|
||||
/* print some progress indication */
|
||||
printf("\rEvent #%d read successfully\n", i);
|
||||
}
|
||||
|
||||
fclose(f);
|
||||
|
||||
printf("Program finished.\n");
|
||||
|
||||
/* delete DRS object -> close USB connection */
|
||||
delete drs;
|
||||
}
|
||||
@@ -0,0 +1,305 @@
|
||||
// !$*UTF8*$!
|
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{
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archiveVersion = 1;
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classes = {
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};
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objectVersion = 46;
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objects = {
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/* Begin PBXBuildFile section */
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/********************************************************************\
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Name: drs_scaler.cpp
|
||||
Created by: Stefan Ritt
|
||||
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||||
Contents: Wrapper function to read scalers via Labview
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$Id: drs_scaler.cpp 21293 2014-03-19 16:36:44Z ritt $
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\********************************************************************/
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#endif
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{
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|
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|
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|
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|
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|
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/*------------------------------------------------------------------*/
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int main()
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{
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unsigned int s1, s2, s3, s4;
|
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|
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scaler(&s1, &s2, &s3, &s4);
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printf("%d %d %d %d\n", s1, s2, s3, s4);
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return 1;
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GCC_C_LANGUAGE_STANDARD = gnu99;
|
||||
GCC_ENABLE_OBJC_EXCEPTIONS = YES;
|
||||
GCC_NO_COMMON_BLOCKS = YES;
|
||||
GCC_VERSION = com.apple.compilers.llvm.clang.1_0;
|
||||
GCC_WARN_64_TO_32_BIT_CONVERSION = YES;
|
||||
GCC_WARN_ABOUT_MISSING_PROTOTYPES = YES;
|
||||
GCC_WARN_ABOUT_RETURN_TYPE = YES;
|
||||
GCC_WARN_UNDECLARED_SELECTOR = YES;
|
||||
GCC_WARN_UNINITIALIZED_AUTOS = YES;
|
||||
GCC_WARN_UNUSED_FUNCTION = YES;
|
||||
GCC_WARN_UNUSED_VARIABLE = YES;
|
||||
MACOSX_DEPLOYMENT_TARGET = 10.7;
|
||||
SDKROOT = macosx;
|
||||
};
|
||||
name = Release;
|
||||
};
|
||||
D5446436141E1BB40027AF52 /* Debug */ = {
|
||||
isa = XCBuildConfiguration;
|
||||
buildSettings = {
|
||||
GCC_PREPROCESSOR_DEFINITIONS = (
|
||||
"DEBUG=1",
|
||||
"$(inherited)",
|
||||
OS_LINUX,
|
||||
HAVE_USB,
|
||||
HAVE_LIBUSB10,
|
||||
);
|
||||
GCC_WARN_64_TO_32_BIT_CONVERSION = NO;
|
||||
HEADER_SEARCH_PATHS = (
|
||||
/usr/local/include,
|
||||
/drs4eb/software/include,
|
||||
);
|
||||
OTHER_LDFLAGS = (
|
||||
"-L/usr/local/lib",
|
||||
"-lusb-1.0",
|
||||
"-framework",
|
||||
IOKit,
|
||||
"-framework",
|
||||
Carbon,
|
||||
);
|
||||
PRELINK_LIBS = "";
|
||||
PRODUCT_NAME = "$(TARGET_NAME)";
|
||||
};
|
||||
name = Debug;
|
||||
};
|
||||
D5446437141E1BB40027AF52 /* Release */ = {
|
||||
isa = XCBuildConfiguration;
|
||||
buildSettings = {
|
||||
GCC_WARN_64_TO_32_BIT_CONVERSION = NO;
|
||||
HEADER_SEARCH_PATHS = (
|
||||
/usr/local/include,
|
||||
/drs4eb/software/include,
|
||||
);
|
||||
OTHER_LDFLAGS = (
|
||||
"-L/usr/local/lib",
|
||||
"-lusb-1.0",
|
||||
"-framework",
|
||||
IOKit,
|
||||
"-framework",
|
||||
Carbon,
|
||||
);
|
||||
PRELINK_LIBS = "";
|
||||
PRODUCT_NAME = "$(TARGET_NAME)";
|
||||
};
|
||||
name = Release;
|
||||
};
|
||||
/* End XCBuildConfiguration section */
|
||||
|
||||
/* Begin XCConfigurationList section */
|
||||
D5446425141E1BB40027AF52 /* Build configuration list for PBXProject "drscl" */ = {
|
||||
isa = XCConfigurationList;
|
||||
buildConfigurations = (
|
||||
D5446433141E1BB40027AF52 /* Debug */,
|
||||
D5446434141E1BB40027AF52 /* Release */,
|
||||
);
|
||||
defaultConfigurationIsVisible = 0;
|
||||
defaultConfigurationName = Release;
|
||||
};
|
||||
D5446435141E1BB40027AF52 /* Build configuration list for PBXNativeTarget "drscl" */ = {
|
||||
isa = XCConfigurationList;
|
||||
buildConfigurations = (
|
||||
D5446436141E1BB40027AF52 /* Debug */,
|
||||
D5446437141E1BB40027AF52 /* Release */,
|
||||
);
|
||||
defaultConfigurationIsVisible = 0;
|
||||
defaultConfigurationName = Release;
|
||||
};
|
||||
/* End XCConfigurationList section */
|
||||
};
|
||||
rootObject = D5446422141E1BB40027AF52 /* Project object */;
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* AboutDialog.cpp
|
||||
* About Dialog class
|
||||
* $Id: AboutDialog.cpp 21911 2015-11-23 07:31:04Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
extern char svn_revision[];
|
||||
extern char drsosc_version[];
|
||||
|
||||
AboutDialog::AboutDialog(wxWindow* parent)
|
||||
:
|
||||
AboutDialog_fb( parent )
|
||||
{
|
||||
wxString str;
|
||||
char d[80];
|
||||
|
||||
str.Printf(wxT("Version %s"), (const wxChar*)wxString::FromAscii(drsosc_version));
|
||||
m_stVersion->SetLabel(str);
|
||||
|
||||
strcpy(d, svn_revision+23);
|
||||
d[10] = 0;
|
||||
str.Printf(wxT("Build %d, %s"), atoi(svn_revision+17), (const wxChar*)wxString::FromAscii(d));
|
||||
m_stBuild->SetLabel(str);
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
#ifndef __AboutDialog__
|
||||
#define __AboutDialog__
|
||||
|
||||
// $Id: AboutDialog.h 14011 2009-08-06 11:34:04Z ritt $
|
||||
|
||||
/**
|
||||
@file
|
||||
Subclass of AboutDialog_fb, which is generated by wxFormBuilder.
|
||||
*/
|
||||
|
||||
/** Implementing ConfigDialog_fb */
|
||||
class AboutDialog : public AboutDialog_fb
|
||||
{
|
||||
public:
|
||||
/** Constructor */
|
||||
AboutDialog( wxWindow* parent );
|
||||
};
|
||||
|
||||
#endif // __AboutDialog__
|
||||
@@ -0,0 +1,581 @@
|
||||
/*
|
||||
* ConfigDialog.cpp
|
||||
* Modeless Configuration Dialog class
|
||||
* $Id: ConfigDialog.cpp 22325 2016-10-07 14:05:49Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
ConfigDialog::ConfigDialog( wxWindow* parent )
|
||||
:
|
||||
ConfigDialog_fb( parent )
|
||||
{
|
||||
m_frame = (DOFrame *)parent;
|
||||
m_osci = m_frame->GetOsci();
|
||||
|
||||
fCalMode = 0;
|
||||
m_board = 0;
|
||||
m_firstChannel = 0;
|
||||
m_chnSection = m_frame->GetOsci()->GetChnSection();
|
||||
|
||||
if (m_frame->GetMultiBoard()) {
|
||||
m_cbMulti->SetValue(true);
|
||||
m_cbTrgCorr->SetValue(false);
|
||||
m_cbTrgCorr->Enable(false);
|
||||
m_frame->SetDisplayTrgCorr(false);
|
||||
}
|
||||
|
||||
m_cbClkOn->SetValue(m_frame->GetClkOn());
|
||||
if (m_osci->GetNumberOfBoards() == 0) {
|
||||
m_cbClkOn->SetLabel(wxT("Connect reference clock to channel #4"));
|
||||
} else {
|
||||
if (m_frame->GetOsci()->GetBoard(0)->GetBoardType() == 9)
|
||||
m_cbClkOn->SetLabel(wxT("Connect reference clock to all channels"));
|
||||
else
|
||||
m_cbClkOn->SetLabel(wxT("Connect reference clock to channel #4"));
|
||||
}
|
||||
|
||||
if (m_frame->GetRange() == 0) {
|
||||
m_rbRange->SetSelection(0);
|
||||
m_slCal->SetRange(-500, 500);
|
||||
} else if (m_frame->GetRange() == 0.45) {
|
||||
m_rbRange->SetSelection(1);
|
||||
m_slCal->SetRange(-50, 950);
|
||||
} else if (m_frame->GetRange() == 0.5) {
|
||||
m_rbRange->SetSelection(2);
|
||||
m_slCal->SetRange(-0, 1000);
|
||||
}
|
||||
|
||||
if (m_chnSection == 2)
|
||||
m_rbChHalf->SetSelection(2);
|
||||
|
||||
wxString wxstr;
|
||||
wxstr.Printf(wxT("%1.4lg"), m_frame->GetReqSamplingSpeed());
|
||||
m_tbFreq->SetValue(wxstr);
|
||||
wxstr.Printf(wxT("%1.4lg GSPS"), m_frame->GetActSamplingSpeed());
|
||||
m_stActFreq->SetLabel(wxstr);
|
||||
|
||||
m_cbLocked->SetValue(m_frame->IsFreqLocked());
|
||||
m_cbSpikes->SetValue(m_frame->GetSpikeRemovel());
|
||||
|
||||
if (m_osci->GetNumberOfBoards() == 0) {
|
||||
m_cbTCalOn->SetValue(true);
|
||||
m_cbTCalOn->Enable(true);
|
||||
} else {
|
||||
m_cbTCalOn->SetValue(m_frame->GetOsci()->IsTCalibrated());
|
||||
m_cbTCalOn->Enable(m_frame->GetOsci()->IsTCalibrated());
|
||||
}
|
||||
|
||||
PopulateBoards();
|
||||
}
|
||||
|
||||
void ConfigDialog::PopulateBoards()
|
||||
{
|
||||
wxString wxstr;
|
||||
|
||||
m_cbBoard->Clear();
|
||||
|
||||
for (int i=0 ; i<m_osci->GetNumberOfBoards() ; i++) {
|
||||
DRSBoard *b = m_osci->GetBoard(i);
|
||||
|
||||
#ifdef HAVE_VME
|
||||
if (b->GetTransport() == 1)
|
||||
wxstr.Printf(wxT("VME DRS%d slot %2d%s serial %d"),
|
||||
b->GetDRSType(), (b->GetSlotNumber() >> 1)+2,
|
||||
((b->GetSlotNumber() & 1) == 0) ? "up" : "lo",
|
||||
b->GetBoardSerialNumber());
|
||||
else
|
||||
#endif
|
||||
wxstr.Printf(wxT("USB DRS%d serial %d"), b->GetDRSType(), b->GetBoardSerialNumber());
|
||||
|
||||
m_cbBoard->Append(wxstr);
|
||||
}
|
||||
|
||||
m_cbBoard->Select(m_board);
|
||||
UpdateControls();
|
||||
}
|
||||
|
||||
void ConfigDialog::UpdateControls()
|
||||
{
|
||||
if (m_osci->GetNumberOfBoards() < 2) {
|
||||
m_cbMulti->Enable(false);
|
||||
} else
|
||||
m_cbMulti->Enable(true);
|
||||
|
||||
if (m_osci->GetNumberOfBoards() == 0 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardType() == 5 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardType() == 7 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardType() == 8 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardType() == 9) {
|
||||
if (m_osci->GetNumberOfBoards() > 0) {
|
||||
m_cbExtRefclk->Enable(m_osci->GetBoard(m_board)->GetBoardType() == 8 || m_osci->GetBoard(m_board)->GetBoardType() == 9);
|
||||
m_cbExtRefclk->Show(m_osci->GetBoard(m_board)->GetBoardType() == 8 || m_osci->GetBoard(m_board)->GetBoardType() == 9);
|
||||
}
|
||||
} else {
|
||||
m_cbExtRefclk->Enable(true);
|
||||
m_cbExtRefclk->Show(true);
|
||||
}
|
||||
|
||||
if (m_osci->GetNumberOfBoards() > 0) {
|
||||
if (m_osci->GetBoard(m_board)->GetBoardType() == 5 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardType() == 6 ||
|
||||
m_osci->GetBoard(m_board)->Is2048ModeCapable()) {
|
||||
m_rbChHalf->Enable(true);
|
||||
} else {
|
||||
if (m_osci->GetBoard(m_board)->GetBoardSerialNumber() == 2146 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardSerialNumber() == 2205 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardSerialNumber() == 2208 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardSerialNumber() == 2253 ||
|
||||
m_osci->GetBoard(m_board)->GetBoardSerialNumber() == 2287) {
|
||||
m_rbChHalf->Enable(true); // special boards modified for RFBeta & Slow Muons
|
||||
} else {
|
||||
m_rbChHalf->Enable(false);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
m_rbChHalf->Enable(false);
|
||||
}
|
||||
|
||||
if (m_osci->GetNumberOfBoards() == 0) {
|
||||
m_cbTCalOn->SetValue(true);
|
||||
m_cbTCalOn->Enable(true);
|
||||
} else {
|
||||
m_cbCalibrated->SetValue(m_frame->GetOsci()->IsVCalibrated());
|
||||
m_cbCalibrated->Enable(m_frame->GetOsci()->IsVCalibrated());
|
||||
m_cbCalibrated2->SetValue(m_frame->GetOsci()->IsVCalibrated());
|
||||
m_cbCalibrated2->Enable(m_frame->GetOsci()->IsVCalibrated());
|
||||
|
||||
m_cbTCalOn->SetValue(m_frame->GetOsci()->IsTCalibrated());
|
||||
m_cbTCalOn->Enable(m_frame->GetOsci()->IsTCalibrated());
|
||||
m_cbExtRefclk->SetValue(m_osci->GetBoard(m_board)->GetRefclk() == 1);
|
||||
|
||||
if ((m_osci->GetBoard(m_board)->GetBoardType() == 8 || m_osci->GetBoard(m_board)->GetBoardType() == 9)
|
||||
&& (!m_osci->IsMultiBoard() || m_board == 0))
|
||||
m_frame->EnableTriggerConfig(true);
|
||||
else
|
||||
m_frame->EnableTriggerConfig(false);
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnBoardSelect( wxCommandEvent& event )
|
||||
{
|
||||
if (event.GetId() == ID_MULTI) {
|
||||
if (m_cbMulti->IsChecked()) {
|
||||
wxString str;
|
||||
|
||||
str.Printf(wxT("In a multi-board configuration, the Trigger and Clock singals must be conected. Please read the manual for details. Turn on multi-board mode?"));
|
||||
|
||||
if (wxMessageBox(str, wxT("DRS Oscilloscope Info"), wxOK | wxCANCEL | wxICON_EXCLAMATION) == wxOK) {
|
||||
m_osci->Enable(false);
|
||||
m_osci->SetMultiBoard(true);
|
||||
for (int i=1 ; i<m_osci->GetNumberOfBoards() ; i++) {
|
||||
DRSBoard *b = m_frame->GetOsci()->GetBoard(i);
|
||||
m_frame->SetTriggerSource(i, 4); // select external trigger
|
||||
m_frame->SetTriggerPolarity(i, false); // positive trigger
|
||||
|
||||
if (b->GetFirmwareVersion() < 21260) {
|
||||
wxMessageBox(wxT("For this operation V5 boards with firmware revision >= 21260 is required"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
} else {
|
||||
if (b->GetScaler(5) < 300000) {
|
||||
str.Printf(wxT("No clock signal connected to CLK IN of board #%d"), i);
|
||||
wxMessageBox(str, wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
m_frame->SetRefclk(i, false);
|
||||
} else {
|
||||
m_frame->SetRefclk(i, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
m_osci->Enable(true);
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_osci->SelectChannel(m_firstChannel, m_chnSection);
|
||||
m_frame->SetDisplayTrgCorr(false);
|
||||
m_cbTrgCorr->SetValue(false);
|
||||
m_cbTrgCorr->Enable(false);
|
||||
} else {
|
||||
m_cbMulti->SetValue(false);
|
||||
}
|
||||
} else {
|
||||
m_osci->Enable(false);
|
||||
m_osci->SetMultiBoard(false);
|
||||
m_osci->Enable(true);
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_osci->SelectChannel(m_firstChannel, m_chnSection);
|
||||
m_cbTrgCorr->Enable(true);
|
||||
}
|
||||
m_frame->SetMultiBoard(m_cbMulti->IsChecked());
|
||||
m_frame->SelectBoard(m_board); // cause control update
|
||||
if (!m_cbMulti->IsChecked())
|
||||
m_frame->SetSplitMode(false);
|
||||
|
||||
} else {
|
||||
m_board = m_cbBoard->GetSelection();
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_osci->SelectChannel(m_firstChannel, m_chnSection);
|
||||
m_frame->SelectBoard(m_board);
|
||||
UpdateControls();
|
||||
}
|
||||
}
|
||||
|
||||
// called from DOFrame if one selects another board
|
||||
void ConfigDialog::SelectBoard(int i)
|
||||
{
|
||||
m_board = i;
|
||||
m_cbBoard->SetSelection(i);
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_osci->SelectChannel(m_firstChannel, m_chnSection);
|
||||
m_frame->UpdateStatusBar();
|
||||
UpdateControls();
|
||||
}
|
||||
|
||||
|
||||
void ConfigDialog::OnRescan( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->EnableEPThread(false);
|
||||
m_osci->ScanBoards();
|
||||
PopulateBoards();
|
||||
if (m_board >= m_osci->GetNumberOfBoards())
|
||||
m_board = m_firstChannel = m_chnSection = 0;
|
||||
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_frame->EnableEPThread(true);
|
||||
m_frame->UpdateStatusBar();
|
||||
}
|
||||
|
||||
void ConfigDialog::OnInfo( wxCommandEvent& event )
|
||||
{
|
||||
InfoDialog id(m_frame);
|
||||
id.ShowModal();
|
||||
}
|
||||
|
||||
void ConfigDialog::OnChannelHalf( wxCommandEvent& event )
|
||||
{
|
||||
if (event.GetId() == ID_CH_HALF)
|
||||
m_chnSection = m_rbChHalf->GetSelection();
|
||||
|
||||
m_frame->SetSource(m_board, m_firstChannel, m_chnSection);
|
||||
m_osci->SelectBoard(m_board);
|
||||
m_osci->SelectChannel(m_firstChannel, m_chnSection);
|
||||
}
|
||||
|
||||
void ConfigDialog::OnInputRange( wxCommandEvent& event )
|
||||
{
|
||||
if (m_rbRange->GetSelection() == 0) {
|
||||
m_frame->GetOsci()->SetInputRange(0);
|
||||
m_frame->SetRange(0);
|
||||
m_slCal->SetRange(-500, 500);
|
||||
} else if (m_rbRange->GetSelection() == 1) {
|
||||
m_frame->GetOsci()->SetInputRange(0.45);
|
||||
m_frame->SetRange(0.45);
|
||||
m_slCal->SetRange(-50, 950);
|
||||
} else if (m_rbRange->GetSelection() == 2) {
|
||||
m_frame->GetOsci()->SetInputRange(0.5);
|
||||
m_frame->SetRange(0.5);
|
||||
m_slCal->SetRange(0, 1000);
|
||||
}
|
||||
OnCalEnter(event);
|
||||
}
|
||||
|
||||
void ConfigDialog::OnCalOn( wxCommandEvent& event )
|
||||
{
|
||||
if (event.IsChecked()) {
|
||||
m_frame->GetOsci()->SetCalibVoltage(true, m_slCal->GetValue()/1000.0);
|
||||
} else {
|
||||
m_frame->GetOsci()->SetCalibVoltage(false, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnCalEnter( wxCommandEvent& event )
|
||||
{
|
||||
if (!m_teCal->IsEmpty()) {
|
||||
long value;
|
||||
m_teCal->GetValue().ToLong(&value);
|
||||
if (m_frame->GetRange() == 0) {
|
||||
if (value < -500)
|
||||
value = -500;
|
||||
if (value > 500)
|
||||
value = 500;
|
||||
} else if (m_frame->GetRange() == 0.45) {
|
||||
if (value < -50)
|
||||
value = -50;
|
||||
if (value > 950)
|
||||
value = 950;
|
||||
} else if (m_frame->GetRange() == 0.5) {
|
||||
if (value < 0)
|
||||
value = 0;
|
||||
if (value > 1000)
|
||||
value = 1000;
|
||||
}
|
||||
m_slCal->SetValue(value);
|
||||
m_teCal->SetValue(wxString::Format(wxT("%ld"), value));
|
||||
if (m_cbCalOn->IsChecked())
|
||||
m_frame->GetOsci()->SetCalibVoltage(true, value/1000.0);
|
||||
}
|
||||
|
||||
/* check for calibration */
|
||||
if (m_osci->GetNumberOfBoards() > 0 &&
|
||||
fabs(m_frame->GetRange() - m_frame->GetOsci()->GetCalibratedInputRange()) > 0.001) {
|
||||
wxString str;
|
||||
|
||||
str.Printf(wxT("This board was calibrated for an input range of\n %1.2lg V ... %1.2lg V\nYou must execute a new voltage calibration to use this board for the new input range"),
|
||||
m_frame->GetOsci()->GetCalibratedInputRange()-0.5, m_frame->GetOsci()->GetCalibratedInputRange()+0.5);
|
||||
wxMessageBox(str, wxT("DRS Oscilloscope Warning"), wxOK | wxICON_EXCLAMATION, this);
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnCalSlider( wxScrollEvent& event )
|
||||
{
|
||||
m_teCal->SetValue(wxString::Format(wxT("%d"), m_slCal->GetValue()));
|
||||
|
||||
if (m_cbCalOn->IsChecked())
|
||||
m_frame->GetOsci()->SetCalibVoltage(true, m_slCal->GetValue()/1000.0);
|
||||
|
||||
}
|
||||
|
||||
void ConfigDialog::Progress(int prog)
|
||||
{
|
||||
if (fCalMode == 1)
|
||||
m_gaugeCalVolt->SetValue(prog);
|
||||
else {
|
||||
m_gaugeCalTime->SetValue(prog);
|
||||
m_frame->SetProgress(prog);
|
||||
m_frame->Refresh();
|
||||
m_frame->Update();
|
||||
}
|
||||
|
||||
/* produces flickers with V 2.9.2
|
||||
this->Refresh();
|
||||
this->Update(); */
|
||||
}
|
||||
|
||||
void ConfigDialog::OnButtonCalVolt( wxCommandEvent& event )
|
||||
{
|
||||
fCalMode = 1;
|
||||
if (m_frame->GetOsci()->GetNumberOfBoards()) {
|
||||
|
||||
m_frame->GetTimer()->Stop();
|
||||
m_frame->GetOsci()->Enable(false); // turn off readout thread
|
||||
|
||||
DRSBoard *b = m_frame->GetOsci()->GetCurrentBoard();
|
||||
|
||||
if (b->GetTransport() == TR_USB2 && b->GetBoardType() == 6) {
|
||||
wxMessageBox(wxT("Voltage calibration not possible with Mezzanine Board through USB"),
|
||||
wxT("DRS Oscilloscope Error"), wxOK | wxICON_STOP, this);
|
||||
return;
|
||||
}
|
||||
|
||||
wxMessageBox(wxT("Please disconnect any signal from input to continue calibration"),
|
||||
wxT("DRS Oscilloscope Info"), wxOK | wxICON_INFORMATION, this);
|
||||
m_frame->Refresh();
|
||||
m_frame->Update();
|
||||
|
||||
/* remember current settings */
|
||||
double acalVolt = b->GetAcalVolt();
|
||||
int acalMode = b->GetAcalMode();
|
||||
int tcalFreq = b->GetTcalFreq();
|
||||
int tcalLevel = b->GetTcalLevel();
|
||||
int tcalSource = b->GetTcalSource();
|
||||
int flag1 = b->GetTriggerEnable(0);
|
||||
int flag2 = b->GetTriggerEnable(1);
|
||||
int trgSource = b->GetTriggerSource();
|
||||
int trgDelay = b->GetTriggerDelay();
|
||||
double range = b->GetInputRange();
|
||||
int config = b->GetReadoutChannelConfig();
|
||||
int casc = b->GetChannelCascading();
|
||||
|
||||
wxBusyCursor cursor;
|
||||
b->CalibrateVolt(this);
|
||||
|
||||
/* restore old values */
|
||||
b->EnableAcal(acalMode, acalVolt);
|
||||
b->EnableTcal(tcalFreq, tcalLevel);
|
||||
b->SelectClockSource(tcalSource);
|
||||
b->EnableTrigger(flag1, flag2);
|
||||
b->SetTriggerSource(trgSource);
|
||||
b->SetTriggerDelayPercent(trgDelay);
|
||||
b->SetInputRange(range);
|
||||
if (casc == 2)
|
||||
b->SetChannelConfig(config, 8, 4);
|
||||
else
|
||||
b->SetChannelConfig(config, 8, 8);
|
||||
|
||||
if (b->GetBoardType() == 5)
|
||||
b->SetTranspMode(1); // Evaluation board with build-in trigger
|
||||
else
|
||||
b->SetTranspMode(1); // VPC Mezzanine board
|
||||
|
||||
UpdateControls();
|
||||
|
||||
m_frame->GetTimer()->Start(100);
|
||||
m_frame->GetOsci()->Start();
|
||||
m_frame->GetOsci()->Enable(true);
|
||||
}
|
||||
Progress(0);
|
||||
}
|
||||
|
||||
void ConfigDialog::OnButtonCalTime( wxCommandEvent& event )
|
||||
{
|
||||
fCalMode = 2;
|
||||
if (m_frame->GetOsci()->GetNumberOfBoards()) {
|
||||
if (m_frame->GetOsci()->GetCurrentBoard()->GetFirmwareVersion() < 13279)
|
||||
wxMessageBox(wxT("Firmware revision 13279 or later\nrequired for timing calibration"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
else if (m_frame->GetOsci()->GetInputRange() != 0)
|
||||
wxMessageBox(wxT("Timing calibration can only be done\nat the -0.5V to +0.5V input range"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
|
||||
else {
|
||||
|
||||
DRSBoard *b = m_frame->GetOsci()->GetCurrentBoard();
|
||||
m_frame->GetOsci()->Enable(false); // turn off readout thread
|
||||
|
||||
/* remember current settings */
|
||||
double acalVolt = b->GetAcalVolt();
|
||||
int acalMode = b->GetAcalMode();
|
||||
int tcalFreq = b->GetTcalFreq();
|
||||
int tcalLevel = b->GetTcalLevel();
|
||||
int tcalSource = b->GetTcalSource();
|
||||
int flag1 = b->GetTriggerEnable(0);
|
||||
int flag2 = b->GetTriggerEnable(1);
|
||||
int trgSource = b->GetTriggerSource();
|
||||
int trgDelay = b->GetTriggerDelay();
|
||||
double range = b->GetInputRange();
|
||||
int config = b->GetReadoutChannelConfig();
|
||||
|
||||
m_frame->SetPaintMode(kPMTimeCalibration);
|
||||
|
||||
wxBusyCursor cursor;
|
||||
int status = b->CalibrateTiming(this);
|
||||
|
||||
if (!status)
|
||||
wxMessageBox(wxT("Error performing timing calibration, please check waveforms and redo voltage calibration."),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
else
|
||||
wxMessageBox(wxT("Timing calibration successfully finished."),
|
||||
wxT("DRS Oscilloscope"), wxOK, this);
|
||||
|
||||
m_frame->SetPaintMode(kPMWaveform);
|
||||
|
||||
/* restore old values */
|
||||
b->EnableAcal(acalMode, acalVolt);
|
||||
b->EnableTcal(tcalFreq, tcalLevel);
|
||||
b->SelectClockSource(tcalSource);
|
||||
b->EnableTrigger(flag1, flag2);
|
||||
b->SetTriggerSource(trgSource);
|
||||
b->SetTriggerDelayPercent(trgDelay);
|
||||
b->SetInputRange(range);
|
||||
b->SetChannelConfig(config, 8, 8);
|
||||
|
||||
if (b->GetBoardType() == 5)
|
||||
b->SetTranspMode(1); // Evaluation board with build-in trigger
|
||||
else
|
||||
b->SetTranspMode(1); // VPC Mezzanine board
|
||||
|
||||
FreqChange(); // update enable flag for timing calibration check box
|
||||
m_frame->GetTimer()->Start(100);
|
||||
m_frame->GetOsci()->Start();
|
||||
m_frame->GetOsci()->Enable(true);
|
||||
}
|
||||
Progress(0);
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnClkOn( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetClkOn(event.IsChecked());
|
||||
}
|
||||
|
||||
void ConfigDialog::OnDateTime( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayDateTime(event.IsChecked());
|
||||
}
|
||||
|
||||
void ConfigDialog::OnShowGrid( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayShowGrid(event.IsChecked());
|
||||
}
|
||||
|
||||
void ConfigDialog::OnDisplayWaveforms( wxCommandEvent& event )
|
||||
{
|
||||
if (event.GetId() == ID_DISP_CALIBRATED)
|
||||
m_frame->SetDisplayCalibrated(event.IsChecked());
|
||||
if (event.GetId() == ID_DISP_CALIBRATED2)
|
||||
m_frame->SetDisplayCalibrated2(event.IsChecked());
|
||||
if (event.GetId() == ID_DISP_ROTATED)
|
||||
m_frame->SetDisplayRotated(event.IsChecked());
|
||||
if (event.GetId() == ID_DISP_TCALIBRATED)
|
||||
m_frame->SetDisplayTCalOn(event.IsChecked());
|
||||
if (event.GetId() == ID_DISP_TRGCORR)
|
||||
m_frame->SetDisplayTrgCorr(event.IsChecked());
|
||||
if (event.GetId() == ID_REFCLK) {
|
||||
if (event.IsChecked()) {
|
||||
// check if clock is connected to CLK in
|
||||
if (m_frame->GetOsci()->GetNumberOfBoards() > 0) {
|
||||
if (m_frame->GetOsci()->GetCurrentBoard()->GetFirmwareVersion() < 21260) {
|
||||
wxMessageBox(wxT("For this operation a V5 board with firmware revision >= 21260 is required"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
m_cbExtRefclk->SetValue(false);
|
||||
} else {
|
||||
if (m_frame->GetOsci()->GetScaler(5) < 300000) {
|
||||
wxMessageBox(wxT("No clock signal connected to CLK IN"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
m_cbExtRefclk->SetValue(false);
|
||||
} else
|
||||
m_frame->SetRefclk(m_board, true);
|
||||
}
|
||||
}
|
||||
} else
|
||||
m_frame->SetRefclk(m_board, false);
|
||||
FreqChange();
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnRemoveSpikes( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetSpikeRemoval(event.IsChecked());
|
||||
}
|
||||
|
||||
void ConfigDialog::FreqChange()
|
||||
{
|
||||
wxString wxstr;
|
||||
wxstr.Printf(wxT("%1.4lg"), m_frame->GetReqSamplingSpeed());
|
||||
m_tbFreq->SetValue(wxstr);
|
||||
wxstr.Printf(wxT("%1.4lg GSPS"), m_frame->GetActSamplingSpeed());
|
||||
m_stActFreq->SetLabel(wxstr);
|
||||
|
||||
if (m_osci->GetNumberOfBoards() == 0) {
|
||||
m_cbTCalOn->SetValue(true);
|
||||
m_cbTCalOn->Enable(true);
|
||||
} else {
|
||||
m_cbTCalOn->SetValue(m_frame->GetOsci()->IsTCalibrated());
|
||||
m_cbTCalOn->Enable(m_frame->GetOsci()->IsTCalibrated());
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnFreq( wxCommandEvent& event )
|
||||
{
|
||||
wxString wxstr = m_tbFreq->GetValue();
|
||||
double freq = 0;
|
||||
wxstr.ToDouble(&freq);
|
||||
m_frame->SetSamplingSpeed(freq);
|
||||
wxstr.Printf(wxT("%1.4lg GSPS"), m_frame->GetActSamplingSpeed());
|
||||
m_stActFreq->SetLabel(wxstr);
|
||||
|
||||
if (m_osci->GetNumberOfBoards() == 0) {
|
||||
m_cbTCalOn->SetValue(true);
|
||||
m_cbTCalOn->Enable(true);
|
||||
} else {
|
||||
m_cbTCalOn->SetValue(m_frame->GetOsci()->IsTCalibrated());
|
||||
m_cbTCalOn->Enable(m_frame->GetOsci()->IsTCalibrated());
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigDialog::OnLock( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetFreqLock(event.IsChecked());
|
||||
}
|
||||
|
||||
void ConfigDialog::OnClose( wxCommandEvent& event )
|
||||
{
|
||||
this->Hide();
|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
#ifndef __ConfigDialog__
|
||||
#define __ConfigDialog__
|
||||
|
||||
// $Id: ConfigDialog.h 22325 2016-10-07 14:05:49Z ritt $
|
||||
|
||||
/**
|
||||
@file
|
||||
Subclass of ConfigDialog_fb, which is generated by wxFormBuilder.
|
||||
*/
|
||||
|
||||
class DOFrame;
|
||||
class Osci;
|
||||
|
||||
/** Implementing ConfigDialog_fb */
|
||||
class ConfigDialog : public ConfigDialog_fb, DRSCallback
|
||||
{
|
||||
protected:
|
||||
// Handlers for ConfigDialog_fb events.
|
||||
void OnBoardSelect( wxCommandEvent& event );
|
||||
void OnRescan( wxCommandEvent& event );
|
||||
void OnInfo( wxCommandEvent& event );
|
||||
void OnChannelHalf( wxCommandEvent& event );
|
||||
void OnInputRange( wxCommandEvent& event );
|
||||
void OnCalOn( wxCommandEvent& event );
|
||||
void OnCalEnter( wxCommandEvent& event );
|
||||
void OnCalSlider( wxScrollEvent& event );
|
||||
void OnClkOn( wxCommandEvent& event );
|
||||
void OnDateTime( wxCommandEvent& event );
|
||||
void OnShowGrid( wxCommandEvent& event );
|
||||
void OnDisplayWaveforms( wxCommandEvent& event );
|
||||
void OnButtonCalVolt( wxCommandEvent& event );
|
||||
void OnButtonSelect( wxCommandEvent& event );
|
||||
void UpdateCalVolt(int value);
|
||||
void OnButtonCalTime( wxCommandEvent& event );
|
||||
void OnRemoveSpikes( wxCommandEvent& event );
|
||||
void OnFreq( wxCommandEvent& event );
|
||||
void OnLock( wxCommandEvent& event );
|
||||
|
||||
void OnClose( wxCommandEvent& event );
|
||||
|
||||
int fCalMode;
|
||||
|
||||
public:
|
||||
/** Constructor */
|
||||
ConfigDialog( wxWindow* parent );
|
||||
void Progress(int prog);
|
||||
void FreqChange();
|
||||
void SelectBoard(int i);
|
||||
|
||||
private:
|
||||
DOFrame *m_frame;
|
||||
Osci *m_osci;
|
||||
|
||||
int m_board, m_firstChannel, m_chnSection;
|
||||
|
||||
void PopulateBoards(void);
|
||||
void UpdateControls(void);
|
||||
|
||||
};
|
||||
|
||||
#endif // __ConfigDialog__
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,231 @@
|
||||
#ifndef __DOFrame__
|
||||
#define __DOFrame__
|
||||
|
||||
// $Id: DOFrame.h 22327 2016-10-11 13:18:26Z ritt $
|
||||
|
||||
/**
|
||||
@file
|
||||
Subclass of DOFrame_fb, which is generated by wxFormBuilder.
|
||||
*/
|
||||
|
||||
class EPThread;
|
||||
|
||||
/** Implementing DOFrame_fb */
|
||||
class DOFrame : public DOFrame_fb
|
||||
{
|
||||
protected:
|
||||
void LoadConfig(char *error, int size);
|
||||
void SaveConfig(void);
|
||||
|
||||
// Handlers for DOFrame_fb events.
|
||||
void OnConfig(wxCommandEvent& event);
|
||||
void OnMeasure(wxCommandEvent& event);
|
||||
void OnDisplay(wxCommandEvent& event);
|
||||
void OnPrint(wxCommandEvent& event);
|
||||
void OnExit(wxCommandEvent& event);
|
||||
void OnAbout(wxCommandEvent& event);
|
||||
void OnSave(wxCommandEvent& event);
|
||||
void OnTrigger(wxCommandEvent& event);
|
||||
void OnTrgButton(wxCommandEvent& event);
|
||||
void OnTrgLevelChange(wxScrollEvent& event);
|
||||
void OnTrgDelayChange(wxScrollEvent& event);
|
||||
void OnChnOn(wxCommandEvent& event);
|
||||
void OnPosChange(wxScrollEvent& event);
|
||||
void OnScaleChange(wxCommandEvent& event);
|
||||
void OnHScaleChange(wxCommandEvent& event);
|
||||
void OnHOffsetChange(wxScrollEvent& event);
|
||||
void OnZero(wxMouseEvent& event);
|
||||
void OnTimer(wxTimerEvent& event);
|
||||
void OnCursor(wxCommandEvent& event);
|
||||
void OnSnap(wxCommandEvent& event);
|
||||
|
||||
void ProcessEvents(void);
|
||||
|
||||
public:
|
||||
DOFrame( wxWindow* parent );
|
||||
~DOFrame();
|
||||
|
||||
ConfigDialog *GetConfigDialog() { return m_configDialog; }
|
||||
wxColor GetColor(int i, bool p) { return p ? m_pcolor[i]: m_color[i]; }
|
||||
int GetAcqPerSecond() { return m_acqPerSecond; }
|
||||
double GetTrgLevel(int i) { return m_trgLevel[m_board][i]; }
|
||||
bool IsTrgConfigEnabled() { return m_trgConfigEnabled[m_board]; }
|
||||
int GetTrgMode() { return m_trgMode[m_board]; }
|
||||
int GetTrgSource(int b) { return m_trgSource[b]; }
|
||||
int GetTrgPolarity() { return m_trgNegative[m_board]; }
|
||||
double GetTrgDelay() { return m_trgDelayNs[m_board]; }
|
||||
int GetTriggerConfig() { return m_trgConfig[m_board]; }
|
||||
double GetTrgPosition(int board);
|
||||
time_t GetLastTriggerUpdate() { return m_lastTriggerUpdate; }
|
||||
bool IsIdle();
|
||||
bool GetRearm() { return m_rearm; }
|
||||
bool GetTrgCorr() { return m_trgCorr; }
|
||||
MXML_WRITER *GetWFFile() { return m_WFFile; }
|
||||
int GetWFfd() { return m_WFfd; }
|
||||
int GetNSaved() { return m_nSaved; }
|
||||
int GetNSaveMax() { return m_nSaveMax; }
|
||||
void SetRearm(bool f) { m_rearm = f; }
|
||||
void SetSamplingSpeed(double speed);
|
||||
double GetReqSamplingSpeed() { return m_reqSamplingSpeed; }
|
||||
double GetActSamplingSpeed();
|
||||
void SetTrgLevel(int i, double value);
|
||||
Osci *GetOsci() { return m_osci; }
|
||||
void SetPaintMode(int pm) { m_screen->SetPaintMode(pm); }
|
||||
void SetDisplayDateTime(bool flag);
|
||||
void SetDisplayShowGrid(bool flag);
|
||||
void SetDisplayLines(bool flag);
|
||||
void SetDisplayMode(int mode, int n);
|
||||
void SetDisplayScalers(bool flag);
|
||||
void SetDisplayCalibrated(bool flag);
|
||||
void SetDisplayCalibrated2(bool flag);
|
||||
void SetDisplayTCalOn(bool flag);
|
||||
void SetDisplayTrgCorr(bool flag);
|
||||
void SetDisplayRotated(bool flag);
|
||||
void SetCursorA(bool flag);
|
||||
void SetCursorB(bool flag);
|
||||
bool IsCursorA() { return m_cursorA; }
|
||||
bool IsCursorB() { return m_cursorB; }
|
||||
int ActiveCursor() { return m_actCursor; }
|
||||
void SetActiveCursor(int c) { m_actCursor = c; }
|
||||
bool IsSnap() { return m_snap; }
|
||||
void ToggleControls();
|
||||
void SetMeasurement(int id, bool flag);
|
||||
void SetMathDisplay(int id, bool flag);
|
||||
void SetTriggerConfig(int id, bool flag);
|
||||
void SetTriggerSource(int b, int source);
|
||||
void SetTriggerPolarity(int b, bool negative);
|
||||
void SetStat(bool flag);
|
||||
void SetHist(bool flag);
|
||||
void SetStatNStat(int n);
|
||||
int GetNStat() { return m_nStat; }
|
||||
void SetIndicator(bool flag);
|
||||
void SetClkOn(bool flag){ m_clkOn = flag; m_osci->SetClkOn(flag) ; }
|
||||
bool GetClkOn() { return m_clkOn; }
|
||||
void SelectBoard(int board);
|
||||
int GetCurrentBoard() { return m_board; }
|
||||
void SetMultiBoard(bool flag);
|
||||
void SetSplitMode(bool flag) { m_splitMode = flag; m_screen->SetSplitMode(flag); }
|
||||
bool GetMultiBoard() { return m_multiBoard; }
|
||||
void SetSource(int board, int firstChannel, int chnSection);
|
||||
void SetRefclk(int board, bool flag);
|
||||
bool GetRefclk() { return m_refClk > 0; }
|
||||
void SetRange(double range){ m_range[m_board] = range; }
|
||||
double GetRange() { return m_range[m_board]; }
|
||||
void SetSpikeRemoval(bool flag) { m_spikeRemoval = flag; m_osci->SetSpikeRemoval(flag); }
|
||||
bool GetSpikeRemovel() { return m_spikeRemoval; }
|
||||
void StatReset();
|
||||
bool IsStat() { return m_stat; }
|
||||
bool IsHist() { return m_hist; }
|
||||
bool IsIndicator() { return m_indicator; }
|
||||
wxTimer *GetTimer() { return m_timer; }
|
||||
void UpdateStatusBar();
|
||||
bool IsFirst() { return m_first; }
|
||||
void SetFreqLock(bool flag) { m_freqLocked = flag; }
|
||||
bool IsFreqLocked() { return m_freqLocked; }
|
||||
void SetProgress(int prog) { m_progress = prog; }
|
||||
int GetProgress() { return m_progress; }
|
||||
void UpdateWaveforms();
|
||||
void ClearWaveforms();
|
||||
void UpdateControls();
|
||||
float *GetWaveform(int b, int c);
|
||||
float *GetTime(int b, int c);
|
||||
void EnableTriggerConfig(bool flag);
|
||||
|
||||
bool IsMeasurement(int m, int chn);
|
||||
double GetMeasurement(int idx, double *x, double *y, int n);
|
||||
wxString GetMeasurementName(int idx) { return m_measurement[idx][0]->GetName(); }
|
||||
Measurement* GetMeasurement(int idx, int chn);
|
||||
void EvaluateMeasurements(void);
|
||||
void ChangeHScale(int delta);
|
||||
void RecalculateHOffset(double trgFrac);
|
||||
void CloseWFFile(bool errorFlag);
|
||||
void SetSaveBtn(wxString l, wxString t);
|
||||
void IncrementAcquisitions();
|
||||
void IncrementSaved();
|
||||
void EnableEPThread(bool flag);
|
||||
void SaveHisto();
|
||||
|
||||
|
||||
private:
|
||||
DECLARE_EVENT_TABLE()
|
||||
|
||||
DOScreen *m_screen;
|
||||
Osci *m_osci;
|
||||
Measurement *m_measurement[Measurement::N_MEASUREMENTS][4];
|
||||
bool m_measFlag[Measurement::N_MEASUREMENTS][4];
|
||||
bool m_stat;
|
||||
bool m_hist;
|
||||
bool m_indicator;
|
||||
bool m_first;
|
||||
|
||||
wxTimer *m_timer;
|
||||
ConfigDialog *m_configDialog;
|
||||
MeasureDialog *m_measureDialog;
|
||||
TriggerDialog *m_triggerDialog;
|
||||
DisplayDialog *m_displayDialog;
|
||||
EPThread *m_epthread;
|
||||
|
||||
float m_time[MAX_N_BOARDS][4][2048];
|
||||
float m_waveform[MAX_N_BOARDS][4][2048];
|
||||
char m_xmlError[256];
|
||||
bool m_running;
|
||||
bool m_single;
|
||||
bool m_rearm;
|
||||
double m_reqSamplingSpeed;
|
||||
bool m_freqLocked;
|
||||
bool m_oldIdle;
|
||||
|
||||
double m_trgLevel[MAX_N_BOARDS][4];
|
||||
int m_trgMode[MAX_N_BOARDS];
|
||||
bool m_trgNegative[MAX_N_BOARDS];
|
||||
int m_trgSource[MAX_N_BOARDS];
|
||||
int m_trgDelay[MAX_N_BOARDS];
|
||||
double m_trgDelayNs[MAX_N_BOARDS];
|
||||
int m_trgConfig[MAX_N_BOARDS];
|
||||
bool m_trgConfigEnabled[MAX_N_BOARDS];
|
||||
bool m_refClk[MAX_N_BOARDS];
|
||||
bool m_trgCorr;
|
||||
|
||||
int m_HScale[MAX_N_BOARDS];
|
||||
int m_HOffset[MAX_N_BOARDS];
|
||||
|
||||
bool m_chnOn[MAX_N_BOARDS][4];
|
||||
int m_chnOffset[MAX_N_BOARDS][4];
|
||||
int m_chnScale[MAX_N_BOARDS][4];
|
||||
bool m_clkOn;
|
||||
double m_range[MAX_N_BOARDS];
|
||||
bool m_spikeRemoval;
|
||||
bool m_displayScalers;
|
||||
|
||||
wxColour m_color[5];
|
||||
wxColour m_pcolor[5];
|
||||
|
||||
int m_acquisitions;
|
||||
wxStopWatch m_stopWatch;
|
||||
wxStopWatch m_stopWatch1;
|
||||
int m_acqPerSecond;
|
||||
int m_nStat;
|
||||
|
||||
time_t m_lastTriggerUpdate;
|
||||
|
||||
MXML_WRITER *m_WFFile;
|
||||
int m_WFfd;
|
||||
int m_nSaved;
|
||||
int m_nSaveMax;
|
||||
int m_actCursor;
|
||||
bool m_cursorA;
|
||||
bool m_cursorB;
|
||||
bool m_snap;
|
||||
|
||||
bool m_hideControls;
|
||||
|
||||
int m_board;
|
||||
int m_firstChannel;
|
||||
int m_chnSection;
|
||||
bool m_multiBoard;
|
||||
bool m_splitMode;
|
||||
|
||||
int m_progress;
|
||||
};
|
||||
|
||||
#endif // __DOFrame__
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,169 @@
|
||||
/*
|
||||
* DOScreen.h
|
||||
* DRS oscilloscope screen header file
|
||||
* $Id: DOScreen.h 22327 2016-10-11 13:18:26Z ritt $
|
||||
*/
|
||||
|
||||
class Osci;
|
||||
class DOFrame;
|
||||
|
||||
enum PaintModes {
|
||||
kPMWaveform,
|
||||
kPMTimeCalibration,
|
||||
};
|
||||
|
||||
class DOScreen : public wxWindow
|
||||
{
|
||||
public:
|
||||
DOScreen(wxWindow* parent, Osci *osci, DOFrame *frame);
|
||||
~DOScreen();
|
||||
void SelectBoard(int b) { m_board = b; }
|
||||
void SetChnOn(int b, int i, int value ) { m_chnon[b][i] = value; }
|
||||
int GetChnOn(int b, int i) { return m_chnon[b][i]; }
|
||||
int GetCurChn() { return m_chn; }
|
||||
bool GetSplitMode() { return m_splitMode; }
|
||||
void SetSplitMode(bool flag) { m_splitMode = flag; }
|
||||
void SetPaintMode(int pm) { m_paintMode = pm; }
|
||||
void SetPos(int b, int i, double value) { m_offset[b][i] = value; }
|
||||
void SetScale(int b, int i, int sclae);
|
||||
void SetHScale(int b, int hscale);
|
||||
void SetHScaleInc(int b, int increment);
|
||||
int GetPaintMode() { return m_paintMode; }
|
||||
void SetScreenOffset(int b, int offset) { m_screenOffset[b] = offset; }
|
||||
int GetScreenSize(int b) { return m_screenSize[b]; }
|
||||
int GetScreenOffset(int b) { return m_screenOffset[b]; }
|
||||
int GetScaleIndex(int b, int i) { return m_scale[b][i]; }
|
||||
double GetScale(int b, int i) { return m_scaleTable[m_scale[b][i]]; }
|
||||
double GetOffset(int b, int i) { return m_offset[b][i]; }
|
||||
int GetHScale(int b) { return m_hscale[b]; }
|
||||
void SetDisplayDateTime(bool flag) { m_displayDateTime = flag; }
|
||||
void SetDisplayShowGrid(bool flag) { m_displayShowGrid = flag; }
|
||||
void SetDisplayLines(bool flag) { m_displayLines = flag; }
|
||||
void SetDisplayScalers(bool flag) { m_displayScalers = flag; }
|
||||
void SetDisplayMode(int mode, int n) { m_displayMode = mode; m_displayN = n; }
|
||||
void SetMathDisplay(int id, bool flag);
|
||||
wxDC *GetDC() { return m_dc; }
|
||||
int GetX1() { return m_x1[m_board]; }
|
||||
int GetX2() { return m_x2[m_board]; }
|
||||
int GetY1() { return m_y1[m_board]; }
|
||||
int GetY2() { return m_y2[m_board]; }
|
||||
int timeToX(float t);
|
||||
int voltToY(float v);
|
||||
int voltToY(int chn, float v);
|
||||
double XToTime(int x);
|
||||
double YToVolt(int y);
|
||||
double YToVolt(int chn, int y);
|
||||
double GetT1();
|
||||
double GetT2();
|
||||
|
||||
static const int m_scaleTable[10];
|
||||
static const int m_hscaleTable[13];
|
||||
|
||||
// event handlers
|
||||
void OnPaint(wxPaintEvent& event);
|
||||
void OnSize(wxSizeEvent& event);
|
||||
|
||||
// drawing routines
|
||||
void DrawScope(wxDC& dc, wxCoord w, wxCoord h, bool printing);
|
||||
void DrawScopeBottom(wxDC& dc, int board, int x1, int y1, int width, bool printing);
|
||||
void DrawWaveforms(wxDC& dc, int wfIndex, bool printing);
|
||||
void DrawHisto(wxDC& dc, wxCoord w, wxCoord h, bool printing);
|
||||
void SaveHisto(int fd);
|
||||
void DrawTcalib(wxDC& dc, wxCoord w, wxCoord h, bool printing);
|
||||
void DrawMath(wxDC& dc, wxCoord width, wxCoord height, bool printing);
|
||||
void DrawPeriodJitter(wxDC& dc, int chn, bool printing);
|
||||
void DrawHAxis(wxDC &dc, int x1, int y1, int width,
|
||||
int minor, int major, int text, int label, int grid, double xmin, double xmax);
|
||||
|
||||
void OnMouse(wxMouseEvent& event);
|
||||
|
||||
private:
|
||||
// any class wishing to process wxWidgets events must use this macro
|
||||
DECLARE_EVENT_TABLE()
|
||||
|
||||
// pointer for main Osci object
|
||||
Osci *m_osci;
|
||||
|
||||
// pointer to DOFrame object
|
||||
DOFrame *m_frame;
|
||||
|
||||
// fonts
|
||||
wxFont m_fontNormal;
|
||||
wxFont m_fontFixed;
|
||||
wxFont m_fontFixedBold;
|
||||
|
||||
// coordinates of total scope area
|
||||
int m_sx1, m_sx2, m_sy1, m_sy2;
|
||||
|
||||
// coordinates of subpanel area
|
||||
int m_x1[MAX_N_BOARDS], m_x2[MAX_N_BOARDS], m_y1[MAX_N_BOARDS], m_y2[MAX_N_BOARDS];
|
||||
|
||||
// split mode
|
||||
bool m_splitMode;
|
||||
|
||||
// current device context
|
||||
wxDC *m_dc;
|
||||
|
||||
// stop watch for screen updates
|
||||
wxStopWatch m_sw;
|
||||
|
||||
// paing mode
|
||||
int m_paintMode;
|
||||
|
||||
// current board index for drawing
|
||||
int m_board;
|
||||
|
||||
// curent channel index
|
||||
int m_chn;
|
||||
|
||||
// offset and size of display area in ns
|
||||
int m_screenSize[MAX_N_BOARDS], m_screenOffset[MAX_N_BOARDS];
|
||||
|
||||
// cursor variables
|
||||
int m_clientHeight, m_clientWidth;
|
||||
double m_mouseX;
|
||||
double m_mouseY;
|
||||
int m_MeasX1, m_MeasX2, m_MeasY1, m_MeasY2;
|
||||
int m_BSX1[MAX_N_BOARDS], m_BSX2[MAX_N_BOARDS], m_BSY1[MAX_N_BOARDS], m_BSY2[MAX_N_BOARDS];
|
||||
|
||||
double m_xCursorA, m_xCursorB, m_yCursorA, m_yCursorB;
|
||||
int m_idxA, m_idxB;
|
||||
double m_uCursorA, m_uCursorB, m_tCursorA, m_tCursorB;
|
||||
|
||||
// waveform propoerties
|
||||
int m_chnon[MAX_N_BOARDS][4];
|
||||
double m_offset[MAX_N_BOARDS][4];
|
||||
int m_scale[MAX_N_BOARDS][4];
|
||||
int m_hscale[MAX_N_BOARDS];
|
||||
|
||||
// math display
|
||||
bool m_mathFlag[2][4];
|
||||
|
||||
// histogram coordinates
|
||||
int m_hx1, m_hy1, m_hx2, m_hy2;
|
||||
|
||||
// save button
|
||||
int m_savex1, m_savey1, m_savex2, m_savey2;
|
||||
|
||||
// histogram x axis
|
||||
bool m_histAxisAuto;
|
||||
double m_histAxisMin;
|
||||
double m_histAxisMax;
|
||||
double m_minCursor;
|
||||
double m_maxCursor;
|
||||
bool m_dragMin, m_dragMax;
|
||||
|
||||
// display properties
|
||||
bool m_displayDateTime, m_displayShowGrid, m_displayLines, m_displayScalers;
|
||||
int m_displayMode, m_displayN;
|
||||
|
||||
// grid drawing (screen vs. printer)
|
||||
void DrawDot(wxDC& dc, wxCoord w, wxCoord h, bool printing);
|
||||
|
||||
// find waveform point close to mouse cursor
|
||||
bool FindClosestWafeformPoint(int& idx_min, int& x_min, int& y_min);
|
||||
|
||||
// optional debug message
|
||||
char m_debugMsg[80];
|
||||
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
|
||||
<plist version="1.0">
|
||||
<dict/>
|
||||
</plist>
|
||||
@@ -0,0 +1,604 @@
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// C++ code generated with wxFormBuilder (version Nov 27 2012)
|
||||
// http://www.wxformbuilder.org/
|
||||
//
|
||||
// PLEASE DO "NOT" EDIT THIS FILE!
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __DRSOSC_H__
|
||||
#define __DRSOSC_H__
|
||||
|
||||
#include <wx/artprov.h>
|
||||
#include <wx/xrc/xmlres.h>
|
||||
#include <wx/string.h>
|
||||
#include <wx/bitmap.h>
|
||||
#include <wx/image.h>
|
||||
#include <wx/icon.h>
|
||||
#include <wx/menu.h>
|
||||
#include <wx/gdicmn.h>
|
||||
#include <wx/font.h>
|
||||
#include <wx/colour.h>
|
||||
#include <wx/settings.h>
|
||||
#include <wx/panel.h>
|
||||
#include <wx/slider.h>
|
||||
#include <wx/button.h>
|
||||
#include <wx/sizer.h>
|
||||
#include <wx/radiobut.h>
|
||||
#include <wx/bmpbuttn.h>
|
||||
#include <wx/statbox.h>
|
||||
#include <wx/stattext.h>
|
||||
#include <wx/radiobox.h>
|
||||
#include <wx/tglbtn.h>
|
||||
#include <wx/checkbox.h>
|
||||
#include <wx/frame.h>
|
||||
#include <wx/choice.h>
|
||||
#include <wx/textctrl.h>
|
||||
#include <wx/gauge.h>
|
||||
#include <wx/dialog.h>
|
||||
#include <wx/combobox.h>
|
||||
#include <wx/statline.h>
|
||||
#include <wx/statbmp.h>
|
||||
#include <wx/hyperlink.h>
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define ID_CURSORA 1000
|
||||
#define ID_CURSORB 1001
|
||||
#define ID_TR_LEVEL 1002
|
||||
#define ID_RUN 1003
|
||||
#define ID_SINGLE 1004
|
||||
#define ID_TR_NORMAL 1005
|
||||
#define ID_TR_AUTO 1006
|
||||
#define ID_TR_POLARITY 1007
|
||||
#define ID_TRGCFG 1008
|
||||
#define ID_TR_DELAY 1009
|
||||
#define ID_TR_SOURCE 1010
|
||||
#define ID_HSCALEDOWN 1011
|
||||
#define ID_HSCALEUP 1012
|
||||
#define ID_HOR_POS 1013
|
||||
#define ID_CHON1 1014
|
||||
#define ID_POS1 1015
|
||||
#define ID_SCALEUP1 1016
|
||||
#define ID_SCALEDN1 1017
|
||||
#define ID_CHON2 1018
|
||||
#define ID_POS2 1019
|
||||
#define ID_SCALEUP2 1020
|
||||
#define ID_SCALEDN2 1021
|
||||
#define ID_CHON3 1022
|
||||
#define ID_POS3 1023
|
||||
#define ID_SCALEUP3 1024
|
||||
#define ID_SCALEDN3 1025
|
||||
#define ID_CHON4 1026
|
||||
#define ID_POS4 1027
|
||||
#define ID_SCALEUP4 1028
|
||||
#define ID_SCALEDN4 1029
|
||||
#define ID_CONFIG 1030
|
||||
#define ID_SAVE 1031
|
||||
#define ID_MEASURE 1032
|
||||
#define ID_PRINT 1033
|
||||
#define ID_ABOUT 1034
|
||||
#define ID_EXIT 1035
|
||||
#define ID_BSEL 1036
|
||||
#define ID_MULTI 1037
|
||||
#define ID_CH_HALF 1038
|
||||
#define ID_DISP_CALIBRATED 1039
|
||||
#define ID_DISP_CALIBRATED2 1040
|
||||
#define ID_DISP_ROTATED 1041
|
||||
#define ID_DISP_TCALIBRATED 1042
|
||||
#define ID_DISP_TRGCORR 1043
|
||||
#define ID_REFCLK 1044
|
||||
#define ID_DISPSAMPLE 1045
|
||||
#define ID_DISPAVERAGE 1046
|
||||
#define ID_DISPPERSIST 1047
|
||||
#define ID_DISPNUMBER 1048
|
||||
#define ID_PJ1 1049
|
||||
#define ID_PJ2 1050
|
||||
#define ID_PJ3 1051
|
||||
#define ID_PJ4 1052
|
||||
#define ID_LEVEL1 1053
|
||||
#define ID_LEVEL2 1054
|
||||
#define ID_LEVEL3 1055
|
||||
#define ID_LEVEL4 1056
|
||||
#define ID_PKPK1 1057
|
||||
#define ID_PKPK2 1058
|
||||
#define ID_PKPK3 1059
|
||||
#define ID_PKPK4 1060
|
||||
#define ID_RMS1 1061
|
||||
#define ID_RMS2 1062
|
||||
#define ID_RMS3 1063
|
||||
#define ID_RMS4 1064
|
||||
#define ID_VS1 1065
|
||||
#define ID_VS2 1066
|
||||
#define ID_VS3 1067
|
||||
#define ID_VS4 1068
|
||||
#define ID_CHRG1 1069
|
||||
#define ID_CHRG2 1070
|
||||
#define ID_CHRG3 1071
|
||||
#define ID_CHRG4 1072
|
||||
#define ID_FREQ1 1073
|
||||
#define ID_FREQ2 1074
|
||||
#define ID_FREQ3 1075
|
||||
#define ID_FREQ4 1076
|
||||
#define ID_PERIOD1 1077
|
||||
#define ID_PERIOD2 1078
|
||||
#define ID_PERIOD3 1079
|
||||
#define ID_PERIOD4 1080
|
||||
#define ID_RISE1 1081
|
||||
#define ID_RISE2 1082
|
||||
#define ID_RISE3 1083
|
||||
#define ID_RISE4 1084
|
||||
#define ID_FALL1 1085
|
||||
#define ID_FALL2 1086
|
||||
#define ID_FALL3 1087
|
||||
#define ID_FALL4 1088
|
||||
#define ID_POSWIDTH1 1089
|
||||
#define ID_POSWIDTH2 1090
|
||||
#define ID_POSWIDTH3 1091
|
||||
#define ID_POSWIDTH4 1092
|
||||
#define ID_NEGWIDTH1 1093
|
||||
#define ID_NEGWIDTH2 1094
|
||||
#define ID_NEGWIDTH3 1095
|
||||
#define ID_NEGWIDTH4 1096
|
||||
#define ID_CHNDELAY1 1097
|
||||
#define ID_CHNDELAY2 1098
|
||||
#define ID_CHNDELAY3 1099
|
||||
#define ID_CHNDELAY4 1100
|
||||
#define ID_HS1 1101
|
||||
#define ID_HS2 1102
|
||||
#define ID_HS3 1103
|
||||
#define ID_HS4 1104
|
||||
#define ID_OR1 1105
|
||||
#define ID_OR2 1106
|
||||
#define ID_OR3 1107
|
||||
#define ID_OR4 1108
|
||||
#define ID_OREXT 1109
|
||||
#define ID_AND1 1110
|
||||
#define ID_AND2 1111
|
||||
#define ID_AND3 1112
|
||||
#define ID_AND4 1113
|
||||
#define ID_ANDEXT 1114
|
||||
#define ID_TRANS 1115
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class DOFrame_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class DOFrame_fb : public wxFrame
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxMenuBar* m_menubar1;
|
||||
wxMenu* m_menu1;
|
||||
wxMenu* m_menu4;
|
||||
wxMenu* m_menu3;
|
||||
wxMenu* m_menu2;
|
||||
wxPanel* m_pnScreen;
|
||||
wxPanel* m_pnControls;
|
||||
wxSlider* m_slTrgLevel;
|
||||
wxButton* m_btRun;
|
||||
wxButton* m_btSingle;
|
||||
wxRadioButton* m_rbNormal;
|
||||
wxRadioButton* m_rbAuto;
|
||||
wxBitmapButton* m_bpPolarity;
|
||||
wxButton* m_btTrgCfg;
|
||||
wxStaticText* m_staticText59;
|
||||
wxStaticText* m_staticText60;
|
||||
wxStaticText* m_staticText61;
|
||||
wxSlider* m_slTrgDelay;
|
||||
wxRadioBox* m_rbSource;
|
||||
wxBitmapButton* m_bpButton2;
|
||||
wxStaticText* m_stHScale;
|
||||
wxBitmapButton* m_bpButton3;
|
||||
wxSlider* m_slHOffset;
|
||||
wxToggleButton* m_btCh1;
|
||||
wxSlider* m_slPos1;
|
||||
wxBitmapButton* m_bpButton4;
|
||||
wxStaticText* m_stScale1;
|
||||
wxBitmapButton* m_bpButton5;
|
||||
wxToggleButton* m_btCh2;
|
||||
wxSlider* m_slPos2;
|
||||
wxBitmapButton* m_bpButton6;
|
||||
wxStaticText* m_stScale2;
|
||||
wxBitmapButton* m_bpButton7;
|
||||
wxToggleButton* m_btCh3;
|
||||
wxSlider* m_slPos3;
|
||||
wxBitmapButton* m_bpButton8;
|
||||
wxStaticText* m_stScale3;
|
||||
wxBitmapButton* m_bpButton9;
|
||||
wxToggleButton* m_btCh4;
|
||||
wxSlider* m_slPos4;
|
||||
wxBitmapButton* m_bpButton10;
|
||||
wxStaticText* m_stScale4;
|
||||
wxBitmapButton* m_bpButton11;
|
||||
wxStaticText* m_staticText76;
|
||||
wxToggleButton* m_toggleCursorA;
|
||||
wxToggleButton* m_toggleCursorB;
|
||||
wxCheckBox* m_checkBox8;
|
||||
wxButton* m_btConfig;
|
||||
wxButton* m_btSave;
|
||||
wxButton* m_btMeasure;
|
||||
wxButton* m_btDisplay;
|
||||
wxButton* m_btPrint;
|
||||
wxButton* m_btAbout;
|
||||
wxButton* m_btExit;
|
||||
|
||||
// Virtual event handlers, overide them in your derived class
|
||||
virtual void OnSave( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnPrint( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnExit( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnCursor( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnSnap( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnConfig( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnMeasure( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnDisplay( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnAbout( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnTrgLevelChange( wxScrollEvent& event ) { event.Skip(); }
|
||||
virtual void OnZero( wxMouseEvent& event ) { event.Skip(); }
|
||||
virtual void OnTrigger( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnTrgButton( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnTrgDelayChange( wxScrollEvent& event ) { event.Skip(); }
|
||||
virtual void OnHScaleChange( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnHOffsetChange( wxScrollEvent& event ) { event.Skip(); }
|
||||
virtual void OnChnOn( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnPosChange( wxScrollEvent& event ) { event.Skip(); }
|
||||
virtual void OnScaleChange( wxCommandEvent& event ) { event.Skip(); }
|
||||
|
||||
|
||||
public:
|
||||
|
||||
DOFrame_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("DRS Oscilloscope"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( 1024,768 ), long style = wxDEFAULT_FRAME_STYLE|wxTAB_TRAVERSAL );
|
||||
|
||||
~DOFrame_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class ConfigDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class ConfigDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxChoice* m_cbBoard;
|
||||
wxButton* m_btScan;
|
||||
wxButton* m_btInfo;
|
||||
wxCheckBox* m_cbMulti;
|
||||
wxRadioBox* m_rbChHalf;
|
||||
wxCheckBox* m_cbClkOn;
|
||||
wxRadioBox* m_rbRange;
|
||||
wxTextCtrl* m_tbFreq;
|
||||
wxStaticText* m_staticText26;
|
||||
wxCheckBox* m_cbLocked;
|
||||
wxStaticText* m_staticText261;
|
||||
wxStaticText* m_stActFreq;
|
||||
wxCheckBox* m_cbCalOn;
|
||||
wxTextCtrl* m_teCal;
|
||||
wxSlider* m_slCal;
|
||||
wxStaticText* m_staticText10;
|
||||
wxCheckBox* m_cbCalibrated;
|
||||
wxCheckBox* m_cbCalibrated2;
|
||||
wxCheckBox* m_cbSpikes;
|
||||
wxButton* m_button13;
|
||||
wxGauge* m_gaugeCalVolt;
|
||||
wxCheckBox* m_cbRotated;
|
||||
wxCheckBox* m_cbTCalOn;
|
||||
wxCheckBox* m_cbTrgCorr;
|
||||
wxCheckBox* m_cbExtRefclk;
|
||||
wxButton* m_button14;
|
||||
wxGauge* m_gaugeCalTime;
|
||||
wxButton* m_button10;
|
||||
|
||||
// Virtual event handlers, overide them in your derived class
|
||||
virtual void OnBoardSelect( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnRescan( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnInfo( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnChannelHalf( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnClkOn( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnInputRange( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnFreq( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnLock( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnCalOn( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnCalEnter( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnCalSlider( wxScrollEvent& event ) { event.Skip(); }
|
||||
virtual void OnDisplayWaveforms( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnRemoveSpikes( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnButtonCalVolt( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnButtonCalTime( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnClose( wxCommandEvent& event ) { event.Skip(); }
|
||||
|
||||
|
||||
public:
|
||||
|
||||
ConfigDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("Configuration"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~ConfigDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class DisplayDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class DisplayDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxCheckBox* m_checkBox7;
|
||||
wxCheckBox* m_checkBox71;
|
||||
wxCheckBox* m_checkBox88;
|
||||
wxCheckBox* m_checkBox73;
|
||||
wxRadioButton* m_rbShowSample;
|
||||
wxRadioButton* m_rbShowAverage;
|
||||
wxRadioButton* m_rbShowPersist;
|
||||
wxStaticText* m_staticText59;
|
||||
wxComboBox* m_cbNumber;
|
||||
wxStaticText* m_staticText11;
|
||||
wxStaticText* m_staticText12;
|
||||
wxStaticText* m_staticText13;
|
||||
wxStaticText* m_staticText14;
|
||||
wxStaticText* m_staticText15;
|
||||
wxStaticText* m_staticText17;
|
||||
wxCheckBox* m_checkBox13;
|
||||
wxCheckBox* m_checkBox14;
|
||||
wxCheckBox* m_checkBox15;
|
||||
wxCheckBox* m_checkBox16;
|
||||
wxButton* m_button10;
|
||||
|
||||
// Virtual event handlers, overide them in your derived class
|
||||
virtual void OnDateTime( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnShowGrid( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnLines( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnScalers( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnDisplayMode( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnButton( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnClose( wxCommandEvent& event ) { event.Skip(); }
|
||||
|
||||
|
||||
public:
|
||||
|
||||
DisplayDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("Display"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~DisplayDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class MeasureDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class MeasureDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxStaticText* m_staticText11;
|
||||
wxStaticText* m_staticText12;
|
||||
wxStaticText* m_staticText13;
|
||||
wxStaticText* m_staticText14;
|
||||
wxStaticText* m_staticText15;
|
||||
wxStaticText* m_staticText80;
|
||||
wxStaticText* m_staticText81;
|
||||
wxStaticText* m_staticText82;
|
||||
wxStaticText* m_staticText83;
|
||||
wxStaticText* m_staticText84;
|
||||
wxStaticText* m_staticText16;
|
||||
wxCheckBox* m_checkBox9;
|
||||
wxCheckBox* m_checkBox10;
|
||||
wxCheckBox* m_checkBox11;
|
||||
wxCheckBox* m_checkBox12;
|
||||
wxStaticText* m_staticText17;
|
||||
wxCheckBox* m_checkBox13;
|
||||
wxCheckBox* m_checkBox14;
|
||||
wxCheckBox* m_checkBox15;
|
||||
wxCheckBox* m_checkBox16;
|
||||
wxStaticText* m_staticText19;
|
||||
wxCheckBox* m_checkBox17;
|
||||
wxCheckBox* m_checkBox18;
|
||||
wxCheckBox* m_checkBox19;
|
||||
wxCheckBox* m_checkBox20;
|
||||
wxStaticText* m_staticText90;
|
||||
wxCheckBox* m_checkBox74;
|
||||
wxCheckBox* m_checkBox75;
|
||||
wxCheckBox* m_checkBox76;
|
||||
wxCheckBox* m_checkBox77;
|
||||
wxStaticText* m_staticText91;
|
||||
wxCheckBox* m_checkBox82;
|
||||
wxCheckBox* m_checkBox83;
|
||||
wxCheckBox* m_checkBox84;
|
||||
wxCheckBox* m_checkBox85;
|
||||
wxStaticLine* m_staticline4;
|
||||
wxStaticLine* m_staticline41;
|
||||
wxStaticLine* m_staticline42;
|
||||
wxStaticLine* m_staticline43;
|
||||
wxStaticLine* m_staticline44;
|
||||
wxStaticText* m_staticText85;
|
||||
wxStaticText* m_staticText86;
|
||||
wxStaticText* m_staticText87;
|
||||
wxStaticText* m_staticText88;
|
||||
wxStaticText* m_staticText89;
|
||||
wxStaticText* m_staticText20;
|
||||
wxCheckBox* m_checkBox21;
|
||||
wxCheckBox* m_checkBox22;
|
||||
wxCheckBox* m_checkBox23;
|
||||
wxCheckBox* m_checkBox24;
|
||||
wxStaticText* m_staticText21;
|
||||
wxCheckBox* m_checkBox25;
|
||||
wxCheckBox* m_checkBox26;
|
||||
wxCheckBox* m_checkBox27;
|
||||
wxCheckBox* m_checkBox28;
|
||||
wxStaticText* m_staticText22;
|
||||
wxCheckBox* m_checkBox29;
|
||||
wxCheckBox* m_checkBox30;
|
||||
wxCheckBox* m_checkBox31;
|
||||
wxCheckBox* m_checkBox32;
|
||||
wxStaticText* m_staticText23;
|
||||
wxCheckBox* m_checkBox33;
|
||||
wxCheckBox* m_checkBox34;
|
||||
wxCheckBox* m_checkBox35;
|
||||
wxCheckBox* m_checkBox36;
|
||||
wxStaticText* m_staticText221;
|
||||
wxCheckBox* m_checkBox291;
|
||||
wxCheckBox* m_checkBox2911;
|
||||
wxCheckBox* m_checkBox2912;
|
||||
wxCheckBox* m_checkBox2913;
|
||||
wxStaticText* m_staticText2211;
|
||||
wxCheckBox* m_checkBox2914;
|
||||
wxCheckBox* m_checkBox2915;
|
||||
wxCheckBox* m_checkBox2916;
|
||||
wxCheckBox* m_checkBox2917;
|
||||
wxStaticText* m_staticText231;
|
||||
wxCheckBox* m_checkBox37;
|
||||
wxCheckBox* m_checkBox38;
|
||||
wxCheckBox* m_checkBox39;
|
||||
wxCheckBox* m_checkBox40;
|
||||
wxStaticText* m_staticText901;
|
||||
wxCheckBox* m_checkBox78;
|
||||
wxCheckBox* m_checkBox79;
|
||||
wxCheckBox* m_checkBox80;
|
||||
wxCheckBox* m_checkBox81;
|
||||
wxStaticLine* m_staticline1;
|
||||
wxCheckBox* m_cbStat;
|
||||
wxCheckBox* m_cbHist;
|
||||
wxStaticText* m_staticText27;
|
||||
wxComboBox* m_cbNAverage;
|
||||
wxStaticText* m_staticText271;
|
||||
wxButton* m_button15;
|
||||
wxStaticLine* m_staticline2;
|
||||
wxCheckBox* m_cbIndicator;
|
||||
wxStaticLine* m_staticline21;
|
||||
wxButton* m_button11;
|
||||
|
||||
// Virtual event handlers, overide them in your derived class
|
||||
virtual void OnButton( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnStat( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnHist( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnStatNAverage( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnStatReset( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnIndicator( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnClose( wxCommandEvent& event ) { event.Skip(); }
|
||||
|
||||
|
||||
public:
|
||||
|
||||
MeasureDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("Select Measurements"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~MeasureDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class TriggerDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class TriggerDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxStaticText* m_staticText12;
|
||||
wxStaticText* m_staticText13;
|
||||
wxStaticText* m_staticText14;
|
||||
wxStaticText* m_staticText15;
|
||||
wxStaticText* m_staticText16;
|
||||
wxStaticLine* m_staticline11;
|
||||
wxStaticText* m_staticText771;
|
||||
wxCheckBox* m_cbOR1;
|
||||
wxStaticText* m_staticText17;
|
||||
wxCheckBox* m_cbOR2;
|
||||
wxStaticText* m_staticText171;
|
||||
wxCheckBox* m_cbOR3;
|
||||
wxStaticText* m_staticText172;
|
||||
wxCheckBox* m_cbOR4;
|
||||
wxStaticText* m_staticText173;
|
||||
wxCheckBox* m_cbOREXT;
|
||||
wxStaticText* m_staticText84;
|
||||
wxCheckBox* m_cbAND1;
|
||||
wxStaticText* m_staticText18;
|
||||
wxCheckBox* m_cbAND2;
|
||||
wxStaticText* m_staticText181;
|
||||
wxCheckBox* m_cbAND3;
|
||||
wxStaticText* m_staticText182;
|
||||
wxCheckBox* m_cbAND4;
|
||||
wxStaticText* m_staticText183;
|
||||
wxCheckBox* m_cbANDEXT;
|
||||
wxCheckBox* m_cbTrans;
|
||||
wxStaticLine* m_staticline10;
|
||||
wxStaticText* m_staticText77;
|
||||
wxTextCtrl* m_tbLevel1;
|
||||
wxTextCtrl* m_tbLevel2;
|
||||
wxTextCtrl* m_tbLevel3;
|
||||
wxTextCtrl* m_tbLevel4;
|
||||
wxStaticText* m_staticText78;
|
||||
wxStaticLine* m_staticline25;
|
||||
wxButton* m_button11;
|
||||
|
||||
// Virtual event handlers, overide them in your derived class
|
||||
virtual void OnButton( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnTriggerLevel( wxCommandEvent& event ) { event.Skip(); }
|
||||
virtual void OnClose( wxCommandEvent& event ) { event.Skip(); }
|
||||
|
||||
|
||||
public:
|
||||
|
||||
TriggerDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("Configure Trigger"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxDefaultSize, long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~TriggerDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class AboutDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class AboutDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxStaticText* m_staticText18;
|
||||
wxStaticText* m_stVersion;
|
||||
wxStaticText* m_stBuild;
|
||||
wxStaticText* m_staticText20;
|
||||
wxStaticText* m_staticText21;
|
||||
wxStaticBitmap* m_bitmap1;
|
||||
wxStaticText* m_staticText23;
|
||||
wxHyperlinkCtrl* m_hyperlink1;
|
||||
wxButton* m_button12;
|
||||
|
||||
public:
|
||||
|
||||
AboutDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("About"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~AboutDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// Class InfoDialog_fb
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
class InfoDialog_fb : public wxDialog
|
||||
{
|
||||
private:
|
||||
|
||||
protected:
|
||||
wxStaticText* m_staticText45;
|
||||
wxStaticText* m_stBoardType;
|
||||
wxStaticText* m_staticText47;
|
||||
wxStaticText* m_stDRSType;
|
||||
wxStaticText* m_staticText49;
|
||||
wxStaticText* m_stSerialNumber;
|
||||
wxStaticText* m_staticText51;
|
||||
wxStaticText* m_stFirmwareRevision;
|
||||
wxStaticText* m_staticText53;
|
||||
wxStaticText* m_stTemperature;
|
||||
wxStaticText* m_staticText55;
|
||||
wxStaticText* m_stInputRange;
|
||||
wxStaticText* m_staticText57;
|
||||
wxStaticText* m_stCalibratedRange;
|
||||
wxStaticText* m_staticText59;
|
||||
wxStaticText* m_stCalibratedFrequency;
|
||||
wxStaticText* m_staticText61;
|
||||
wxStaticText* m_stFrequency;
|
||||
wxButton* m_button12;
|
||||
|
||||
public:
|
||||
|
||||
InfoDialog_fb( wxWindow* parent, wxWindowID id = wxID_ANY, const wxString& title = wxT("Info"), const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxDEFAULT_DIALOG_STYLE );
|
||||
~InfoDialog_fb();
|
||||
|
||||
};
|
||||
|
||||
#endif //__DRSOSC_H__
|
||||
Binary file not shown.
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* DRSOscInc.h
|
||||
* Collection of all DRS oscilloscope header include files
|
||||
* $Id: DRSOscInc.h 20924 2013-03-21 13:31:33Z ritt $
|
||||
*/
|
||||
|
||||
#define MAX_N_BOARDS 16
|
||||
|
||||
#include "wx/wx.h"
|
||||
#include "wx/dcbuffer.h"
|
||||
#include "wx/print.h"
|
||||
#include "wx/numdlg.h"
|
||||
#include "mxml.h"
|
||||
#include "DRS.h"
|
||||
#include "DRSOsc.h"
|
||||
#include "Osci.h"
|
||||
#include "Measurement.h"
|
||||
#include "ConfigDialog.h"
|
||||
#include "DisplayDialog.h"
|
||||
#include "AboutDialog.h"
|
||||
#include "InfoDialog.h"
|
||||
#include "MeasureDialog.h"
|
||||
#include "TriggerDialog.h"
|
||||
#include "DOScreen.h"
|
||||
#include "DOFrame.h"
|
||||
#include "EPThread.h"
|
||||
|
||||
double ss_nan();
|
||||
int ss_isnan(double x);
|
||||
void ss_sleep(int ms);
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* DisplayDialog.cpp
|
||||
* Modeless Displayuration Dialog class
|
||||
* $Id: DisplayDialog.cpp 21252 2014-02-06 09:37:27Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
DisplayDialog::DisplayDialog( wxWindow* parent )
|
||||
:
|
||||
DisplayDialog_fb( parent )
|
||||
{
|
||||
m_frame = (DOFrame *)parent;
|
||||
m_osci = m_frame->GetOsci();
|
||||
}
|
||||
|
||||
void DisplayDialog::OnDateTime( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayDateTime(event.IsChecked());
|
||||
}
|
||||
|
||||
void DisplayDialog::OnShowGrid( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayShowGrid(event.IsChecked());
|
||||
}
|
||||
|
||||
void DisplayDialog::OnLines( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayLines(event.IsChecked());
|
||||
}
|
||||
|
||||
void DisplayDialog::OnDisplayMode( wxCommandEvent& event )
|
||||
{
|
||||
long n;
|
||||
m_cbNumber->GetValue().ToLong(&n);
|
||||
|
||||
if (event.GetId() == ID_DISPSAMPLE)
|
||||
m_frame->SetDisplayMode(ID_DISPSAMPLE, 0);
|
||||
else if (event.GetId() == ID_DISPAVERAGE)
|
||||
m_frame->SetDisplayMode(ID_DISPAVERAGE, n);
|
||||
else if (event.GetId() == ID_DISPPERSIST)
|
||||
m_frame->SetDisplayMode(ID_DISPPERSIST, n);
|
||||
else if (event.GetId() == ID_DISPNUMBER)
|
||||
m_frame->SetDisplayMode(m_rbShowAverage->GetValue()?ID_DISPAVERAGE:ID_DISPPERSIST, n);
|
||||
}
|
||||
|
||||
void DisplayDialog::OnScalers( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetDisplayScalers(event.IsChecked());
|
||||
}
|
||||
|
||||
void DisplayDialog::OnButton( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetMathDisplay(event.GetId(), event.IsChecked());
|
||||
}
|
||||
|
||||
void DisplayDialog::OnClose( wxCommandEvent& event )
|
||||
{
|
||||
this->Hide();
|
||||
}
|
||||
@@ -0,0 +1,41 @@
|
||||
#ifndef __DisplayDialog__
|
||||
#define __DisplayDialog__
|
||||
|
||||
// $Id: DisplayDialog.h 21252 2014-02-06 09:37:27Z ritt $
|
||||
|
||||
/**
|
||||
@file
|
||||
Subclass of DisplayDialog_fb, which is generated by wxFormBuilder.
|
||||
*/
|
||||
|
||||
class DOFrame;
|
||||
class Osci;
|
||||
|
||||
/** Implementing DisplayDialog_fb */
|
||||
class DisplayDialog : public DisplayDialog_fb
|
||||
{
|
||||
protected:
|
||||
// Handlers for DisplayDialog_fb events.
|
||||
void OnDateTime(wxCommandEvent& event);
|
||||
void OnShowGrid(wxCommandEvent& event);
|
||||
void OnLines(wxCommandEvent& event);
|
||||
void OnDisplayMode(wxCommandEvent& event);
|
||||
void OnButton(wxCommandEvent& event);
|
||||
void OnScalers(wxCommandEvent& event);
|
||||
|
||||
void OnClose(wxCommandEvent& event);
|
||||
|
||||
public:
|
||||
/** Constructor */
|
||||
DisplayDialog( wxWindow* parent );
|
||||
|
||||
private:
|
||||
DOFrame *m_frame;
|
||||
Osci *m_osci;
|
||||
|
||||
void PopulateBoards(void);
|
||||
void EnableButtons(void);
|
||||
|
||||
};
|
||||
|
||||
#endif // __DisplayDialog__
|
||||
@@ -0,0 +1,124 @@
|
||||
/*
|
||||
* EPThread.cpp
|
||||
* DRS oscilloscope event processing thread
|
||||
* $Id: EPThread.cpp 21511 2014-10-17 08:02:30Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
#include "rb.h"
|
||||
|
||||
extern wxCriticalSection *g_epcs;
|
||||
|
||||
bool g_finished = false;
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
EPThread::EPThread(DOFrame *f) : wxThread()
|
||||
{
|
||||
m_frame = f;
|
||||
m_osci = f->GetOsci();
|
||||
m_finished = false;
|
||||
m_stopThread = false;
|
||||
m_active = false;
|
||||
m_enabled = true;
|
||||
Create();
|
||||
Run();
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
EPThread::~EPThread()
|
||||
{
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
void EPThread::ClearWaveforms()
|
||||
{
|
||||
while (m_osci->HasNewEvent());
|
||||
memset(m_time, 0, sizeof(m_time));
|
||||
memset(m_waveform, 0, sizeof(m_waveform));
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
void EPThread::StopThread()
|
||||
{
|
||||
m_stopThread = true;
|
||||
do {
|
||||
wxThread::Sleep(10);
|
||||
} while (!g_finished); // cannot access m_finished here under Widnows
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
void EPThread::Enable(bool flag)
|
||||
{
|
||||
m_enabled = flag;
|
||||
if (!flag)
|
||||
while (m_active)
|
||||
wxThread::Sleep(10);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
void *EPThread::Entry()
|
||||
{
|
||||
int status;
|
||||
|
||||
do {
|
||||
if (m_enabled) {
|
||||
m_active = true;
|
||||
if (m_osci->HasNewEvent()) {
|
||||
m_osci->ReadWaveforms();
|
||||
if (m_frame->GetRearm()) {
|
||||
m_osci->Start();
|
||||
m_frame->SetRearm(false);
|
||||
}
|
||||
|
||||
if (m_frame->GetTrgCorr())
|
||||
m_osci->CorrectTriggerPoint(m_frame->GetTrgPosition(0));
|
||||
|
||||
g_epcs->Enter();
|
||||
status = 0;
|
||||
if (m_frame->GetWFFile() || m_frame->GetWFfd()) {
|
||||
status = m_osci->SaveWaveforms(m_frame->GetWFFile(), m_frame->GetWFfd());
|
||||
m_frame->IncrementSaved();
|
||||
}
|
||||
g_epcs->Leave();
|
||||
|
||||
if (status < 0)
|
||||
m_frame->CloseWFFile(true);
|
||||
|
||||
if (m_frame->GetWFFile() || m_frame->GetWFfd())
|
||||
if (m_frame->GetNSaved() >= m_frame->GetNSaveMax())
|
||||
m_frame->CloseWFFile(false);
|
||||
|
||||
m_frame->EvaluateMeasurements();
|
||||
m_frame->IncrementAcquisitions();
|
||||
|
||||
// copy event from oscilloscope
|
||||
int n = m_osci->IsMultiBoard() ? m_osci->GetNumberOfBoards() : 1;
|
||||
|
||||
g_epcs->Enter();
|
||||
for (int i=0 ; i<n ; i++) {
|
||||
for (int j=0 ; j<4 ; j++) {
|
||||
memcpy(m_time[i][j], m_osci->GetTime(i, j), m_osci->GetWaveformDepth(j)*sizeof(float));
|
||||
memcpy(m_waveform[i][j], m_osci->GetWaveform(i, j), m_osci->GetWaveformDepth(j)*sizeof(float));
|
||||
}
|
||||
}
|
||||
g_epcs->Leave();
|
||||
} else
|
||||
wxThread::Sleep(10);
|
||||
} else {
|
||||
wxThread::Sleep(10);
|
||||
m_active = false;
|
||||
}
|
||||
|
||||
} while (!m_stopThread);
|
||||
|
||||
m_finished = true;
|
||||
g_finished = true;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* EPThread.h
|
||||
* DRS oscilloscope event processor header file
|
||||
* $Id: EPThread.h 21263 2014-02-07 16:38:07Z ritt $
|
||||
*/
|
||||
|
||||
class EPThread : public wxThread
|
||||
{
|
||||
public:
|
||||
EPThread(DOFrame *o);
|
||||
~EPThread();
|
||||
void *Entry();
|
||||
float *GetTime(int b, int c) { return m_time[b][c]; }
|
||||
float *GetWaveform(int b, int c) { return m_waveform[b][c]; }
|
||||
void ClearWaveforms();
|
||||
void Enable(bool flag);
|
||||
void StopThread();
|
||||
bool IsFinished() { return m_finished; }
|
||||
|
||||
private:
|
||||
DOFrame *m_frame;
|
||||
Osci *m_osci;
|
||||
bool m_stopThread;
|
||||
bool m_enabled;
|
||||
bool m_active;
|
||||
bool m_finished;
|
||||
float m_waveform[MAX_N_BOARDS][4][2048];
|
||||
float m_time[MAX_N_BOARDS][4][2048];
|
||||
};
|
||||
Binary file not shown.
@@ -0,0 +1,68 @@
|
||||
{
|
||||
"images" : [
|
||||
{
|
||||
"size" : "16x16",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc16x16.png",
|
||||
"scale" : "1x"
|
||||
},
|
||||
{
|
||||
"size" : "16x16",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc16x16x2.png",
|
||||
"scale" : "2x"
|
||||
},
|
||||
{
|
||||
"size" : "32x32",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc32x32.png",
|
||||
"scale" : "1x"
|
||||
},
|
||||
{
|
||||
"size" : "32x32",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc32x32x2.png",
|
||||
"scale" : "2x"
|
||||
},
|
||||
{
|
||||
"size" : "128x128",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc128x128.png",
|
||||
"scale" : "1x"
|
||||
},
|
||||
{
|
||||
"size" : "128x128",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc128x128x2.png",
|
||||
"scale" : "2x"
|
||||
},
|
||||
{
|
||||
"size" : "256x256",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc256x256.png",
|
||||
"scale" : "1x"
|
||||
},
|
||||
{
|
||||
"size" : "256x256",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc256x256x2.png",
|
||||
"scale" : "2x"
|
||||
},
|
||||
{
|
||||
"size" : "512x512",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc512x512.png",
|
||||
"scale" : "1x"
|
||||
},
|
||||
{
|
||||
"size" : "512x512",
|
||||
"idiom" : "mac",
|
||||
"filename" : "DRSOsc512x512x2.png",
|
||||
"scale" : "2x"
|
||||
}
|
||||
],
|
||||
"info" : {
|
||||
"version" : 1,
|
||||
"author" : "xcode"
|
||||
}
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 15 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 40 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 3.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 5.5 KiB |
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|
After Width: | Height: | Size: 36 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 96 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 4.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 8.9 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 94 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 236 KiB |
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* InfoDialog.cpp
|
||||
* Info Dialog class
|
||||
* $Id: InfoDialog.cpp 17646 2011-05-11 15:21:02Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
extern char svn_revision[];
|
||||
extern char drsosc_version[];
|
||||
|
||||
InfoDialog::InfoDialog(wxWindow* parent)
|
||||
:
|
||||
InfoDialog_fb( parent )
|
||||
{
|
||||
wxString str;
|
||||
|
||||
DOFrame *frame = (DOFrame*)parent;
|
||||
DRSBoard *b = frame->GetOsci()->GetCurrentBoard();
|
||||
|
||||
int t = b->GetBoardType();
|
||||
if (t == 5)
|
||||
str.Printf(wxT("5 (Eval. 2.0)"));
|
||||
else if (t == 6)
|
||||
str.Printf(wxT("6 (Mezz. 1.4)"));
|
||||
else if (t == 7)
|
||||
str.Printf(wxT("7 (Eval. 3.0)"));
|
||||
else if (t == 8)
|
||||
str.Printf(wxT("8 (Eval. 4.0)"));
|
||||
else
|
||||
str.Printf(wxT("%d"), t);
|
||||
m_stBoardType->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("DRS%d"), b->GetDRSType());
|
||||
m_stDRSType->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%d"), b->GetBoardSerialNumber());
|
||||
m_stSerialNumber->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%d"), b->GetFirmwareVersion());
|
||||
m_stFirmwareRevision->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%1.1lf"), b->GetTemperature());
|
||||
m_stTemperature->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%1.2lgV...%1.2lgV"), b->GetInputRange()-0.5, b->GetInputRange()+0.5);
|
||||
m_stInputRange->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%1.2lgV...%1.2lgV"), b->GetCalibratedInputRange()-0.5, b->GetCalibratedInputRange()+0.5);
|
||||
m_stCalibratedRange->SetLabel(str);
|
||||
|
||||
str.Printf(wxT("%1.3lf GSPS"), b->GetCalibratedFrequency());
|
||||
m_stCalibratedFrequency->SetLabel(str);
|
||||
|
||||
double freq;
|
||||
b->ReadFrequency(0, &freq);
|
||||
str.Printf(wxT("%1.3lf GSPS"), freq);
|
||||
m_stFrequency->SetLabel(str);
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
#ifndef __InfoDialog__
|
||||
#define __InfoDialog__
|
||||
|
||||
// $Id: InfoDialog.h 15243 2010-05-07 14:01:43Z ritt $
|
||||
|
||||
/**
|
||||
@file
|
||||
Subclass of InfoDialog_fb, which is generated by wxFormBuilder.
|
||||
*/
|
||||
|
||||
/** Implementing ConfigDialog_fb */
|
||||
class InfoDialog : public InfoDialog_fb
|
||||
{
|
||||
public:
|
||||
/** Constructor */
|
||||
InfoDialog( wxWindow* parent );
|
||||
};
|
||||
|
||||
#endif // __InfoDialog__
|
||||
@@ -0,0 +1,87 @@
|
||||
########################################################
|
||||
#
|
||||
# Makefile for drsosc executable under linux
|
||||
#
|
||||
# Requires wxWidgets 2.8.9 or newer
|
||||
#
|
||||
# S. Ritt, Nov. 2016
|
||||
########################################################
|
||||
|
||||
# determine OS
|
||||
OSTYPE = $(shell uname)
|
||||
|
||||
# check if wxWidgets is installed
|
||||
HAVE_WX = $(shell which wx-config)
|
||||
ifeq ($(HAVE_WX),)
|
||||
$(error Error: wxWidgets required to compile "drsosc")
|
||||
endif
|
||||
|
||||
CFLAGS = -g -O2 -Wall -Wuninitialized -Wno-unused-result -fno-strict-aliasing -DHAVE_USB -DHAVE_LIBUSB10 -DUSE_DRS_MUTEX
|
||||
CFLAGS += -I../include -I../ -I/usr/local/include
|
||||
WXFLAGS = $(shell wx-config --cxxflags)
|
||||
LIBS = -L/usr/local/lib -lpthread -lutil
|
||||
LIBS += $(shell wx-config --libs)
|
||||
|
||||
WX_OBJ = ConfigDialog.o DOFrame.o DOScreen.o DRSOsc.o MeasureDialog.o Measurement.o Osci.o EPThread.o DisplayDialog.o InfoDialog.o AboutDialog.o TriggerDialog.o
|
||||
OBJECTS = main.o musbstd.o DRS.o rb.o averager.o mxml.o strlcpy.o $(WX_OBJ)
|
||||
|
||||
OUTNAME = drsosc
|
||||
|
||||
# OS specific flags
|
||||
ifeq ($(OSTYPE),Darwin)
|
||||
CFLAGS += -DOS_DARWIN -stdlib=libstdc++
|
||||
LIBS += -lusb-1.0
|
||||
endif
|
||||
|
||||
ifeq ($(OSTYPE),Linux)
|
||||
CFLAGS += -DOS_LINUX
|
||||
LIBS += -lusb-1.0
|
||||
endif
|
||||
|
||||
all: $(OUTNAME) read_binary
|
||||
app: DRSOsc.app
|
||||
|
||||
$(OUTNAME): $(OBJECTS)
|
||||
$(CXX) $(CFLAGS) $(OBJECTS) -o $(OUTNAME) $(LIBS)
|
||||
|
||||
DRSOsc.app: drsosc
|
||||
-mkdir DRSOsc.app
|
||||
-mkdir DRSOsc.app/Contents
|
||||
-mkdir DRSOsc.app/Contents/MacOS
|
||||
-mkdir DRSOsc.app/Contents/Resources
|
||||
-mkdir DRSOsc.app/Contents/Resources/English.lproj
|
||||
echo 'APPL????' > DRSOsc.app/Contents/PkgInfo
|
||||
cp drsosc.xcodeproj/Info-processed.plist DRSOsc.app/Contents/Info.plist
|
||||
cp drsosc DRSOsc.app/Contents/MacOS/DRSOsc
|
||||
cp DRSOsc.icns DRSOsc.app/Contents/Resources
|
||||
|
||||
read_binary: read_binary.cpp
|
||||
$(CXX) $(CFLAGS) -o $@ $<
|
||||
|
||||
main.o: %.o: %.cpp ../include/mxml.h ../include/DRS.h
|
||||
$(CXX) $(CFLAGS) $(WXFLAGS) -c $<
|
||||
|
||||
musbstd.o: ../src/musbstd.c ../include/musbstd.h
|
||||
$(CC) $(CFLAGS) -c $<
|
||||
|
||||
DRS.o: ../src/DRS.cpp ../include/DRS.h
|
||||
$(CXX) $(CFLAGS) $(WXFLAGS) -c $<
|
||||
|
||||
rb.o: rb.cpp rb.h
|
||||
$(CXX) $(CFLAGS) -c $<
|
||||
|
||||
averager.o: ../src/averager.cpp ../include/averager.h
|
||||
$(CXX) $(CFLAGS) -c $<
|
||||
|
||||
mxml.o: ../src/mxml.c ../include/mxml.h
|
||||
$(CC) $(CFLAGS) -c $<
|
||||
|
||||
strlcpy.o: ../src/strlcpy.c ../include/strlcpy.h
|
||||
$(CC) $(CFLAGS) -c $<
|
||||
|
||||
$(WX_OBJ): %.o: %.cpp %.h ../include/mxml.h ../include/DRS.h
|
||||
$(CXX) $(CFLAGS) $(WXFLAGS) -c $<
|
||||
|
||||
clean:
|
||||
rm -f *.o $(OUTNAME) read_binary
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* ConfigDialog.cpp
|
||||
* Modal Measurement Configuration Dialog class
|
||||
* $Id: MeasureDialog.cpp 21271 2014-02-17 15:20:55Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
MeasureDialog::MeasureDialog( wxWindow* parent )
|
||||
:
|
||||
MeasureDialog_fb( parent )
|
||||
{
|
||||
m_frame = (DOFrame *)parent;
|
||||
}
|
||||
|
||||
void MeasureDialog::OnClose( wxCommandEvent& event )
|
||||
{
|
||||
this->Hide();
|
||||
}
|
||||
|
||||
void MeasureDialog::OnButton( wxCommandEvent& event )
|
||||
{
|
||||
if (event.IsChecked() && event.GetId() >= ID_VS1 && event.GetId() <= ID_VS4)
|
||||
wxMessageBox(wxT("Please use cursor A to set the location of the vertical slice"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_INFORMATION, this);
|
||||
|
||||
if (event.IsChecked() && event.GetId() >= ID_CHRG1 && event.GetId() <= ID_CHRG4)
|
||||
wxMessageBox(wxT("Please use cursors A and B to define the integration region"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_INFORMATION, this);
|
||||
|
||||
if (event.IsChecked() && event.GetId() >= ID_HS1 && event.GetId() <= ID_HS4)
|
||||
wxMessageBox(wxT("Please use cursor A to set the location of the horizontal slice"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_INFORMATION, this);
|
||||
|
||||
m_frame->SetMeasurement(event.GetId(), event.IsChecked());
|
||||
}
|
||||
|
||||
void MeasureDialog::OnStat( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetStat(event.IsChecked());
|
||||
}
|
||||
|
||||
void MeasureDialog::OnHist( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetHist(event.IsChecked());
|
||||
}
|
||||
|
||||
void MeasureDialog::OnStatNAverage( wxCommandEvent& event )
|
||||
{
|
||||
wxString str = m_cbNAverage->GetValue();
|
||||
char buf[100];
|
||||
strcpy( buf, (const char*)str.mb_str(wxConvUTF8) );
|
||||
m_frame->SetStatNStat(atoi(buf));
|
||||
}
|
||||
|
||||
void MeasureDialog::OnIndicator( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->SetIndicator(event.IsChecked());
|
||||
}
|
||||
|
||||
void MeasureDialog::OnStatReset( wxCommandEvent& event )
|
||||
{
|
||||
m_frame->StatReset();
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
#ifndef __MeasureDialog__
|
||||
#define __MeasureDialog__
|
||||
|
||||
/*
|
||||
$Id: MeasureDialog.h 18557 2011-10-28 13:21:44Z ritt $
|
||||
*/
|
||||
|
||||
class DOFrame;
|
||||
|
||||
#include "DRSOsc.h"
|
||||
|
||||
/** Implementing MeasureDialog_fb */
|
||||
class MeasureDialog : public MeasureDialog_fb
|
||||
{
|
||||
protected:
|
||||
// Handlers for MeasureDialog_fb events.
|
||||
void OnClose( wxCommandEvent& event );
|
||||
void OnButton( wxCommandEvent& event );
|
||||
void OnStat( wxCommandEvent& event );
|
||||
void OnHist( wxCommandEvent& event );
|
||||
void OnStatNAverage( wxCommandEvent& event );
|
||||
void OnIndicator( wxCommandEvent& event );
|
||||
void OnStatReset( wxCommandEvent& event );
|
||||
|
||||
public:
|
||||
/** Constructor */
|
||||
MeasureDialog( wxWindow* parent );
|
||||
|
||||
private:
|
||||
DOFrame *m_frame;
|
||||
};
|
||||
|
||||
#endif // __MeasureDialog__
|
||||
@@ -0,0 +1,801 @@
|
||||
/*
|
||||
* Measurement.cpp
|
||||
* Measuremnet class implementation
|
||||
* $Id: Measurement.cpp 21615 2015-02-25 09:31:08Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
void linfit(double *x, double *y, int n, double &a, double &b);
|
||||
|
||||
Measurement::Measurement(DOFrame *frame, int index)
|
||||
{
|
||||
m_frame = frame;
|
||||
m_index = index;
|
||||
memset(m_param, 0, sizeof(m_param));
|
||||
m_statIndex = 0;
|
||||
m_nMeasured = 0;
|
||||
m_nStat = 1000;
|
||||
m_statArray = new double[m_nStat];
|
||||
m_vsum = m_vvsum = 0;
|
||||
m_min = m_max = 0;
|
||||
ResetStat();
|
||||
}
|
||||
|
||||
Measurement::~Measurement()
|
||||
{
|
||||
delete m_statArray;
|
||||
}
|
||||
|
||||
void Measurement::ResetStat()
|
||||
{
|
||||
m_nMeasured = 0;
|
||||
m_statIndex = 0;
|
||||
}
|
||||
|
||||
void Measurement::SetNStat(int n)
|
||||
{
|
||||
if (n > 1000000)
|
||||
n = 1000000;
|
||||
if (n < 1)
|
||||
n = 1;
|
||||
m_nStat = n;
|
||||
delete m_statArray;
|
||||
m_statArray = new double[n];
|
||||
ResetStat();
|
||||
}
|
||||
|
||||
wxString Measurement::GetName()
|
||||
{
|
||||
switch (m_index) {
|
||||
case 0: return wxT("Level"); break;
|
||||
case 1: return wxT("Pk-Pk"); break;
|
||||
case 2: return wxT("RMS"); break;
|
||||
case 3: return wxT("VSlice"); break;
|
||||
case 4: return wxT("Charge"); break;
|
||||
case 5: return wxT("Freq"); break;
|
||||
case 6: return wxT("Period"); break;
|
||||
case 7: return wxT("Rise"); break;
|
||||
case 8: return wxT("Fall"); break;
|
||||
case 9: return wxT("Pos Width"); break;
|
||||
case 10: return wxT("Neg Width"); break;
|
||||
case 11: return wxT("Chn delay"); break;
|
||||
case 12: return wxT("HSlice"); break;
|
||||
default: return wxT("<undefined>"); break;
|
||||
}
|
||||
}
|
||||
|
||||
void Measurement::Measure(double *x1, double *y1, double *x2, double *y2, int n)
|
||||
{
|
||||
Measure(x1, y1, x2, y2, n, true, NULL);
|
||||
}
|
||||
|
||||
double Measurement::Measure(double *x1, double *y1, double *x2, double *y2, int n, bool update, DOScreen *s)
|
||||
{
|
||||
double v;
|
||||
int i, na;
|
||||
|
||||
switch (m_index) {
|
||||
case 0: v = MLevel(x1, y1, n, s); break;
|
||||
case 1: v = MPkPk(x1, y1, n, s); break;
|
||||
case 2: v = MRMS(x1, y1, n, s); break;
|
||||
case 3: v = MVSlice(x1, y1, n, s); break;
|
||||
case 4: v = MCharge(x1, y1, n, s); break;
|
||||
case 5: v = MFreq(x1, y1, n, s); break;
|
||||
case 6: v = MPeriod(x1, y1, n, s); break;
|
||||
case 7: v = MRise(x1, y1, n, s); break;
|
||||
case 8: v = MFall(x1, y1, n, s); break;
|
||||
case 9: v = MPosWidth(x1, y1, n, s); break;
|
||||
case 10: v = MNegWidth(x1, y1, n, s); break;
|
||||
case 11: v = MChnDelay(x1, y1, x2, y2, n, s); break;
|
||||
case 12: v = MHSlice(x1, y1, n, s); break;
|
||||
default: v = 0; break;
|
||||
}
|
||||
|
||||
m_value = v;
|
||||
|
||||
/* update statistics */
|
||||
if (update && !ss_isnan(v)) {
|
||||
m_statArray[m_statIndex] = v;
|
||||
m_statIndex = (m_statIndex + 1) % m_nStat;
|
||||
|
||||
if (m_nMeasured < m_nStat) {
|
||||
m_nMeasured++;
|
||||
na = m_nMeasured;
|
||||
} else {
|
||||
na = m_nStat;
|
||||
}
|
||||
|
||||
m_vsum = m_vvsum = 0;
|
||||
m_min = m_max = v;
|
||||
|
||||
for (i=0 ; i<na ; i++) {
|
||||
m_vsum += m_statArray[i];
|
||||
m_vvsum += (m_statArray[i] * m_statArray[i]);
|
||||
if (m_statArray[i] < m_min)
|
||||
m_min = m_statArray[i];
|
||||
if (m_statArray[i] > m_max)
|
||||
m_max = m_statArray[i];
|
||||
}
|
||||
}
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
wxString Measurement::GetString()
|
||||
{
|
||||
wxString str;
|
||||
|
||||
if (ss_isnan(m_value))
|
||||
str.Printf(wxT(" N/A"));
|
||||
else {
|
||||
switch (m_index) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 3: str.Printf(wxT("%6.1lf mV"), m_value); break;
|
||||
case 4: str.Printf(wxT("%6.1lf pC"), m_value); break;
|
||||
case 5: str.Printf(wxT("%6.1lf MHz"), m_value); break;
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
case 12: str.Printf(wxT("%6.3lf ns"), m_value); break;
|
||||
}
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
wxString Measurement::GetStat()
|
||||
{
|
||||
double mean, std;
|
||||
|
||||
if (m_nMeasured == 0) {
|
||||
mean = 0;
|
||||
std = 0;
|
||||
} else {
|
||||
mean = m_vsum / m_nMeasured;
|
||||
std = sqrt(m_vvsum/m_nMeasured - m_vsum*m_vsum/m_nMeasured/m_nMeasured);
|
||||
}
|
||||
|
||||
wxString str;
|
||||
if (ss_isnan(m_min) || ss_isnan(m_max))
|
||||
str.Printf(wxT(" N/A N/A N/A N/A %6d"), m_nMeasured);
|
||||
else
|
||||
str.Printf(wxT("%8.3lf %8.3lf %8.3lf %8.4lf %6d"), m_min, m_max, mean, std, m_nMeasured);
|
||||
return str;
|
||||
}
|
||||
|
||||
double Measurement::MLevel(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
double l = 0;
|
||||
for (int i=0 ; i<n ; i++)
|
||||
l += y[i];
|
||||
|
||||
if (n > 0)
|
||||
l /= n;
|
||||
|
||||
if (s) {
|
||||
s->GetDC()->DrawLine(s->timeToX(x[0]), s->voltToY(l),
|
||||
s->timeToX(x[n-1]), s->voltToY(l));
|
||||
}
|
||||
return l;
|
||||
}
|
||||
|
||||
double Measurement::MPkPk(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
double min_x, min_y, max_x, max_y;
|
||||
|
||||
min_x = max_x = x[0];
|
||||
min_y = max_y = y[0];
|
||||
for (int i=0 ; i<n ; i++) {
|
||||
if (y[i] < min_y) {
|
||||
min_x = x[i];
|
||||
min_y = y[i];
|
||||
}
|
||||
if (y[i] > max_y) {
|
||||
max_x = x[i];
|
||||
max_y = y[i];
|
||||
}
|
||||
}
|
||||
|
||||
if (s) {
|
||||
int x_min = s->timeToX(min_x);
|
||||
int x_max = s->timeToX(max_x);
|
||||
int y_min = s->voltToY(min_y);
|
||||
int y_max = s->voltToY(max_y);
|
||||
|
||||
int x_center = (x_min + x_max) / 2;
|
||||
|
||||
if (x_max > x_min) {
|
||||
s->GetDC()->DrawLine(x_min-20, y_min, x_center+20, y_min);
|
||||
s->GetDC()->DrawLine(x_center-20, y_max, x_max+20, y_max);
|
||||
} else {
|
||||
s->GetDC()->DrawLine(x_max-20, y_max, x_center+20, y_max);
|
||||
s->GetDC()->DrawLine(x_center-20, y_min, x_min+20, y_min);
|
||||
}
|
||||
|
||||
s->GetDC()->DrawLine(x_center, y_max, x_center, y_min);
|
||||
s->GetDC()->DrawLine(x_center, y_max, x_center+2, y_max+6);
|
||||
s->GetDC()->DrawLine(x_center, y_max, x_center-2, y_max+6);
|
||||
s->GetDC()->DrawLine(x_center, y_min, x_center+2, y_min-6);
|
||||
s->GetDC()->DrawLine(x_center, y_min, x_center-2, y_min-6);
|
||||
|
||||
}
|
||||
|
||||
return max_y-min_y;
|
||||
}
|
||||
|
||||
double Measurement::MRMS(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
double mean = 0;
|
||||
double rms = 0;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
for (int i=0 ; i<n ; i++)
|
||||
mean += y[i];
|
||||
mean /= n;
|
||||
for (int i=0 ; i<n ; i++)
|
||||
rms += (y[i]-mean)*(y[i]-mean);
|
||||
rms = sqrt(rms/n);
|
||||
|
||||
if (s) {
|
||||
int ym = s->voltToY(mean);
|
||||
for (int i=0 ; i<n ; i++)
|
||||
s->GetDC()->DrawLine(s->timeToX(x[i]), ym, s->timeToX(x[i]), s->voltToY(y[i]));
|
||||
}
|
||||
|
||||
return rms;
|
||||
}
|
||||
|
||||
double Measurement::MVSlice(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double u = 0;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
for (i=0 ; i<n-1 ; i++)
|
||||
if (x[i] <= m_param[0] && x[i+1] > m_param[0])
|
||||
break;
|
||||
|
||||
if (i == n-1)
|
||||
return ss_nan();
|
||||
|
||||
if (x[i+1] - x[i] == 0)
|
||||
return ss_nan();
|
||||
|
||||
u = y[i] + (y[i+1]-y[i]) * (m_param[0] - x[i]) / (x[i+1] - x[i]);
|
||||
|
||||
if (s) {
|
||||
s->GetDC()->DrawLine(s->timeToX(m_param[0]), s->GetY1(), s->timeToX(m_param[0]), s->GetY2());
|
||||
}
|
||||
|
||||
return u;
|
||||
}
|
||||
|
||||
double Measurement::MCharge(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
double q = 0;
|
||||
double x1, x2, y1, y2;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
for (int i=0 ; i<n ; i++) {
|
||||
if (x[i+1] >= m_param[0] && x[i] <= m_param[2]) {
|
||||
if (x[i] < m_param[0]) {
|
||||
x1 = m_param[0];
|
||||
y1 = y[i] + (y[i+1]-y[i]) * (m_param[0] - x[i]) / (x[i+1] - x[i]);
|
||||
} else {
|
||||
x1 = x[i];
|
||||
y1 = y[i];
|
||||
}
|
||||
if (x[i+1] > m_param[2]) {
|
||||
x2 = m_param[2];
|
||||
y2 = y[i] + (y[i+1]-y[i]) * (m_param[2] - x[i]) / (x[i+1] - x[i]);
|
||||
} else {
|
||||
x2 = x[i+1];
|
||||
y2 = y[i+1];
|
||||
}
|
||||
|
||||
q += 0.5 * (y1 + y2) * (x2 - x1);
|
||||
|
||||
if (s) {
|
||||
wxPoint p[4];
|
||||
p[0] = wxPoint(s->timeToX(x1), s->voltToY(0));
|
||||
p[1] = wxPoint(s->timeToX(x1), s->voltToY(y1));
|
||||
p[2] = wxPoint(s->timeToX(x2), s->voltToY(y2));
|
||||
p[3] = wxPoint(s->timeToX(x2), s->voltToY(0));
|
||||
|
||||
s->GetDC()->DrawPolygon(4, p, 0, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return q / 50; // signal into 50 Ohm
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
double Measurement::MFreq(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
double p = MPeriod(x, y, n, s);
|
||||
|
||||
if (ss_isnan(p) || p == 0)
|
||||
return ss_nan();
|
||||
|
||||
return 1000/p;
|
||||
}
|
||||
|
||||
double Measurement::MPeriod(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i, pos_edge, n_pos, n_neg;
|
||||
double miny, maxy, mean, t1, t2;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
miny = maxy = y[0];
|
||||
mean = 0;
|
||||
for (i=0 ; i<n ; i++) {
|
||||
if (y[i] > maxy)
|
||||
maxy = y[i];
|
||||
if (y[i] < miny)
|
||||
miny = y[i];
|
||||
mean += y[i];
|
||||
}
|
||||
if (n < 5 || maxy - miny < 10)
|
||||
return ss_nan();
|
||||
|
||||
mean = mean/n;
|
||||
|
||||
/* count zero crossings */
|
||||
n_pos = n_neg = 0;
|
||||
for (i=1 ; i<n ; i++) {
|
||||
if (y[i] > mean && y[i-1] <= mean)
|
||||
n_pos++;
|
||||
if (y[i] < mean && y[i-1] >= mean)
|
||||
n_neg++;
|
||||
}
|
||||
|
||||
/* search for zero crossing */
|
||||
for (i=n/2+2 ; i>1 ; i--) {
|
||||
if (n_pos > 1 && y[i] > mean && y[i-1] <= mean)
|
||||
break;
|
||||
if (n_neg > 1 && y[i] < mean && y[i-1] >= mean)
|
||||
break;
|
||||
}
|
||||
if (i == 1)
|
||||
for (i=n/2 ; i<n ; i++) {
|
||||
if (n_pos > 1 && y[i] > mean && y[i-1] <= mean)
|
||||
break;
|
||||
if (n_neg > 1 && y[i] < mean && y[i-1] >= mean)
|
||||
break;
|
||||
}
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
pos_edge = y[i] > mean;
|
||||
|
||||
t1 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
/* search next zero crossing */
|
||||
for (i++ ; i<n ; i++) {
|
||||
if (pos_edge && y[i] > mean && y[i-1] <= mean)
|
||||
break;
|
||||
if (!pos_edge && y[i] < mean && y[i-1] >= mean)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
if (s) {
|
||||
int ym = s->voltToY(mean);
|
||||
int x1 = s->timeToX(t1);
|
||||
int x2 = s->timeToX(t2);
|
||||
s->GetDC()->DrawLine(x1, ym-10, x1, ym+10);
|
||||
s->GetDC()->DrawLine(x2, ym-10, x2, ym+10);
|
||||
s->GetDC()->DrawLine(x1, ym, x2, ym);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym-2);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym+2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym-2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym+2);
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
double Measurement::MRise(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double miny, maxy, t1, t2, y10, y90;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
miny = maxy = y[0];
|
||||
for (i=0 ; i<n ; i++) {
|
||||
if (y[i] > maxy)
|
||||
maxy = y[i];
|
||||
if (y[i] < miny)
|
||||
miny = y[i];
|
||||
}
|
||||
|
||||
if (maxy - miny < 10)
|
||||
return ss_nan();
|
||||
|
||||
y10 = miny+0.1*(maxy-miny);
|
||||
y90 = miny+0.9*(maxy-miny);
|
||||
|
||||
/* search for 10% level crossing */
|
||||
for (i=n/2+2 ; i>1 ; i--)
|
||||
if (y[i] > y10 && y[i-1] <= y10)
|
||||
break;
|
||||
if (i == 1)
|
||||
for (i=n/2 ; i<n ; i++) {
|
||||
if (y[i] > y10 && y[i-1] <= y10)
|
||||
break;
|
||||
}
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t1 = (y10*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
/* search for 90% level crossing */
|
||||
for (i++ ; i<n ; i++)
|
||||
if (y[i] > y90 && y[i-1] <= y90)
|
||||
break;
|
||||
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (y90*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
if (s) {
|
||||
int y1 = s->voltToY(y10);
|
||||
int y2 = s->voltToY(y90);
|
||||
int x1 = s->timeToX(t1);
|
||||
int x2 = s->timeToX(t2);
|
||||
int ym = (y1 + y2)/2;
|
||||
|
||||
s->GetDC()->DrawLine(x1, y1+10, x1, ym-10);
|
||||
s->GetDC()->DrawLine(x2, y2-10, x2, ym+10);
|
||||
s->GetDC()->DrawLine(x1, ym, x2, ym);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym-2);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym+2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym-2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym+2);
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
double Measurement::MFall(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double miny, maxy, t1, t2, y10, y90;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
miny = maxy = y[0];
|
||||
for (i=0 ; i<n ; i++) {
|
||||
if (y[i] > maxy)
|
||||
maxy = y[i];
|
||||
if (y[i] < miny)
|
||||
miny = y[i];
|
||||
}
|
||||
|
||||
if (maxy - miny < 10)
|
||||
return ss_nan();
|
||||
|
||||
y10 = miny+0.1*(maxy-miny);
|
||||
y90 = miny+0.9*(maxy-miny);
|
||||
|
||||
/* search for 90% level crossing */
|
||||
for (i=n/2+2 ; i>1 ; i--)
|
||||
if (y[i] < y90 && y[i-1] >= y90)
|
||||
break;
|
||||
if (i == 1)
|
||||
for (i=n/2 ; i<n ; i++) {
|
||||
if (y[i] < y90 && y[i-1] >= y90)
|
||||
break;
|
||||
}
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t1 = (y90*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
/* search for 10% level crossing */
|
||||
for (i++ ; i<n ; i++)
|
||||
if (y[i] < y10 && y[i-1] >= y10)
|
||||
break;
|
||||
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (y10*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
if (s) {
|
||||
int y1 = s->voltToY(y90);
|
||||
int y2 = s->voltToY(y10);
|
||||
int x1 = s->timeToX(t1);
|
||||
int x2 = s->timeToX(t2);
|
||||
int ym = (y1 + y2)/2;
|
||||
|
||||
s->GetDC()->DrawLine(x1, y1-10, x1, ym+10);
|
||||
s->GetDC()->DrawLine(x2, y2+10, x2, ym-10);
|
||||
s->GetDC()->DrawLine(x1, ym, x2, ym);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym-2);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym+2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym-2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym+2);
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
double Measurement::MPosWidth(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double miny, maxy, mean, t1, t2;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
miny = maxy = y[0];
|
||||
for (i=0 ; i<n ; i++) {
|
||||
if (y[i] > maxy)
|
||||
maxy = y[i];
|
||||
if (y[i] < miny)
|
||||
miny = y[i];
|
||||
}
|
||||
mean = (miny + maxy)/2;
|
||||
|
||||
if (maxy - miny < 10)
|
||||
return ss_nan();
|
||||
|
||||
/* search for first pos zero crossing */
|
||||
for (i=1 ; i<n ; i++)
|
||||
if (y[i] > mean && y[i-1] <= mean)
|
||||
break;
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t1 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
/* search next neg zero crossing */
|
||||
for (i++ ; i<n ; i++)
|
||||
if (y[i] < mean && y[i-1] >= mean)
|
||||
break;
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
if (s) {
|
||||
int ym = s->voltToY(mean);
|
||||
int x1 = s->timeToX(t1);
|
||||
int x2 = s->timeToX(t2);
|
||||
s->GetDC()->DrawLine(x1, ym-10, x1, ym+10);
|
||||
s->GetDC()->DrawLine(x2, ym-10, x2, ym+10);
|
||||
s->GetDC()->DrawLine(x1, ym, x2, ym);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym-2);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym+2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym-2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym+2);
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
double Measurement::MNegWidth(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double miny, maxy, mean, t1, t2;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
miny = maxy = y[0];
|
||||
for (i=0 ; i<n ; i++) {
|
||||
if (y[i] > maxy)
|
||||
maxy = y[i];
|
||||
if (y[i] < miny)
|
||||
miny = y[i];
|
||||
}
|
||||
mean = (miny + maxy)/2;
|
||||
|
||||
if (maxy - miny < 10)
|
||||
return ss_nan();
|
||||
|
||||
/* search for first neg zero crossing */
|
||||
for (i=1 ; i<n ; i++)
|
||||
if (y[i] < mean && y[i-1] >= mean)
|
||||
break;
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t1 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
/* search next pos zero crossing */
|
||||
for (i++ ; i<n ; i++)
|
||||
if (y[i] > mean && y[i-1] <= mean)
|
||||
break;
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (mean*(x[i]-x[i-1])+x[i-1]*y[i]-x[i]*y[i-1])/(y[i]-y[i-1]);
|
||||
|
||||
if (s) {
|
||||
int ym = s->voltToY(mean);
|
||||
int x1 = s->timeToX(t1);
|
||||
int x2 = s->timeToX(t2);
|
||||
s->GetDC()->DrawLine(x1, ym-10, x1, ym+10);
|
||||
s->GetDC()->DrawLine(x2, ym-10, x2, ym+10);
|
||||
s->GetDC()->DrawLine(x1, ym, x2, ym);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym-2);
|
||||
s->GetDC()->DrawLine(x1, ym, x1+6, ym+2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym-2);
|
||||
s->GetDC()->DrawLine(x2, ym, x2-6, ym+2);
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
#define N_FIT 0
|
||||
|
||||
void linfit(double *x, double *y, int n, double &a, double &b)
|
||||
{
|
||||
int i;
|
||||
double sx, sxx, sy, syy, sxy;
|
||||
|
||||
sx = sxx = sy = syy = sxy = 0;
|
||||
|
||||
for (i=0 ; i<n ; i++) {
|
||||
sx += x[i];
|
||||
sy += y[i];
|
||||
sxy += x[i]*y[i];
|
||||
sxx += x[i]*x[i];
|
||||
syy += y[i]*y[i];
|
||||
}
|
||||
|
||||
b = (sxy - sx*sy/n) / (sxx - sx*sx/n);
|
||||
a = sy/n-b*sx/n;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
double Measurement::MChnDelay(double *x1, double *y1, double *x2, double *y2, int n, DOScreen *s)
|
||||
{
|
||||
int i, pol, i1l, i1r, i2l, i2r;
|
||||
double t1, t2, thr, a, b;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
thr = m_frame->GetTrgLevel(0) * 1000;
|
||||
pol = m_frame->GetTrgPolarity();
|
||||
for (i=1 ; i<n ; i++) {
|
||||
if (pol == 1 && y1[i] < thr && y1[i-1] >= thr)
|
||||
break;
|
||||
if (pol == 0 && y1[i] > thr && y1[i-1] <= thr)
|
||||
break;
|
||||
}
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t1 = (thr*(x1[i]-x1[i-1])+x1[i-1]*y1[i]-x1[i]*y1[i-1])/(y1[i]-y1[i-1]);
|
||||
|
||||
if (N_FIT > 0 && i>=N_FIT/2) {
|
||||
i1l = i-N_FIT/2;
|
||||
i1r = i1l+N_FIT-1;
|
||||
linfit(&x1[i-N_FIT/2], &y1[i-N_FIT/2], N_FIT, a, b);
|
||||
if (b != 0)
|
||||
t1 = (thr-a)/b;
|
||||
|
||||
if (s) {
|
||||
int xa = s->timeToX(x1[i1l]);
|
||||
int ya = s->voltToY(s->GetCurChn(), a+b*x1[i1l]);
|
||||
int xb = s->timeToX(x1[i1r]);
|
||||
int yb = s->voltToY(s->GetCurChn(), a+b*x1[i1r]);
|
||||
|
||||
s->GetDC()->DrawLine(xa, ya, xb, yb);
|
||||
}
|
||||
}
|
||||
|
||||
for (i=1 ; i<n ; i++) {
|
||||
if (pol == 1 && y2[i] < thr && y2[i-1] >= thr)
|
||||
break;
|
||||
if (pol == 0 && y2[i] > thr && y2[i-1] <= thr)
|
||||
break;
|
||||
}
|
||||
if (i == n)
|
||||
return ss_nan();
|
||||
|
||||
t2 = (thr*(x2[i]-x2[i-1])+x2[i-1]*y2[i]-x2[i]*y2[i-1])/(y2[i]-y2[i-1]);
|
||||
|
||||
if (N_FIT > 0 && i>=N_FIT/2) {
|
||||
i2l = i-N_FIT/2;
|
||||
i2r = i2l+N_FIT-1;
|
||||
linfit(&x2[i-N_FIT/2], &y2[i-N_FIT/2], N_FIT, a, b);
|
||||
if (b != 0)
|
||||
t2 = (thr-a)/b;
|
||||
|
||||
if (s) {
|
||||
int xa = s->timeToX(x2[i2l]);
|
||||
int ya = s->voltToY(s->GetCurChn(), a+b*x2[i2l]);
|
||||
int xb = s->timeToX(x2[i2r]);
|
||||
int yb = s->voltToY(s->GetCurChn(), a+b*x2[i2r]);
|
||||
|
||||
s->GetDC()->DrawLine(xa, ya, xb, yb);
|
||||
}
|
||||
}
|
||||
|
||||
if (s) {
|
||||
if (s->GetChnOn(0, (s->GetCurChn()+1)%4)) { /// ### TBG: change board index
|
||||
int ym1 = s->voltToY(s->GetCurChn(), thr);
|
||||
int ym2 = s->voltToY((s->GetCurChn()+1)%4, thr);
|
||||
int xa = s->timeToX(t1);
|
||||
int xb = s->timeToX(t2);
|
||||
int ymm = (ym1+ym2)/2;
|
||||
if (ym1 < ym2) {
|
||||
s->GetDC()->DrawLine(xa, ym1-10, xa, ymm+10);
|
||||
s->GetDC()->DrawLine(xb, ymm-10, xb, ym2+10);
|
||||
} else {
|
||||
s->GetDC()->DrawLine(xa, ym1+10, xa, ymm-10);
|
||||
s->GetDC()->DrawLine(xb, ymm+10, xb, ym2-10);
|
||||
}
|
||||
s->GetDC()->DrawLine(xa, ymm, xb, ymm);
|
||||
s->GetDC()->DrawLine(xa, ymm, xa+6, ymm-2);
|
||||
s->GetDC()->DrawLine(xa, ymm, xa+6, ymm+2);
|
||||
s->GetDC()->DrawLine(xb, ymm, xb-6, ymm-2);
|
||||
s->GetDC()->DrawLine(xb, ymm, xb-6, ymm+2);
|
||||
}
|
||||
}
|
||||
|
||||
return t2 - t1;
|
||||
}
|
||||
|
||||
double Measurement::MHSlice(double *x, double *y, int n, DOScreen *s)
|
||||
{
|
||||
int i;
|
||||
double tmin = ss_nan();
|
||||
double t, dtmin = 1E6;;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
for (i=0 ; i<n-1 ; i++) {
|
||||
if ((y[i] <= m_param[1] && y[i+1] > m_param[1]) ||
|
||||
(y[i] >= m_param[1] && y[i+1] < m_param[1])) {
|
||||
|
||||
if (y[i+1] - y[i] == 0)
|
||||
continue;
|
||||
t = x[i] + (x[i+1]-x[i]) * (m_param[1] - y[i]) / (y[i+1] - y[i]);
|
||||
if (fabs(t - m_param[0]) < dtmin) {
|
||||
dtmin = fabs(t - m_param[0]);
|
||||
tmin = t;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (s) {
|
||||
s->GetDC()->DrawLine(s->GetX1(), s->voltToY(m_param[1]), s->GetX2(), s->voltToY(m_param[1]));
|
||||
}
|
||||
|
||||
return tmin;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
$Id: Measurement.h 21271 2014-02-17 15:20:55Z ritt $
|
||||
*/
|
||||
|
||||
class DOScreen;
|
||||
class DOFrame;
|
||||
|
||||
class Measurement
|
||||
{
|
||||
protected:
|
||||
DOFrame *m_frame;
|
||||
wxString m_name;
|
||||
int m_index;
|
||||
double m_value;
|
||||
double m_param[4];
|
||||
double *m_statArray;
|
||||
int m_statIndex;
|
||||
int m_nMeasured;
|
||||
int m_nStat;
|
||||
double m_vsum;
|
||||
double m_vvsum;
|
||||
double m_min;
|
||||
double m_max;
|
||||
|
||||
public:
|
||||
/** Constructor & Desctructor */
|
||||
Measurement(DOFrame *frame, int index);
|
||||
~Measurement();
|
||||
|
||||
wxString GetName();
|
||||
wxString GetUnit();
|
||||
double Measure(double *x1, double *y1, double *x2, double *y2, int n, bool update, DOScreen *s);
|
||||
void Measure(double *x1, double *y1, double *x2, double *y2, int n);
|
||||
wxString GetString();
|
||||
wxString GetStat();
|
||||
void SetNStat(int n);
|
||||
int GetNStat() { return m_nStat; }
|
||||
int GetNMeasured() { return m_nMeasured; }
|
||||
void ResetStat();
|
||||
double *GetArray() { return m_statArray; }
|
||||
void SetParam(int i, double p) { if (i<4) m_param[i] = p; }
|
||||
double GetParam(int i) { return m_param[i]; }
|
||||
|
||||
static const int N_MEASUREMENTS = 13;
|
||||
|
||||
private:
|
||||
double MLevel(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MPkPk(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MRMS(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MVSlice(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MCharge(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MFreq(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MPeriod(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MRise(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MFall(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MPosWidth(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MNegWidth(double *x1, double *y1, int n, DOScreen *s);
|
||||
double MChnDelay(double *x1, double *y1, double *x2, double *y2, int n, DOScreen *s);
|
||||
double MHSlice(double *x1, double *y1, int n, DOScreen *s);
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Osci.h
|
||||
* DRS oscilloscope header file
|
||||
* $Id: Osci.h 21496 2014-09-26 14:55:49Z ritt $
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
unsigned short Year;
|
||||
unsigned short Month;
|
||||
unsigned short Day;
|
||||
unsigned short Hour;
|
||||
unsigned short Minute;
|
||||
unsigned short Second;
|
||||
unsigned short Milliseconds;
|
||||
} TIMESTAMP;
|
||||
|
||||
#define TM_AUTO 0
|
||||
#define TM_NORMAL 1
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
class Osci;
|
||||
|
||||
class OsciThread : public wxThread
|
||||
{
|
||||
public:
|
||||
OsciThread(Osci *o);
|
||||
bool IsIdle();
|
||||
void *Entry();
|
||||
void ResetSW();
|
||||
void Enable(bool flag);
|
||||
void StopThread();
|
||||
bool IsFinished() { return m_finished; }
|
||||
|
||||
private:
|
||||
Osci *m_osci;
|
||||
wxStopWatch m_sw1, m_sw2;
|
||||
bool m_enabled;
|
||||
bool m_active;
|
||||
bool m_finished;
|
||||
bool m_stopThread;
|
||||
};
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
class Osci
|
||||
{
|
||||
public:
|
||||
Osci(double samplingSpeed = 5, bool mthread = true);
|
||||
~Osci();
|
||||
void StopThread(void);
|
||||
int ScanBoards();
|
||||
int GetNumberOfBoards() { return m_drs->GetNumberOfBoards(); }
|
||||
DRSBoard *GetBoard(int i) { return m_drs->GetBoard(i); }
|
||||
DRSBoard *GetCurrentBoard() { return m_drs->GetBoard(m_board); }
|
||||
int GetCurrentBoardIndex() { return m_board; }
|
||||
DRS *GetDRS() { return m_drs; }
|
||||
bool GetError(char *str, int size) { return m_drs->GetError(str, size); }
|
||||
void CheckTimingCalibration();
|
||||
void SelectBoard(int board);
|
||||
void SelectChannel(int firstChannel, int chnSection);
|
||||
void SetMultiBoard(bool multi);
|
||||
bool IsMultiBoard() { return m_multiBoard; }
|
||||
void SetRunning(bool flag);
|
||||
void Enable(bool flag);
|
||||
bool IsRunning() { return m_running; }
|
||||
void SetSingle(bool flag);
|
||||
bool IsSingle() { return m_single; }
|
||||
void SetArmed(bool flag) { m_armed = flag; }
|
||||
bool IsArmed() { return m_armed; }
|
||||
bool IsIdle();
|
||||
int GetWaveformDepth(int channel);
|
||||
double GetWaveformLength() { return m_waveDepth / GetSamplingSpeed(); }
|
||||
float *GetWaveform(int b, int i) { return (float *)m_waveform[b][i]; }
|
||||
float *GetTime(int board, int channel);
|
||||
int GetChip() { return m_chip; }
|
||||
void SetSamplingSpeed(double freq);
|
||||
double GetSamplingSpeed();
|
||||
double GetTrueSamplingSpeed();
|
||||
double GetMinSamplingSpeed();
|
||||
double GetMaxSamplingSpeed();
|
||||
bool IsTCalibrated();
|
||||
bool IsVCalibrated();
|
||||
bool GetTimeCalibration(int chip, int channel, int mode, float *time, bool force=false);
|
||||
void Start();
|
||||
void Stop();
|
||||
void DrainEvents();
|
||||
void SingleTrigger();
|
||||
void ReadWaveforms();
|
||||
int SaveWaveforms(MXML_WRITER *, int);
|
||||
bool HasTriggered();
|
||||
bool HasNewEvent();
|
||||
void SetTriggerLevel(double level);
|
||||
void SetTriggerPolarity(bool negative);
|
||||
void SetIndividualTriggerLevel(int i, double level);
|
||||
void SetTriggerDelay(int delay);
|
||||
int GetTriggerDelay();
|
||||
double GetTriggerDelayNs();
|
||||
void SetTriggerMode(int mode) { m_trgMode = mode; }
|
||||
int GetTriggerMode() { return m_trgMode; }
|
||||
void SetTriggerSource(int source);
|
||||
int GetTriggerSource() { return m_trgSource[m_board]; }
|
||||
void SetTriggerConfig(int tc);
|
||||
void SetRefclk(int board, bool flag);
|
||||
void SetChnOn(int board, int chn, bool flag);
|
||||
void SetClkOn(bool flag);
|
||||
void SetEventSerial(int serial) { m_evSerial = serial; }
|
||||
void SetCalibVoltage(bool flag, double voltage);
|
||||
void SetInputRange(double center);
|
||||
double GetInputRange() { return m_inputRange; }
|
||||
double GetCalibratedInputRange();
|
||||
unsigned int GetScaler(int channel);
|
||||
void SetCalibrated(bool flag) { m_calibrated = flag; }
|
||||
void SetCalibrated2(bool flag) { m_calibrated2 = flag; }
|
||||
void SetTCalOn(bool flag) { m_tcalon = flag; }
|
||||
bool IsTCalOn() { return m_tcalon; }
|
||||
void SetRotated(bool flag) { m_rotated = flag; }
|
||||
void SetSpikeRemoval(bool flag) { m_spikeRemoval = flag; }
|
||||
void CorrectTriggerPoint(double t);
|
||||
void RemoveSpikes(int board, bool cascading);
|
||||
int CheckWaveforms();
|
||||
bool SkipDisplay(void) { return m_skipDisplay; }
|
||||
int GetChnSection(void) { return m_chnSection; }
|
||||
char *GetDebugMsg(void) { return m_debugMsg; }
|
||||
|
||||
private:
|
||||
DRS *m_drs;
|
||||
OsciThread *m_thread;
|
||||
bool m_running;
|
||||
bool m_single;
|
||||
bool m_armed;
|
||||
double m_samplingSpeed;
|
||||
int m_nBoards;
|
||||
float m_waveform[MAX_N_BOARDS][4][2048];
|
||||
float m_refwaveform[2048];
|
||||
unsigned char m_wavebuffer[MAX_N_BOARDS][9*1024*2];
|
||||
float m_time[MAX_N_BOARDS][4][2048];
|
||||
float m_timeClk[MAX_N_BOARDS][1024];
|
||||
int m_triggerCell[MAX_N_BOARDS];
|
||||
int m_writeSR[MAX_N_BOARDS];
|
||||
int m_boardSerial[MAX_N_BOARDS];
|
||||
int m_waveDepth;
|
||||
int m_trgMode;
|
||||
int m_trgSource[MAX_N_BOARDS];
|
||||
bool m_trgNegative;
|
||||
int m_trgDelay;
|
||||
double m_trgLevel[4];
|
||||
bool m_chnOn[MAX_N_BOARDS][4];
|
||||
bool m_clkOn;
|
||||
bool m_refClk[MAX_N_BOARDS];
|
||||
bool m_calibOn;
|
||||
int m_evSerial;
|
||||
TIMESTAMP m_evTimestamp;
|
||||
bool m_calibrated;
|
||||
bool m_calibrated2;
|
||||
bool m_tcalon;
|
||||
bool m_rotated;
|
||||
int m_nDRS;
|
||||
int m_board;
|
||||
int m_chip;
|
||||
int m_chnOffset;
|
||||
int m_chnSection;
|
||||
bool m_spikeRemoval;
|
||||
double m_inputRange;
|
||||
bool m_skipDisplay;
|
||||
bool m_multiBoard;
|
||||
char m_debugMsg[256];
|
||||
};
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* TriggerDialog.cpp
|
||||
* Modal Trigger Configuration Dialog class
|
||||
* $Id: TriggerDialog.cpp 22292 2016-04-28 10:31:04Z ritt $
|
||||
*/
|
||||
|
||||
#include "DRSOscInc.h"
|
||||
|
||||
TriggerDialog::TriggerDialog( wxWindow* parent )
|
||||
:
|
||||
TriggerDialog_fb( parent )
|
||||
{
|
||||
m_frame = (DOFrame *)parent;
|
||||
m_board = 0;
|
||||
|
||||
UpdateControls();
|
||||
}
|
||||
|
||||
void TriggerDialog::UpdateControls()
|
||||
{
|
||||
if (!m_frame->IsTrgConfigEnabled()) {
|
||||
m_cbOR1->Disable();
|
||||
m_cbOR2->Disable();
|
||||
m_cbOR3->Disable();
|
||||
m_cbOR4->Disable();
|
||||
m_cbOREXT->Disable();
|
||||
|
||||
m_cbAND1->Disable();
|
||||
m_cbAND2->Disable();
|
||||
m_cbAND3->Disable();
|
||||
m_cbAND4->Disable();
|
||||
m_cbANDEXT->Disable();
|
||||
|
||||
m_cbTrans->Disable();
|
||||
|
||||
m_tbLevel1->Disable();
|
||||
m_tbLevel2->Disable();
|
||||
m_tbLevel3->Disable();
|
||||
m_tbLevel4->Disable();
|
||||
} else {
|
||||
m_cbOR1->Enable();
|
||||
m_cbOR2->Enable();
|
||||
m_cbOR3->Enable();
|
||||
m_cbOR4->Enable();
|
||||
m_cbOREXT->Enable();
|
||||
|
||||
m_cbAND1->Enable();
|
||||
m_cbAND2->Enable();
|
||||
m_cbAND3->Enable();
|
||||
m_cbAND4->Enable();
|
||||
m_cbANDEXT->Enable();
|
||||
|
||||
m_cbTrans->Enable();
|
||||
|
||||
m_tbLevel1->Enable();
|
||||
m_tbLevel2->Enable();
|
||||
m_tbLevel3->Enable();
|
||||
m_tbLevel4->Enable();
|
||||
|
||||
int tc = m_frame->GetTriggerConfig();
|
||||
m_cbOR1->SetValue((tc & (1<<0))>0);
|
||||
m_cbOR2->SetValue((tc & (1<<1))>0);
|
||||
m_cbOR3->SetValue((tc & (1<<2))>0);
|
||||
m_cbOR4->SetValue((tc & (1<<3))>0);
|
||||
m_cbOREXT->SetValue((tc & (1<<4))>0);
|
||||
|
||||
m_cbAND1->SetValue((tc & (1<<8))>0);
|
||||
m_cbAND2->SetValue((tc & (1<<9))>0);
|
||||
m_cbAND3->SetValue((tc & (1<<10))>0);
|
||||
m_cbAND4->SetValue((tc & (1<<11))>0);
|
||||
m_cbANDEXT->SetValue((tc & (1<<12))>0);
|
||||
|
||||
m_cbTrans->SetValue((tc & (1<<15))>0);
|
||||
|
||||
wxString s;
|
||||
s.Printf(wxT("%1.3lf"), m_frame->GetTrgLevel(0));
|
||||
m_tbLevel1->SetValue(s);
|
||||
s.Printf(wxT("%1.3lf"), m_frame->GetTrgLevel(1));
|
||||
m_tbLevel2->SetValue(s);
|
||||
s.Printf(wxT("%1.3lf"), m_frame->GetTrgLevel(2));
|
||||
m_tbLevel3->SetValue(s);
|
||||
s.Printf(wxT("%1.3lf"), m_frame->GetTrgLevel(3));
|
||||
m_tbLevel4->SetValue(s);
|
||||
}
|
||||
}
|
||||
|
||||
void TriggerDialog::OnClose( wxCommandEvent& event )
|
||||
{
|
||||
this->Hide();
|
||||
}
|
||||
|
||||
void TriggerDialog::OnButton( wxCommandEvent& event )
|
||||
{
|
||||
if (event.GetId() == ID_TRANS) {
|
||||
DRSBoard *b = m_frame->GetOsci()->GetCurrentBoard();
|
||||
if (b->GetFirmwareVersion() < 21699) {
|
||||
wxMessageBox(wxT("For this operation a boards with firmware\nrevision >= 21699 is required"),
|
||||
wxT("DRS Oscilloscope"), wxOK | wxICON_STOP, this);
|
||||
m_cbTrans->SetValue(false);
|
||||
return;
|
||||
}
|
||||
if (event.IsChecked()) {
|
||||
m_cbOREXT->SetValue(false);
|
||||
m_cbOREXT->Disable();
|
||||
m_cbANDEXT->SetValue(false);
|
||||
m_cbANDEXT->Disable();
|
||||
} else {
|
||||
m_cbOREXT->Enable();
|
||||
m_cbANDEXT->Enable();
|
||||
}
|
||||
}
|
||||
m_frame->SetTriggerConfig(event.GetId(), event.IsChecked());
|
||||
}
|
||||
|
||||
void TriggerDialog::OnTriggerLevel( wxCommandEvent& event )
|
||||
{
|
||||
if (event.GetId() == ID_LEVEL1)
|
||||
m_frame->SetTrgLevel(0, atof(m_tbLevel1->GetValue().mb_str()));
|
||||
if (event.GetId() == ID_LEVEL2)
|
||||
m_frame->SetTrgLevel(1, atof(m_tbLevel2->GetValue().mb_str()));
|
||||
if (event.GetId() == ID_LEVEL3)
|
||||
m_frame->SetTrgLevel(2, atof(m_tbLevel3->GetValue().mb_str()));
|
||||
if (event.GetId() == ID_LEVEL4)
|
||||
m_frame->SetTrgLevel(3, atof(m_tbLevel4->GetValue().mb_str()));
|
||||
}
|
||||
|
||||
void TriggerDialog::SetTriggerLevel(double level)
|
||||
{
|
||||
wxString s;
|
||||
s.Printf(wxT("%1.3lf"), level);
|
||||
m_tbLevel1->SetValue(s);
|
||||
m_tbLevel2->SetValue(s);
|
||||
m_tbLevel3->SetValue(s);
|
||||
m_tbLevel4->SetValue(s);
|
||||
}
|
||||
|
||||
void TriggerDialog::SelectBoard(int board)
|
||||
{
|
||||
m_board = board;
|
||||
UpdateControls();
|
||||
}
|
||||
@@ -0,0 +1,34 @@
|
||||
#ifndef __TriggerDialog__
|
||||
#define __TriggerDialog__
|
||||
|
||||
/*
|
||||
$Id: TriggerDialog.h 22292 2016-04-28 10:31:04Z ritt $
|
||||
*/
|
||||
|
||||
class DOFrame;
|
||||
|
||||
#include "DRSOsc.h"
|
||||
|
||||
/** Implementing TriggerDialog_fb */
|
||||
class TriggerDialog : public TriggerDialog_fb
|
||||
{
|
||||
protected:
|
||||
// Handlers for TriggerDialog_fb events.
|
||||
void OnClose( wxCommandEvent& event );
|
||||
void OnButton( wxCommandEvent& event );
|
||||
void OnTriggerLevel( wxCommandEvent& event );
|
||||
|
||||
public:
|
||||
/** Constructor */
|
||||
TriggerDialog( wxWindow* parent );
|
||||
|
||||
void SetTriggerLevel(double level);
|
||||
void SelectBoard(int board);
|
||||
|
||||
private:
|
||||
DOFrame *m_frame;
|
||||
int m_board;
|
||||
void UpdateControls();
|
||||
};
|
||||
|
||||
#endif // __TriggerDialog__
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,27 @@
|
||||
/* XPM */
|
||||
static const char *down_xpm[]={
|
||||
"28 20 4 1",
|
||||
". c None",
|
||||
"a c #808080",
|
||||
"b c #c0c0c0",
|
||||
"# c #ffffff",
|
||||
"............................",
|
||||
"............................",
|
||||
"............................",
|
||||
".#########################a.",
|
||||
".#bbbbbbbbbbbbbbbbbbbbbbbba.",
|
||||
"..bbbbbbbbbbbbbbbbbbbbbbbba.",
|
||||
"...bbbbbbbbbbbbbbbbbbbbbbaa.",
|
||||
"....bbbbbbbbbbbbbbbbbbbbaa..",
|
||||
".....bbbbbbbbbbbbbbbbbbaa...",
|
||||
"......bbbbbbbbbbbbbbbbaa....",
|
||||
".......bbbbbbbbbbbbbbaa.....",
|
||||
"........bbbbbbbbbbbbaa......",
|
||||
".........bbbbbbbbbbaa.......",
|
||||
"..........bbbbbbbbaa........",
|
||||
"...........bbbbbbaa.........",
|
||||
"............bbbbaa..........",
|
||||
".............bbaa...........",
|
||||
"..............aa............",
|
||||
"............................",
|
||||
"............................"};
|
||||
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Reference in New Issue
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