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42a1aa049a
Update README.md
master
ritt
2026-04-13 13:25:12 +02:00
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0e0df37791
Fixed time and waveform points in rec->Branch
origin/master
origin/HEAD
ritt
2023-02-06 13:58:42 +01:00
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80b3af753e
Replaced strncpy by strlcpy
ritt
2023-02-06 13:27:31 +01:00
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be55a5ed0c
Replaced sprintf by snprintf
ritt
2023-02-06 13:25:16 +01:00
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ebad2db484
README.md edited online with Bitbucket
ritt
2022-04-25 09:48:24 +00:00
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82f6514d7c
README.md edited online with Bitbucket
ritt
2022-04-25 07:24:26 +00:00
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4c9938ec3d
Merge branch 'master' of bitbucket.org:ritt/drs4eb
ritt
2022-04-25 09:18:33 +02:00
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6eb2304605
Added explicit file name extensions
ritt
2022-04-25 09:18:21 +02:00
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c25af88258
Added 41-drs.rules and raspi.txt
ritt
2021-12-17 15:19:12 +01:00
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45c5755882
Fixed issue with channel depth in 2048 bin mode
ritt
2021-08-10 15:30:01 +02:00
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7a630c5f70
Added missing -DUSE_DRS_MUTEX
ritt
2021-08-10 13:28:25 +02:00
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f77c85ad65
Moved temperature readout into Osci thread
ritt
2021-08-10 13:14:08 +02:00
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ef759a59f8
Fixed alignment errors
ritt
2021-08-10 13:13:03 +02:00
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592497bb5a
Updated mxml
ritt
2021-08-10 10:42:42 +02:00
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5edb5cf4b7
Added CMake project, removed obsolete libusb function
ritt
2021-08-10 10:42:29 +02:00
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cefd496089
Ignore .idea
ritt
2020-09-03 15:11:42 +02:00
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878f9632c3
Updated manual
ritt
2020-08-18 10:49:02 +02:00
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6b7f0c83ef
Fixed install dir
ritt
2019-06-20 18:05:10 +02:00
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235024cf76
Fixed error in CMakeLists.txt
ritt
2019-06-20 17:33:44 +02:00
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96b1076ec4
Added mxml as subproject. CMake still gives errors.
ritt
2019-06-20 17:20:00 +02:00
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e579e22cbf
Added initial Cmake file for drsosc
ritt
2019-06-19 18:05:35 +02:00
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e0035fd963
Created initial CMakeLists.txt
ritt
2019-06-17 22:14:03 +02:00
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725294e96a
Made read_binary.C work with current data format
ritt
2019-05-27 17:15:08 +02:00
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8f8c01897a
Added missiong wxT()
ritt
2019-01-14 08:44:31 +01:00
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ce588a1b6d
Merge branch 'master' of bitbucket.org:ritt/drs4eb
ritt
2019-01-09 10:57:42 +01:00
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9418b346bc
Switched to libc++ in Makefile, fixed casting error in wxMessageBox
ritt
2019-01-09 10:57:28 +01:00
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53ec6a7558
Ignore some windows files
ritt
2018-12-11 17:53:33 +01:00
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6b57df374f
Added drs_exam_2018.cpp
ritt
2017-12-13 11:16:21 +01:00
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426776ab0c
Changed comment
ritt
2017-12-12 14:03:06 +01:00
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aded8e478f
Fixed code for external trigger
ritt
2017-12-12 13:58:01 +01:00
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4fc3bab402
Updated XCode project file
ritt
2017-11-07 14:10:27 +01:00
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c4b903e540
Merge branch 'master' of bitbucket.org:ritt/drs4eb
ritt
2017-10-11 11:03:40 +02:00
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a0019cc7da
Fixed a few issues in chip test routine
ritt
2017-10-11 11:03:28 +02:00
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7916c5dbab
Compiled drscl.exe
ritt
2017-10-11 10:03:20 +02:00
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7902250530
Added GPL
ritt
2017-10-11 09:40:31 +02:00
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ed441935a7
Optimized chip tests for good new chips with lower leakage current
ritt
2017-10-10 17:36:34 +02:00
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9df66d5c96
Implemented “-l” option to check USB
ritt
2017-04-12 10:26:50 +02:00
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8c916cab22
Updated Visual Studio project file
ritt
2017-01-13 13:49:05 +01:00
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9e6aa0e059
Recompiled under Windows
ritt
2017-01-09 17:06:59 +01:00
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8461281a67
Optimized chip test for new test board, implemented leakage current limit of 100 pA
ritt
2017-01-09 16:54:01 +01:00
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118ded9ac0
Added optional histogram output in chip test
ritt
2016-12-05 14:03:06 +01:00
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bcc7e30369
Implemented measurement of leakage currents
ritt
2016-12-01 16:16:37 +01:00
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dfe33dc32d
Made chip test work with normal V5 board
ritt
2016-12-01 12:25:02 +01:00
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50964d81ca
Updated examples to new project structure
ritt
2016-12-01 09:31:25 +01:00
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8d814a6705
Switch EXT properly when entering / exiting transparent mode
ritt
2016-12-01 08:50:23 +01:00
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fab70c5365
Fixed problem when no trigger channel is selected
ritt
2016-11-30 17:38:23 +01:00
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8906b39e7d
Fixed trigger display if no channel is selected
ritt
2016-11-30 17:34:59 +01:00
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8004cfb357
Fixed color of trigger level display at bottom of screen
ritt
2016-11-30 17:22:34 +01:00
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51134fb2db
Re-arranged trigger source configuration
ritt
2016-11-30 17:14:46 +01:00
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5ab32c3921
Made transparent trigger mode wok in multi-board configuration
ritt
2016-11-28 16:57:50 +01:00
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12709a248e
Added trigger schemata
ritt
2016-11-25 17:01:54 +01:00
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14420607f2
Implemented variable readout delay in firmware, not at version 30000
ritt
2016-11-25 09:14:13 +01:00
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403dc702fb
Implemented readout delay
ritt
2016-11-24 17:19:27 +01:00
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16b6359c37
Added readout delay to register map
ritt
2016-11-24 14:54:17 +01:00
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bdd6b7fcad
Align cell #0 of each channel instead of 700. Same result, but less confusing.
ritt
2016-11-24 14:40:27 +01:00
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017f72c313
Added docs tree
ritt
2016-11-21 17:16:07 +01:00
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43ec896a4b
Recompiled firmware
ritt
2016-11-14 16:33:59 +01:00
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93a27c595f
Ignore executables
ritt
2016-11-14 16:01:36 +01:00
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f61e25d591
README.md edited online with Bitbucket
ritt
2016-11-14 14:46:39 +00:00
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7bca3829fa
Copied files over from SVN repositories
ritt
2016-11-14 15:38:40 +01:00