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ritt 6b57df374f Added drs_exam_2018.cpp
2017-12-13 11:16:21 +01:00
docs
Added trigger schemata
2016-11-25 17:01:54 +01:00
firmware
Implemented variable readout delay in firmware, not at version 30000
2016-11-25 09:14:13 +01:00
software
Added drs_exam_2018.cpp
2017-12-13 11:16:21 +01:00
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README.md
README.md edited online with Bitbucket
2016-11-14 14:46:39 +00:00

README.md

README

DRS4 Evaluation Board firmware and software

  • VHDL firmware for Xilinx ISE
  • drscl command line interface to DRS4 Evaluation Board
  • drsosc oscilloscope program for DRS4 Evaluation Board

Contact

Stefan Ritt stefan.ritt@psi.ch

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Readme 89 MiB
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C++ 63.2%
VHDL 16.5%
C 14.6%
IGOR Pro 3.4%
Assembly 1.3%
Other 1%