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22 Commits
v1 ... master

Author SHA1 Message Date
Noah Piqué
b98c372f7e version13 
version 11/12 auch noch
 2025-05-23 11:44:24 +02:00
Noah Piqué
ec01320c33 tecware_v10 
errorhandling finish
 2024-12-18 16:29:51 +01:00
Noah Piqué
2fbc3b3023 v08 - add error handling 2024-10-18 10:54:47 +02:00
Noah Piqué
dc2dedf822 v07 pid and negative voltage limit change 
now the voltage limits are from -5 to +12V for the output and the pid loop is now implemented, but not tested yet
 2024-10-10 14:32:26 +02:00
Noah Piqué
670b2aebed version 6 
foundnew ref resistance for temp measurement!
 2024-09-19 12:19:46 +02:00
pique_n
2ba2c9c5bf version 5 2024-05-06 10:10:15 +02:00
pique_n
427106670b v5 - adding preassure sensor (lid status) 2024-05-02 09:58:56 +02:00
pique_n
213ee88c7a updates 
small bugfixes
 2024-02-23 11:25:48 +01:00
pique_n
53a44a4075 bugfix R_Petlier and bootloader init 2023-11-07 11:13:44 +01:00
pique_n
715cb5f478 Update README.md 2022-12-23 10:32:18 +01:00
pique_n
634cff8267 Delete install_tec_raspi.txt 2022-12-22 11:08:23 +00:00
pique_n
055817fe15 update name 2022-12-20 16:54:20 +01:00
pique_n
99a67c6144 bug fix watchdog 2022-12-16 10:10:49 +01:00
Noah Piqué
36d1448b7d adding binary 2022-12-15 15:10:39 +01:00
Noah Piqué
b3bc3ba61a implement watchdog 2022-12-15 15:10:03 +01:00
Noah Piqué
9ebeab7698 starting v3 2022-12-15 15:09:22 +01:00
Noah Piqué
2a9de72dc9 add binary 2022-12-15 15:07:20 +01:00
Noah Piqué
ed6b7160de add eeprom feature v2 2022-12-15 15:04:05 +01:00
pique_n
f654257dd8 add boOK 2022-12-14 13:57:45 +01:00
Noah Piqué
9476d996ff working on bug fix flash save 2022-12-14 08:32:28 +01:00
pique_n
54fef083bf change to stm32cubeide 2022-12-13 15:43:45 +01:00
pique_n
7cadcdbc28 add first rev of eeprom 
and ref voltage in varhandler
 2022-12-13 14:30:40 +01:00
125 changed files with 61207 additions and 18601 deletions
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1
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9
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View File

File diff suppressed because one or more lines are too long

32
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3
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10
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74
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org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()}
org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true}
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"}
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"}
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)}
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"}
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false}
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"}
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem=Warning
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return value not evaluated\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false}
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"}
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true}
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"}
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"}

7
.settings/stm32cubeide.project.prefs
View File

@ -1,5 +1,4 @@
2F62501ED4689FB349E356AB974DBE57=E4D6F48A5E072BF280AE61DC22F0EFF9
66BE74F758C12D739921AEA421D593D3=4
8DF89ED150041C4CBC7CB9A9CAA90856=E4D6F48A5E072BF280AE61DC22F0EFF9
DC22A860405A8BF2F2C095E5B6529F12=F216BE080F2C17807F72AFE2348FF317
2F62501ED4689FB349E356AB974DBE57=A086EFBE51DAEF3695BC2E933AC3927D
8DF89ED150041C4CBC7CB9A9CAA90856=A086EFBE51DAEF3695BC2E933AC3927D
DC22A860405A8BF2F2C095E5B6529F12=4D49891D8384AE8B8742A84C899C7E0C
eclipse.preferences.version=1

1
.vscode/.cortex-debug.registers.state.json vendored
View File

@ -1 +0,0 @@
[]

27
.vscode/c_cpp_properties.json vendored
View File

@ -1,27 +0,0 @@
{
"configurations": [
{
"name": "STM32",
"includePath": [
"Core",
"Core/Application",
"Core/Drivers",
"Core/Inc",
"Core/Toolbox",
"Drivers/CMSIS/Device/ST/STM32L4xx/Include",
"Drivers/CMSIS/Include",
"Drivers/STM32L4xx_HAL_Driver/Inc",
"Drivers/STM32L4xx_HAL_Driver/Inc/Legacy",
"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2",
"Middlewares/Third_Party/FreeRTOS/Source/include",
"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
],
"defines": [
"STM32L432xx",
"USE_HAL_DRIVER"
],
"compilerPath": "C:\\USERS\\PIQUE_N\\APPDATA\\ROAMING\\CODE\\USER\\GLOBALSTORAGE\\BMD.STM32-FOR-VSCODE\\@XPACK-DEV-TOOLS\\ARM-NONE-EABI-GCC\\11.3.1-1.1.2\\.CONTENT\\BIN\\ARM-NONE-EABI-GCC.EXE"
}
],
"version": 4
}

32
.vscode/launch.json vendored
View File

@ -1,32 +0,0 @@
{
"configurations": [
{
"showDevDebugOutput": true,
"cwd": "${workspaceRoot}",
"executable": "./build/PeltierControllerV3.elf",
"name": "Debug STM32",
"request": "launch",
"type": "cortex-debug",
"servertype": "openocd",
"preLaunchTask": "Build STM",
"device": "stlink",
"configFiles": [
"openocd.cfg"
]
},
{
"showDevDebugOutput": "parsed",
"cwd": "${workspaceRoot}",
"executable": "./build/PeltierControllerV3.elf",
"name": "Attach STM32",
"request": "attach",
"type": "cortex-debug",
"servertype": "openocd",
"preLaunchTask": "Build STM",
"device": "stm32l432",
"configFiles": [
"openocd.cfg"
]
}
]
}

18
.vscode/settings.json vendored
View File

@ -1,16 +1,6 @@
{
"C_Cpp.errorSquiggles": "Disabled",
"files.associations": {
"peco_peltiercontroller.h": "c",
"cmsis_os2.h": "c",
"varh_variablehandler.h": "c"
},
"cortex-debug.armToolchainPath": "c:\\Users\\pique_n\\AppData\\Roaming\\Code\\User\\globalStorage\\bmd.stm32-for-vscode\\@xpack-dev-tools\\arm-none-eabi-gcc\\11.3.1-1.1.2\\.content\\bin",
"cortex-debug.openocdPath": "C:\\USERS\\PIQUE_N\\APPDATA\\ROAMING\\CODE\\USER\\GLOBALSTORAGE\\BMD.STM32-FOR-VSCODE\\@XPACK-DEV-TOOLS\\OPENOCD\\0.11.0-5.1\\.CONTENT\\BIN\\OPENOCD.EXE",
"cortex-debug.variableUseNaturalFormat": false,
"stm32-for-vscode.openOCDPath": "C:\\USERS\\PIQUE_N\\APPDATA\\ROAMING\\CODE\\USER\\GLOBALSTORAGE\\BMD.STM32-FOR-VSCODE\\@XPACK-DEV-TOOLS\\OPENOCD\\0.11.0-5.1\\.CONTENT\\BIN\\OPENOCD.EXE",
"stm32-for-vscode.makePath": "C:\\USERS\\PIQUE_N\\APPDATA\\ROAMING\\CODE\\USER\\GLOBALSTORAGE\\BMD.STM32-FOR-VSCODE\\@XPACK-DEV-TOOLS\\WINDOWS-BUILD-TOOLS\\4.3.0-1.1\\.CONTENT\\BIN\\MAKE.EXE",
"stm32-for-vscode.armToolchainPath": "c:\\Users\\pique_n\\AppData\\Roaming\\Code\\User\\globalStorage\\bmd.stm32-for-vscode\\@xpack-dev-tools\\arm-none-eabi-gcc\\11.3.1-1.1.2\\.content\\bin"
"C_Cpp.default.compilerPath": "C:\\MinGW\\bin\\gcc.exe",
"files.associations": {
"eeprom_emul.h": "c"
}
}

50
.vscode/tasks.json vendored
View File

@ -1,50 +0,0 @@
{
"version": "2.0.0",
"tasks": [
{
"label": "Build STM",
"type": "process",
"command": "${command:stm32-for-vscode.build}",
"options": {
"cwd": "${workspaceRoot}"
},
"group": {
"kind": "build",
"isDefault": true
},
"problemMatcher": [
"$gcc"
]
},
{
"label": "Build Clean STM",
"type": "process",
"command": "${command:stm32-for-vscode.cleanBuild}",
"options": {
"cwd": "${workspaceRoot}"
},
"group": {
"kind": "build",
"isDefault": true
},
"problemMatcher": [
"$gcc"
]
},
{
"label": "Flash STM",
"type": "process",
"command": "${command:stm32-for-vscode.flash}",
"options": {
"cwd": "${workspaceRoot}"
},
"group": {
"kind": "build",
"isDefault": true
},
"problemMatcher": [
"$gcc"
]
}
]
}

36
Core/Application/INIT_Initialization.c
View File

@ -153,26 +153,40 @@ BOOL INIT_boCreateTask( VOID )
//-------------------------------------------------------------------------------------------------
PRIVATE VOID vTask( PVOID arg )
{
UNUSED( arg );
UNUSED( arg );
BOOL boOK = TRUE;
//boOK &= USFL_boInitializeModule();
boOK &= VARH_boInitializeModule();
BOOL boOK = TRUE;
boOK &= DIPO_boInitializeModule();
boOK &= ANPI_boInitializeModule();
uint32_t reset_flags = RCC->CSR;
boOK &= ERRH_boInitializeModule();
boOK &= USFL_boInitializeModule();
boOK &= VARH_boInitializeModule();
if (reset_flags & RCC_CSR_IWDGRSTF) {
// This was IWDG
ERRH_vSetError(HARDFAULT_ERROR_MASK | HARDFAULT_ERROR_IWDG);
}else if (reset_flags & RCC_CSR_SFTRSTF) {
// Software reset (NVIC_SystemReset or by debugger)
ERRH_vSetError(HARDFAULT_ERROR_MASK | HARDFAULT_ERROR_SWRST);
}
boOK &= DIPO_boInitializeModule();
boOK &= ANPI_boInitializeModule();
boOK &= ANPO_boInitializeModule();
boOK &= SPID_boInitializeModule();
boOK &= ADCD_boInitializeModule();
boOK &= SPID_boInitializeModule();
boOK &= ADCD_boInitializeModule();
boOK &= TEMP_boInitializeModule();
boOK &= CAND_boInitializeModule();
boOK &= PECO_boInitializeModule();
boOK &= MAIN_boInitializeModule();
boOK &= PECO_boInitializeModule();
boOK &= MAIN_boInitializeModule();
if( !boOK ){
osKernelLock(); // lock kernel to prevent task switch
PECO_Enable( FALSE );
while( 1 ){ // Toggle Error LED fast
DIPO_vToggleOutput( DIPO_eLED );
DELAY_MS( 100 );

139
Core/Application/MAIN_MainApplication.c
View File

@ -43,6 +43,8 @@
#include "../Drivers/ANPI_AnalogPortsIn.h"
#include "../Drivers/ANPO_AnalogPortsOut.h"
#include "../Drivers/ERRH_ErrorHandler.h"
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
@ -57,7 +59,7 @@
//=================================================================================================
/* Software Version */
#define SW_VERSION 1
#define SW_VERSION 13
#define MSG_QUEUE_SIZE 8
@ -74,7 +76,8 @@
#define COMMAND_ALARM 4
#define COMMAND_CLEAR_ERROR 5
#define COMMAND_GET_SW_VERSION 6
#define COMMAND_SET_REF_VOLTAGE 7
#define COMMAND_SAVE_VARIABLES 7
#define COMMAND_LOAD_VARIABLES 8
#define COMMAND_REBOOT 255
@ -199,20 +202,20 @@ LOCAL CONST osTimerAttr_t stWatchdogTimerAttribute =
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL MAIN_boInitializeModule( VOID )
BOOL MAIN_boInitializeModule( VOID )
{
BOOL boOK = TRUE;
boOK &= ( ( m_pstEventID = osEventFlagsNew( &stEventAttribute ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( ( m_pstThreadID = osThreadNew( vTask, NULL, &stTaskAttribute ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( ( m_pstCANRxMsgQueueID = osMessageQueueNew( MSG_QUEUE_SIZE, sizeof( CAND_Message ), &stCANRxMsgQueueAttribute ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( ( m_pstCANRxMsgQueueID = osMessageQueueNew( MSG_QUEUE_SIZE, sizeof( CAND_Message ), &stCANRxMsgQueueAttribute ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( m_pstUpdateTimer = osTimerNew( vEventCallback, osTimerPeriodic, (PVOID)EVENT_TIMER_UPDATE, &stTimerAttribute ) ) == NULL ? FALSE : TRUE;
boOK &= ( m_pstWatchdogTimer = osTimerNew( vEventCallback, osTimerPeriodic, (PVOID)EVENT_TIMER_UPDATE, &stWatchdogTimerAttribute ) ) == NULL ? FALSE : TRUE;
boOK &= ( m_pstWatchdogTimer = osTimerNew( vEventCallback, osTimerPeriodic, (PVOID)EVENT_WATCHDOG, &stWatchdogTimerAttribute ) ) == NULL ? FALSE : TRUE;
boOK &= (osTimerStart( m_pstUpdateTimer, 1000 ) == osOK ) ? TRUE : FALSE;
//boOK &= (osTimerStart( m_pstWatchdogTimer, WATCHDOG ) == osOK ) ? TRUE : FALSE;
boOK &= (osTimerStart( m_pstWatchdogTimer, WATCHDOG ) == osOK ) ? TRUE : FALSE;
CAND_vSetRxCallback( vMsgRxCallback );
CAND_vSetRxCallback( vMsgRxCallback );
return( boOK );
}
@ -243,77 +246,81 @@ PRIVATE VOID vTask( PVOID arg )
if( u32Flags & EVENT_NEW_MESSAGE ) { // New message from CAN
CAND_Message stMessage;
osMessageQueueGet( m_pstCANRxMsgQueueID, &stMessage, NULL, 0 ); // get message from queue
osMessageQueueGet( m_pstCANRxMsgQueueID, &stMessage, NULL, 0 ); // get message from queue
U8 u8Register = stMessage.au8Data[0];
U8 u8Type = stMessage.u8Type;
U8 u8Register = stMessage.au8Data[0];
U8 u8Type = stMessage.u8Type;
if( u8Type == MESSAGE_TYPE_READ ){ // Message type read
if( u8Type == MESSAGE_TYPE_READ ){ // Message type read
if( u8Register >= VARH_eNumberOfVariables ){ // check register
// send register not found
au8Buffer[0] = 0xFF;
CAND_boSendMessage( au8Buffer, 1, stMessage.boIsPrivate, stMessage.u8Type );
} else {
VARH_UVariable uVariable = VARH_uGetVariableData(u8Register); // get data
au8Buffer[0] = u8Register;
UTIL_vMemCopy(&uVariable, &au8Buffer[1], 4); // copy data in buffer
if( u8Register >= VARH_eNumberOfVariables ){ // check register
// send register not found
ERRH_vSetError(MAIN_ERROR_MASK | MAIN_ERROR_REG_NOT_FOUND);
CAND_boSendMessage( au8Buffer, 5, stMessage.boIsPrivate, stMessage.u8Type );
}
} else if( u8Type == MESSAGE_TYPE_WRITE ){ // Message type writeset
VARH_UVariable uData;
UTIL_vMemCopy(&stMessage.au8Data[1], &uData, 4);
au8Buffer[0] = 0xFF;
CAND_boSendMessage( au8Buffer, 1, stMessage.boIsPrivate, stMessage.u8Type );
} else {
VARH_UVariable uVariable = VARH_uGetVariableData(u8Register); // get data
au8Buffer[0] = u8Register;
UTIL_vMemCopy(&uVariable, &au8Buffer[1], 4); // copy data in buffer
VARH_vSetVariableData(u8Register, uData);
} else if( u8Type == MESSAGE_TYPE_COMMAND ){ // Message type command
CAND_boSendMessage( au8Buffer, 5, stMessage.boIsPrivate, stMessage.u8Type );
}
switch (u8Register)
{
case COMMAND_ON:
PECO_Enable( TRUE );
break;
} else if( u8Type == MESSAGE_TYPE_WRITE ){ // Message type write
VARH_UVariable uData;
UTIL_vMemCopy(&stMessage.au8Data[1], &uData, 4);
case COMMAND_OFF:
PECO_Enable( FALSE );
break;
case COMMAND_WATCHDOG:
osTimerStart( m_pstWatchdogTimer, WATCHDOG );
break;
case COMMAND_CLEAR_ERROR:
VARH_vSetVariableDataFromSystemU32( VARH_eError, 0x00000000 );
break;
case COMMAND_REBOOT:
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
break;
case COMMAND_GET_SW_VERSION:
au8Buffer[0] = COMMAND_GET_SW_VERSION;
au8Buffer[1] = SW_VERSION;
CAND_boSendMessage( au8Buffer, 2, stMessage.boIsPrivate, stMessage.u8Type );
break;
case COMMAND_SET_REF_VOLTAGE:
VARH_UVariable uData;
UTIL_vMemCopy(&stMessage.au8Data[1], &uData, 4);
ANPI_vSetRefVoltage(uData.flVal);
ANPO_boSetVoltage(uData.flVal);
break;
default:
break;
}
}
}
VARH_vSetVariableData(u8Register, uData);
} else if( u8Type == MESSAGE_TYPE_COMMAND ){ // Message type command
switch (u8Register)
{
case COMMAND_ON:
PECO_Enable( TRUE );
break;
case COMMAND_OFF:
PECO_Enable( FALSE );
break;
case COMMAND_WATCHDOG:
osTimerStart( m_pstWatchdogTimer, WATCHDOG );
break;
case COMMAND_CLEAR_ERROR:
ERRH_vClearError();
break;
case COMMAND_REBOOT:
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
break;
case COMMAND_GET_SW_VERSION:
au8Buffer[0] = COMMAND_GET_SW_VERSION;
au8Buffer[1] = SW_VERSION;
CAND_boSendMessage( au8Buffer, 2, stMessage.boIsPrivate, stMessage.u8Type );
break;
case COMMAND_SAVE_VARIABLES:
if(!VARH_vSaveVariablestoFlash()){
ERRH_vSetError(MAIN_ERROR_MASK | MAIN_ERROR_SAVE_FLASH);
}
break;
case COMMAND_LOAD_VARIABLES:
VARH_vLoadVariablesfromFlash();
break;
default:
ERRH_vSetError(MAIN_ERROR_MASK | MAIN_ERROR_CMD_NOT_FOUND);
break;
}
}
}
if( u32Flags & EVENT_TIMER_UPDATE )
{
{
DIPO_vToggleOutput( DIPO_eLED );
}
if( u32Flags & EVENT_WATCHDOG )
{
if( u32Flags & EVENT_WATCHDOG )
{
PECO_Enable( FALSE );
// TODO: WATCHDOG: what else?
// ERRH_vSetError(MAIN_ERROR_MASK | MAIN_ERROR_WATCHDOG);
}
}
@ -338,7 +345,7 @@ PRIVATE VOID vEventCallback( PVOID pvData )
//-------------------------------------------------------------------------------------------------
PRIVATE VOID vMsgRxCallback( CAND_Message stMessage )
{
osMessageQueuePut( m_pstCANRxMsgQueueID, &stMessage, 0, 0 );
osMessageQueuePut( m_pstCANRxMsgQueueID, &stMessage, 0, 0 );
osEventFlagsSet( m_pstEventID, EVENT_NEW_MESSAGE );
}

283
Core/Application/PECO_PeltierController.c
View File

@ -23,8 +23,6 @@
//
//=================================================================================================
//=================================================================================================
// Section: INCLUDES
// Description: List of required include files.
@ -32,9 +30,11 @@
#include "PECO_PeltierController.h"
//Application
// Application
#include "../Application/VARH_VariableHandler.h"
#include "ERRH_ErrorHandler.h"
// Driver
#include "ANPO_AnalogPortsOut.h"
#include "DIPO_DigitalPorts.h"
@ -45,50 +45,44 @@
// include STM32 drivers
#include "stm32l4xx_hal.h"
#include "cmsis_os2.h"
#include "cmsis_os2.h"
//=================================================================================================
// Section: DEFINITIONS
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
#define REFRESH 100 // Refresh rate in ms
#define REFRESH 200 // Refresh rate in ms
#define EVENT_TIMER_UPDATE ((U32)(1<<0))
#define EVENT_TIMER_UPDATE ((U32)(1 << 0))
#define EVENT_FLAGS_ALL ( EVENT_TIMER_UPDATE )
#define EVENT_FLAGS_ALL (EVENT_TIMER_UPDATE)
#define MAX_POWER_PELTIER 110 // safety for pid regulations
//=================================================================================================
// Section: MACROS
// Description: Definition of local macros (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: ENUMERATIONS
// Description: Definition of local enumerations (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: STRUCTURES
// Description: Definition of local Structures (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: LOCAL VARIABLES
// Description: Definition of local variables (visible by this module only).
//=================================================================================================
LOCAL osThreadId_t m_pstThreadID = NULL;
LOCAL osTimerId_t m_pstUpdateTimer = NULL;
LOCAL osEventFlagsId_t m_pstEventID = NULL;
LOCAL osThreadId_t m_pstThreadID = NULL;
LOCAL osTimerId_t m_pstUpdateTimer = NULL;
LOCAL osEventFlagsId_t m_pstEventID = NULL;
//=================================================================================================
// Section: LOCAL CONSTANTS
@ -96,50 +90,48 @@ LOCAL osEventFlagsId_t m_pstEventID = NULL;
//=================================================================================================
LOCAL CONST osThreadAttr_t stTaskAttribute =
{
"PECO_Thread", // name of the thread
osThreadDetached, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
NULL, // memory for stack
1024, // size of stack
osPriorityHigh, // initial thread priority (default: osPriorityNormal)
0, // TrustZone module identifier
0, // reserved (must be 0)
{
"PECO_Thread", // name of the thread
osThreadDetached, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
NULL, // memory for stack
1024, // size of stack
osPriorityHigh, // initial thread priority (default: osPriorityNormal)
0, // TrustZone module identifier
0, // reserved (must be 0)
};
LOCAL CONST osTimerAttr_t stTimerAttribute =
{
"PECO_UpdateTimer", // name of the timer
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
{
"PECO_UpdateTimer", // name of the timer
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
};
LOCAL CONST osEventFlagsAttr_t stEventAttribute =
{
"PECO_Event_Flags", // name of the event flags
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
{
"PECO_Event_Flags", // name of the event flags
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
};
//=================================================================================================
// Section: LOCAL FUNCTIONS (PROTOTYPES)
// Description: Definition of local functions (visible by this module only).
//=================================================================================================
PRIVATE VOID vTask( PVOID arg );
BOOL boSetPeltierVoltage( FLOAT Voltage );
PRIVATE VOID vEventCallback( PVOID pvData );
PRIVATE VOID vTask(PVOID arg);
BOOL boSetPeltierVoltage(FLOAT Voltage);
PRIVATE VOID vEventCallback(PVOID pvData);
//=================================================================================================
// Section: EXTERNAL FUNCTIONS
// Description: Definition of external (global) functions.
//=================================================================================================
//=================================================================================================
// Section: EXTERNAL VARIABLES
// Description: Definition of external (global) variables.
@ -159,19 +151,19 @@ extern IWDG_HandleTypeDef hiwdg;
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL PECO_boInitializeModule( VOID )
BOOL PECO_boInitializeModule(VOID)
{
BOOL boOK = TRUE;
boOK &= ( ( m_pstThreadID = osThreadNew( vTask, NULL, &stTaskAttribute ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( ( m_pstEventID = osEventFlagsNew( &stEventAttribute ) ) == NULL) ? FALSE : TRUE;
boOK &= ( m_pstUpdateTimer = osTimerNew( vEventCallback, osTimerPeriodic, (PVOID)EVENT_TIMER_UPDATE, &stTimerAttribute ) ) == NULL ? FALSE : TRUE;
boSetPeltierVoltage(0);
BOOL boOK = TRUE;
boOK &= (osTimerStart( m_pstUpdateTimer, REFRESH ) == osOK ) ? TRUE : FALSE;
boOK &= ((m_pstThreadID = osThreadNew(vTask, NULL, &stTaskAttribute)) == NULL) ? FALSE : TRUE;
boOK &= ((m_pstEventID = osEventFlagsNew(&stEventAttribute)) == NULL) ? FALSE : TRUE;
boOK &= (m_pstUpdateTimer = osTimerNew(vEventCallback, osTimerPeriodic, (PVOID)EVENT_TIMER_UPDATE, &stTimerAttribute)) == NULL ? FALSE : TRUE;
return( boOK );
boSetPeltierVoltage(0);
boOK &= (osTimerStart(m_pstUpdateTimer, REFRESH) == osOK) ? TRUE : FALSE;
return (boOK);
}
//-------------------------------------------------------------------------------------------------
@ -180,9 +172,10 @@ BOOL PECO_boInitializeModule( VOID )
// Parameters: BOOL boEnable
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID PECO_Enable( BOOL boEnable ){
DIPO_vSetState(DIPO_eEN, boEnable);
VARH_vSetVariableDataFromSystemU32( VARH_ePowerState, (U32)boEnable );
VOID PECO_Enable(BOOL boEnable)
{
DIPO_vSetState(DIPO_eEN, boEnable);
VARH_vSetVariableDataFromSystemU32(VARH_ePowerState, (U32)boEnable);
}
//-------------------------------------------------------------------------------------------------
@ -191,8 +184,9 @@ VOID PECO_Enable( BOOL boEnable ){
// Parameters: None
// Returns: BOOL boEnableOutput
//-------------------------------------------------------------------------------------------------
BOOL PECO_isEnabled( VOID ){
return (BOOL)VARH_u32GetVariableData( VARH_ePowerState );
BOOL PECO_isEnabled(VOID)
{
return (BOOL)VARH_u32GetVariableData(VARH_ePowerState);
}
//=================================================================================================
@ -206,88 +200,116 @@ BOOL PECO_isEnabled( VOID ){
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID vTask( PVOID arg )
VOID vTask(PVOID arg)
{
UNUSED( arg );
UNUSED(arg);
U32 u32Flags;
FLOAT last_error = 0;
FLOAT integral = 0;
FLOAT dT = REFRESH / 1000.0f; // 1s
while ( TRUE )
FLOAT error_prev = 0;
FLOAT Tc_prev = 0;
FLOAT i_prev = 0;
FLOAT d_prev = 0;
FLOAT tau = 0.4f;
FLOAT dT = REFRESH / 1000.0f; // 0.2s
while (TRUE)
{
u32Flags = osEventFlagsWait( m_pstEventID, EVENT_FLAGS_ALL, osFlagsWaitAny, osWaitForever );
u32Flags = osEventFlagsWait(m_pstEventID, EVENT_FLAGS_ALL, osFlagsWaitAny, osWaitForever);
if( u32Flags & EVENT_TIMER_UPDATE )
if (u32Flags & EVENT_TIMER_UPDATE)
{
HAL_IWDG_Refresh(&hiwdg);
if ( PECO_isEnabled() )
if (PECO_isEnabled())
{
if ( VARH_u32GetVariableData( VARH_eMode ) == PECO_eConstTemp )
if (VARH_u32GetVariableData(VARH_eMode) == PECO_eConstTemp)
{
// TODO: check the measurements, everything ok?
/** @todo check power good pin */
// PID Regelung
// TODO: check the measurements, everything ok?
FLOAT kp = VARH_flGetVariableData( VARH_ePID_kp );
FLOAT ki = VARH_flGetVariableData( VARH_ePID_ki );
FLOAT kd = VARH_flGetVariableData( VARH_ePID_kd );
FLOAT max = VARH_flGetVariableData( VARH_ePID_Max );
FLOAT min = VARH_flGetVariableData( VARH_ePID_Min );
FLOAT Tnow = VARH_flGetVariableData( VARH_eTemp_Module );
FLOAT Tset = VARH_flGetVariableData( VARH_ePID_Temp );
FLOAT power = VARH_flGetVariableData(VARH_ePeltier_P);
if(power > MAX_POWER_PELTIER){
PECO_Enable(FALSE);
ERRH_vSetError(PELTIER_ERROR_MASK | PELTIER_ERROR_MAX_POWER);
}
// -error
FLOAT error = Tnow - Tset;
// PID Regelung
// proportional term
FLOAT P = kp * error;
// integral term
integral += error * dT;
FLOAT I = ki * integral;
// derivative term
FLOAT D = kd * ( error - last_error ) / dT;
last_error = error;
// total
FLOAT output = P + I + D;
// limitter
if ( output > max ){
output = max;
integral = 0;
} else if ( output < min ){
output = min;
integral = 0;
FLOAT Kp = VARH_flGetVariableData(VARH_ePID_kp);
FLOAT Ki = VARH_flGetVariableData(VARH_ePID_ki);
FLOAT Kd = VARH_flGetVariableData(VARH_ePID_kd);
FLOAT Umax = VARH_flGetVariableData(VARH_ePID_Max);
FLOAT Umin = VARH_flGetVariableData(VARH_ePID_Min);
FLOAT Tc = VARH_flGetVariableData(VARH_eTemp_Module);
FLOAT Ts = VARH_flGetVariableData(VARH_ePID_Temp);
// calculate error
FLOAT error = Tc - Ts;
// proportional term
FLOAT P = Kp * error;
// integral term
FLOAT I = i_prev + 0.5f * Ki * dT * (error + error_prev);
// compute integral limits (anti-windup via dynamic integrator clamping)
FLOAT limMinInt = 0.0f;
FLOAT limMaxInt = 0.0f;
if(Umax > P) limMaxInt = Umax - P;
if(Umin < P) limMinInt = Umin - P;
// clamp integrator
if(I > limMaxInt) I = limMaxInt;
else if (I < limMinInt) I = limMinInt;
// derivative term
FLOAT D = -(2.0f * Kd * (Tc - Tc_prev) /* Note: derivative on measurement, therefore minus sign in front of equation! */
+ (2.0f * tau - dT) * d_prev)
/ (2.0f * tau + dT);
// total
FLOAT Uout = P + I + D;
// limitter
if (Uout > Umax) Uout = Umax;
else if (Uout < Umin) Uout = Umin;
Tc_prev = Tc;
error_prev = error;
d_prev = D;
i_prev = I;
if(!boSetPeltierVoltage(Uout)) ERRH_vSetError(PELTIER_ERROR_MASK | PELTIER_ERROR_SETVOLTAGE_PID); // set the output
}
boSetPeltierVoltage( output ); // set the output
} else if ( VARH_u32GetVariableData( VARH_eMode ) == PECO_eConst_Voltage )
else if (VARH_u32GetVariableData(VARH_eMode) == PECO_eConst_Voltage)
{
boSetPeltierVoltage( VARH_flGetVariableData( VARH_eControlVoltage ) ); // set the output
last_error = 0;
integral = 0;
if(!boSetPeltierVoltage(VARH_flGetVariableData(VARH_eControlVoltage))) ERRH_vSetError(PELTIER_ERROR_MASK | PELTIER_ERROR_SETVOLTAGE); // set the output
// reset PID Vars
error_prev = 0;
Tc_prev = 0;
i_prev = 0;
d_prev = 0;
}
} else {
last_error = 0;
integral = 0;
}
}
else
{
// reset PID vars
error_prev = 0;
Tc_prev = 0;
i_prev = 0;
d_prev = 0;
}
}
}
}
}
//-------------------------------------------------------------------------------------------------
@ -296,15 +318,18 @@ VOID vTask( PVOID arg )
// Parameters: S8 Voltage (12V - -3V)
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL boSetPeltierVoltage( FLOAT Voltage ){
BOOL boOK = TRUE;
BOOL boSetPeltierVoltage(FLOAT Voltage)
{
BOOL boOK = TRUE;
if( Voltage > 12 ) Voltage = 12;
if( Voltage < -3 ) Voltage = -3;
boOK &= ANPO_boSetVoltage( ( ( (FLOAT)Voltage ) + 20.088) / 34.103 );
if (Voltage > 12)
Voltage = 12;
if (Voltage < -5)
Voltage = -5;
return( boOK );
boOK &= ANPO_boSetVoltage(Voltage);
return (boOK);
}
//-------------------------------------------------------------------------------------------------
@ -313,9 +338,7 @@ BOOL boSetPeltierVoltage( FLOAT Voltage ){
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
PRIVATE VOID vEventCallback( PVOID pvData )
PRIVATE VOID vEventCallback(PVOID pvData)
{
osEventFlagsSet( m_pstEventID, (U32)pvData );
osEventFlagsSet(m_pstEventID, (U32)pvData);
}

121
Core/Application/VARH_VariableHandler.c
View File

@ -30,6 +30,12 @@
#include "VARH_VariableHandler.h"
#include "USFL_UserFlash.h"
#include "ERRH_ErrorHandler.h"
#include "CAND_CanDriver.h"
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
@ -69,34 +75,40 @@ LOCAL osMutexId_t m_pstMutexID = NULL;
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
/*
If you set the VARH_FLAGINFO_FLASH, don't forget to update the Number of variables saved into Flash!!!
Middlewares\ST\EEPROM_Emul\Core\eeprom_emul_conf.h
*/
LOCAL CONST VARH_StVarInfo m_astVarInfo[VARH_eNumberOfVariables] =
{
{ VARH_FLAGINFO_NONE, (VARH_UVariable)(U32)1, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1}, // VARH_eMode
{ VARH_FLAGINFO_NONE, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1}, // VARH_eMode
{ VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-2.0f, (VARH_UVariable)12.0f}, // VARH_eControlVoltage
{ VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-5.0f, (VARH_UVariable)12.0f}, // VARH_eControlVoltage
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kp
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_ki
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kd
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.4f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kp
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.03f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_ki
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)3.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kd
{ VARH_FLAGINFO_FLOAT, (VARH_UVariable)23.0f, (VARH_UVariable)-40.0f, (VARH_UVariable)50.0f }, // VARH_ePID_Temp
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)10.0f, (VARH_UVariable)0.0f, (VARH_UVariable)12.0f }, // VARH_ePID_Max
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)-2.0f, (VARH_UVariable)-2.0f, (VARH_UVariable)0.0f }, // VARH_ePID_Min
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)-2.0f, (VARH_UVariable)-5.0f, (VARH_UVariable)0.0f }, // VARH_ePID_Min
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-60.0f, (VARH_UVariable)100.0f }, // VARH_eTemp_Water
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-60.0f, (VARH_UVariable)100.0f }, // VARH_eTemp_Module
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)70.0f }, // VARH_eTemp_Diff
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)50.0f }, // VARH_eTemp_Water
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)50.0f }, // VARH_eTemp_Module
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-1000.0f, (VARH_UVariable)1000.0f }, // VARH_eTemp_Diff - not used anymore
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-5.0f, (VARH_UVariable)14.0f }, // VARH_ePeltier_U
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-10.0f, (VARH_UVariable)10.0f }, // VARH_ePeltier_I
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)5.0f }, // VARH_ePeltier_R
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)150.0f }, // VARH_ePeltier_P
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-8.0f, (VARH_UVariable)15.0f }, // VARH_ePeltier_U
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-15.0f, (VARH_UVariable)15.0f }, // VARH_ePeltier_I
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePeltier_R
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)160.0f }, // VARH_ePeltier_P
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)20.0f, (VARH_UVariable)30.0f }, // VARH_eSupply_U
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)5.0f }, // VARH_eSupply_I
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)150.0f }, // VARH_eSupply_P
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)15.0f }, // VARH_eSupply_I
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)160.0f }, // VARH_eSupply_P
{ VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1 }, // VARH_ePowerState
{ VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0xFFFFFFFF }, // VARH_eError
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)3.3f, (VARH_UVariable)(U32)2.0f, (VARH_UVariable)4.0f }, // VARH_eRef_U
};
LOCAL CONST osMutexAttr_t m_stMutexAttr =
@ -145,7 +157,7 @@ BOOL VARH_boInitializeModule( VOID )
{
BOOL boOK = TRUE;
boOK &= ( ( m_pstMutexID = osMutexNew( &m_stMutexAttr ) ) == NULL ) ? FALSE : TRUE;
boOK &= ( ( m_pstMutexID = osMutexNew( &m_stMutexAttr ) ) == NULL ) ? FALSE : TRUE;
VARH_vSetAllVariablesToInitData();
@ -164,11 +176,14 @@ VOID VARH_vSetVariableData( U8 u8Variable, VARH_UVariable uData )
// check parameters
if( m_astVarInfo[u8Variable].u8Flags & VARH_FLAGINFO_READONLY )
{
return;
ERRH_vSetError(VARH_ERROR_MASK | VARH_ERROR_READONLY | (u8Variable << 8));
return;
}
osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex
if( boCheckRange( u8Variable, uData ) ) { m_auVariable[u8Variable].uData = uData; } // store new value
if( boCheckRange( u8Variable, uData ) ) {
m_auVariable[u8Variable].uData = uData; // store new value
} else ERRH_vSetError(VARH_ERROR_MASK | VARH_ERROR_OUTOFRANGE | (u8Variable << 8));
osMutexRelease( m_pstMutexID ); // release mutex
}
@ -220,12 +235,19 @@ VOID VARH_vSetVariableDataFloat( U8 u8Variable, FLOAT flData )
VOID VARH_vSetVariableDataFromSystem( U8 u8Variable, VARH_UVariable uData )
{
osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex
if( !boCheckRange( u8Variable, uData ) )
{
m_auVariable[u8Variable].u8Flags |= VARH_FLAG_OUTOFRANGE; // check the value
}
m_auVariable[u8Variable].uData = uData; // store new value
osMutexRelease( m_pstMutexID ); // release mutex
if( !(u8Variable == VARH_eTemp_Water && CAND_u8GetBoardId() != 0x08) ){ // lid sensor goes outside of range
if( !boCheckRange( u8Variable, uData ) )
{
m_auVariable[u8Variable].u8Flags |= VARH_FLAG_OUTOFRANGE; // check the value
ERRH_vSetError(VARH_ERROR_MASK | VARH_ERROR_OUTOFRANGE_INT | (u8Variable << 8));
}
}
m_auVariable[u8Variable].uData = uData; // store new value
osMutexRelease( m_pstMutexID ); // release mutex
}
//-------------------------------------------------------------------------------------------------
@ -353,6 +375,57 @@ VOID VARH_vSetAllVariablesToInitData( VOID )
}
}
//-------------------------------------------------------------------------------------------------
// Function: VARH_vSaveVariablestoFlash
// Description: Saves all Variables with Flag VARH_FLAGINFO_FLASH to Flash
// Parameters: None
// Returns: TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL VARH_vSaveVariablestoFlash( VOID )
{
BOOL boOK = TRUE;
boOK &= USFL_vUnlock();
for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ )
{
if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){
boOK &= USFL_boSetVariable(u8Var, VARH_uGetVariableData(u8Var));
}
}
boOK &= USFL_vLock();
return boOK;
}
//-------------------------------------------------------------------------------------------------
// Function: VARH_vSaveVariablestoFlash
// Description: Saves all Variables with Flag VARH_FLAGINFO_FLASH to Flash
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID VARH_vLoadVariablesfromFlash( VOID )
{
BOOL boOK = TRUE;
for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ )
{
if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){
VARH_UVariable uData;
boOK &= USFL_boGetVariable(u8Var, &uData);
if( boOK ) VARH_vSetVariableDataFromSystem(u8Var, uData);
}
}
if( !boOK ){
ERRH_vSetError(VARH_ERROR_MASK | VARH_ERROR_LOAD_FLASH);
for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ )
{
if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){
VARH_vSetVariableToInitData( u8Var );
}
}
}
}
//=================================================================================================
// Section: LOCAL FUNCTIONS
// Descriptionn: Definition (implementation) of local functions.

4
Core/Application/VARH_VariableHandler.h
View File

@ -91,6 +91,7 @@ typedef enum
VARH_ePowerState,
VARH_eError,
VARH_eRef_U,
VARH_eNumberOfVariables, // Must be last entry
} VARH_EnVariables;
@ -167,6 +168,9 @@ U8 VARH_uGetVariableFlags( U8 u8Variable );
VOID VARH_vSetVariableToInitData( U8 u8Variable );
VOID VARH_vSetAllVariablesToInitData( VOID );
BOOL VARH_vSaveVariablestoFlash( VOID );
VOID VARH_vLoadVariablesfromFlash( VOID );
#ifdef __cplusplus
}
#endif

12
Core/Drivers/ADCD_AdcDriver.c
View File

@ -97,7 +97,6 @@
EVENT_DAC_START | EVENT_DAC_STOP | EVENT_ADC_DATA_READY | \
EVENT_RESET_DATA_COUNTER )
//=================================================================================================
// Section: MACROS
// Description: Definition of local macros (visible by this module only).
@ -195,19 +194,16 @@ BOOL ADCD_boInitializeModule( VOID )
osMutexAcquire( m_pstMutexID, osWaitForever );
// Conifg ADC Cold
// Conifg ADC Module
DIPO_vSetOutput( DIPO_eCS_Module );
boOK &= boWriteReg( REG_CONFIG, (U16) CONFIG | CONFIG_FAULTSTATCLEAR, FALSE );
DIPO_vResetOutput( DIPO_eCS_Module );
// Config ADC Hot
// Config ADC Water
DIPO_vSetOutput( DIPO_eCS_Water );
boOK &= boWriteReg( REG_CONFIG, (U16) CONFIG | CONFIG_FAULTSTATCLEAR, FALSE );
DIPO_vResetOutput( DIPO_eCS_Water );
/** @todo read back configuration */
osMutexRelease( m_pstMutexID );
return( boOK );
@ -250,7 +246,7 @@ BOOL ADCD_boReadData( ADCD_EnTemps eChannel, PU8 pu8Error, PU16 pu16Data )
return FALSE;
}
if( ( u16Data & 0x0001 ) == 0x0001 )
if( ( u16Data & 0x0001 ) == 0x0001 ) // error
{
osMutexAcquire( m_pstMutexID, osWaitForever );
@ -265,6 +261,8 @@ BOOL ADCD_boReadData( ADCD_EnTemps eChannel, PU8 pu8Error, PU16 pu16Data )
osMutexRelease( m_pstMutexID );
*pu8Error &= ADCD_FAULT_MASK; // Mask the don't care bits
*pu8Error |= ADCD_STATUS_DATA_ERROR;
return FALSE;

1
Core/Drivers/ADCD_AdcDriver.h
View File

@ -47,6 +47,7 @@ extern "C" {
#define ADCD_FAULT_REFINHIGH 0x10
#define ADCD_FAULT_RTDINLOW 0x08
#define ADCD_FAULT_OVUV 0x04
#define ADCD_FAULT_MASK 0xFC
//=================================================================================================
// Section: MACROS

111
Core/Drivers/ANPI_AnalogPortsIn.c
View File

@ -36,6 +36,8 @@
// Drivers
#include "PECO_PeltierController.h"
#include "ERRH_ErrorHandler.h"
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
@ -43,6 +45,7 @@
#include "stm32l4xx_hal.h"
#include "cmsis_os2.h"
#include <math.h>
//=================================================================================================
// Section: DEFINITIONS
@ -52,8 +55,6 @@
#define ADC_RES (4096) // ADC resolution: 12 bits
#define NR_OF_ADCS ANPI_eInNumberOfInputs // number of internal adc channels
#define INT_ADC_REF (3.3f)// int. reference voltage for conversion
#define BUFFER_SIZE NR_OF_ADCS * 2
#define BUFFER_HALF_SIZE NR_OF_ADCS
@ -65,6 +66,8 @@
#define OVERSAMPLING_DIVISOR 16.0f // calculated with parameters from hardware oversampling
// 6 bits(64x) - 2 bit shift = 4bit -> 16x
#define ALMOST_ZERO 0.1
//=================================================================================================
// Section: MACROS
// Description: Definition of local macros (visible by this module only).
@ -95,7 +98,7 @@ LOCAL osThreadId_t m_pstThreadID = NULL;
LOCAL osEventFlagsId_t m_pstEventID = NULL;
LOCAL osMutexId_t m_pstMutexID = NULL;
LOCAL FLOAT flRefVoltage = INT_ADC_REF;
LOCAL FLOAT aflValues[ANPI_eInNumberOfInputs]; // values
//=================================================================================================
// Section: LOCAL CONSTANTS
@ -107,18 +110,26 @@ LOCAL FLOAT flRefVoltage = INT_ADC_REF;
LOCAL CONST FLOAT m_aflConversionFactor[ANPI_eInNumberOfInputs] =
{
10, // 01 ANPI_eSupplyVoltage24V
5, // 02 ANPI_eSupplyCurrent24V
10, // 03 ANPI_eOutputVoltage
5, // 04 ANPI_eOutputCurrent
5, // 02 ANPI_eSupplyCurrent24V
10, // 03 ANPI_eOutputVoltage
5, // 04 ANPI_eOutputCurrent
};
// Order must fit enumeration "ANPI_EnAnalogInput"
LOCAL CONST FLOAT m_aflOffset[ANPI_eInNumberOfInputs] =
{
0.0f, // 01 ANPI_eSupplyVoltage24V
8.25f, // 02 ANPI_eSupplyCurrent24V
14.85f, // 03 ANPI_eOutputVoltage
8.25f, // 04 ANPI_eOutputCurrent
0.0f, // 01 ANPI_eSupplyVoltage24V
8.25f, // 02 ANPI_eSupplyCurrent24V
14.85f, // 03 ANPI_eOutputVoltage
8.25f, // 04 ANPI_eOutputCurrent
};
LOCAL CONST BOOL m_aboNegativeValuesAllowed[ANPI_eInNumberOfInputs] =
{
FALSE, // 01 ANPI_eSupplyVoltage24V
FALSE, // 02 ANPI_eSupplyCurrent24V
TRUE, // 03 ANPI_eOutputVoltage
TRUE, // 04 ANPI_eOutputCurrent
};
// inputs are connected to the following ADCs
@ -200,17 +211,6 @@ BOOL ANPI_boInitializeModule( VOID )
return( boOK );
}
//-------------------------------------------------------------------------------------------------
// Function: ANPI_vSetRefVoltage
// Description: Sets the Reference Voltage for calculating the Voltage
// Parameters: FLOAT flVoltage -> The Ref Voltage measured with an DMM for example
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID ANPI_vSetRefVoltage( FLOAT flVoltage )
{
flRefVoltage = flVoltage;
}
//-------------------------------------------------------------------------------------------------
// Function: ANPI_vTask
// Description: ANPI_vTask
@ -223,7 +223,6 @@ VOID vTask( PVOID arg )
U16 u16Offset;
FLOAT flUadc;
U32 au32ADCRawData[ANPI_eInNumberOfInputs];
FLOAT aflValues[ANPI_eInNumberOfInputs]; // values
osDelay( 1 ); // Wait 1ms to have a Valid Value
@ -244,6 +243,8 @@ VOID vTask( PVOID arg )
for( U16 u16Cnt = 0; u16Cnt < BUFFER_HALF_SIZE; u16Cnt++ )
au32ADCRawData[ u16Cnt ] = m_au16ADCDataBuffer[u16Cnt + u16Offset];
FLOAT flRefVoltage = VARH_flGetVariableData(VARH_eRef_U);
// multiply conversion factor and add the offset
for( U16 u16Cnt = 0; u16Cnt < ANPI_eInNumberOfInputs; u16Cnt++ )
{
@ -251,10 +252,29 @@ VOID vTask( PVOID arg )
aflValues[u16Cnt] = flUadc * m_aflConversionFactor[u16Cnt] - m_aflOffset[u16Cnt];
}
// Filter
for( U16 u16Cnt = 0; u16Cnt < ANPI_eInNumberOfInputs; u16Cnt++ )
{
if ( -ALMOST_ZERO <= aflValues[u16Cnt] && aflValues[u16Cnt] < ALMOST_ZERO)
aflValues[u16Cnt] = 0.0f;
}
for( U16 u16Cnt = 0; u16Cnt < ANPI_eInNumberOfInputs; u16Cnt++ )
{
if( ! m_aboNegativeValuesAllowed[u16Cnt] ){
if( aflValues[u16Cnt] < 0.0f) aflValues[u16Cnt] = 0.0f;
}
}
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_U, aflValues[ANPI_eOutputVoltage] );
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_I, aflValues[ANPI_eOutputCurrent] );
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, aflValues[ANPI_eOutputVoltage] / aflValues[ANPI_eOutputCurrent] );
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, aflValues[ANPI_eOutputVoltage] * aflValues[ANPI_eOutputCurrent] );
if ( aflValues[ANPI_eOutputCurrent] == 0.0f ){
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, 0.0f );
} else {
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, fabs( aflValues[ANPI_eOutputVoltage] / aflValues[ANPI_eOutputCurrent]) );
}
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_P, aflValues[ANPI_eOutputVoltage] * aflValues[ANPI_eOutputCurrent] );
VARH_vSetVariableDataFromSystemFloat( VARH_eSupply_U, aflValues[ANPI_eSupplyVoltage24V] );
VARH_vSetVariableDataFromSystemFloat( VARH_eSupply_I, aflValues[ANPI_eSupplyCurrent24V] );
@ -275,6 +295,21 @@ void HAL_ADC_ConvCpltCallback( ADC_HandleTypeDef* hadc )
osEventFlagsSet( m_pstEventID, ANPI_ADC_FULL_COMPLETE );
}
//-------------------------------------------------------------------------------------------------
// Function: HAL_ADC_ConvCpltCallback
// Description: Handles the ADC interrupts
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
FLOAT ANPI_GetVoltage( ANPI_EnAnalogInput enVoltage )
{
osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex
FLOAT flVoltage = aflValues[enVoltage];
osMutexRelease( m_pstMutexID ); // release mutex
return flVoltage;
}
//-------------------------------------------------------------------------------------------------
// Function: HAL_ADC_ConvHalfCpltCallback
// Description: Handles the ADC interrupts
@ -299,30 +334,12 @@ void HAL_ADC_ConvHalfCpltCallback( ADC_HandleTypeDef* hadc )
//-------------------------------------------------------------------------------------------------
void HAL_ADC_ErrorCallback( ADC_HandleTypeDef* hadc )
{
// TODO: Error Handling
if( hadc->ErrorCode == HAL_ADC_ERROR_NONE )
{
if( hadc->ErrorCode == HAL_ADC_ERROR_NONE ){
ERRH_vSetError(AI_DMA_ERROR_MASK | hadc->DMA_Handle->ErrorCode);
} else {
ERRH_vSetError(AI_ERROR_MASK | hadc->ErrorCode);
}
}
if( hadc->ErrorCode == HAL_ADC_ERROR_INTERNAL )
{
}
if( hadc->ErrorCode == HAL_ADC_ERROR_OVR )
{
}
if( hadc->ErrorCode == HAL_ADC_ERROR_DMA )
{
}
if( hadc->DMA_Handle->ErrorCode & HAL_DMA_ERROR_TE )
{
}
}

2
Core/Drivers/ANPI_AnalogPortsIn.h
View File

@ -94,7 +94,7 @@ typedef enum
//=================================================================================================
BOOL ANPI_boInitializeModule( VOID );
VOID ANPI_vSetRefVoltage( FLOAT flVoltage );
FLOAT ANPI_GetVoltage( ANPI_EnAnalogInput enVoltage );
#ifdef __cplusplus
}

199
Core/Drivers/ANPO_AnalogPortsOut.c
View File

@ -23,14 +23,16 @@
//
//=================================================================================================
//=================================================================================================
// Section: INCLUDES
// Description: List of required include files.
//=================================================================================================
#include "ANPO_AnalogPortsOut.h"
#include "ANPI_AnalogPortsIn.h"
#include "VARH_VariableHandler.h"
#include "DIPO_DigitalPorts.h"
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
@ -38,65 +40,99 @@
// include STM32 drivers
#include "stm32l4xx_hal.h"
#include "cmsis_os2.h"
#include "cmsis_os2.h"
//=================================================================================================
// Section: DEFINITIONS
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
#define INT_DAC_REF (3.3f)// int. reference voltage for conversion
#define REFRESH 50 // Refresh rate in ms
#define EVENT_TIMER_UPDATE ((U32)(1 << 0))
#define EVENT_FLAGS_ALL (EVENT_TIMER_UPDATE)
#define OFFSET 20.088
#define FACTOR 34.103448
//=================================================================================================
// Section: MACROS
// Description: Definition of local macros (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: ENUMERATIONS
// Description: Definition of local enumerations (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: STRUCTURES
// Description: Definition of local Structures (visible by this module only).
//=================================================================================================
//=================================================================================================
// Section: LOCAL VARIABLES
// Description: Definition of local variables (visible by this module only).
//=================================================================================================
LOCAL FLOAT flRefVoltage = INT_DAC_REF;
LOCAL osThreadId_t m_pstThreadID = NULL;
LOCAL osTimerId_t m_pstUpdateTimer = NULL;
LOCAL osEventFlagsId_t m_pstEventID = NULL;
LOCAL FLOAT flVoltageActual = 0.0f;
LOCAL FLOAT flVoltageSet = 0.0f;
//=================================================================================================
// Section: LOCAL CONSTANTS
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
LOCAL CONST osThreadAttr_t stTaskAttribute =
{
"ANPO_Thread", // name of the thread
osThreadDetached, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
NULL, // memory for stack
1024, // size of stack
osPriorityNormal, // initial thread priority (default: osPriorityNormal)
0, // TrustZone module identifier
0, // reserved (must be 0)
};
LOCAL CONST osTimerAttr_t stTimerAttribute =
{
"ANPO_UpdateTimer", // name of the timer
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
};
LOCAL CONST osEventFlagsAttr_t stEventAttribute =
{
"ANPO_Event_Flags", // name of the event flags
0, // attribute bits
NULL, // memory for control block
0, // size of provided memory for control block
};
//=================================================================================================
// Section: LOCAL FUNCTIONS (PROTOTYPES)
// Description: Definition of local functions (visible by this module only).
//=================================================================================================
U32 u32ConvertVoltagetoRaw( FLOAT flVoltage );
U32 u32ConvertVoltagetoRaw(FLOAT flVoltage);
BOOL boUpdateVoltage(VOID);
PRIVATE VOID vTask(PVOID arg);
PRIVATE VOID vEventCallback(PVOID pvData);
//=================================================================================================
// Section: EXTERNAL FUNCTIONS
// Description: Definition of external (global) functions.
//=================================================================================================
//=================================================================================================
// Section: EXTERNAL VARIABLES
// Description: Definition of external (global) variables.
@ -116,24 +152,19 @@ extern DAC_HandleTypeDef hdac1;
// Returns: Boolean, TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL ANPO_boInitializeModule( VOID )
BOOL ANPO_boInitializeModule(VOID)
{
BOOL boOK = TRUE;
BOOL boOK = TRUE;
boOK &= HAL_DAC_Start( &hdac1, DAC_CHANNEL_1 ) == HAL_OK ? TRUE : FALSE;
boOK &= ((m_pstThreadID = osThreadNew(vTask, NULL, &stTaskAttribute)) == NULL) ? FALSE : TRUE;
boOK &= ((m_pstEventID = osEventFlagsNew(&stEventAttribute)) == NULL) ? FALSE : TRUE;
boOK &= (m_pstUpdateTimer = osTimerNew(vEventCallback, osTimerPeriodic, (PVOID)EVENT_TIMER_UPDATE, &stTimerAttribute)) == NULL ? FALSE : TRUE;
return( boOK );
}
boOK &= HAL_DAC_Start(&hdac1, DAC_CHANNEL_1) == HAL_OK ? TRUE : FALSE;
//-------------------------------------------------------------------------------------------------
// Function: ANPO_vSetRefVoltage
// Description: Sets the Reference Voltage for calculating the Voltage
// Parameters: FLOAT flVoltage -> The Ref Voltage measured with an DMM for example
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID ANPO_vSetRefVoltage( FLOAT flVoltage )
{
flRefVoltage = flVoltage;
boOK &= (osTimerStart(m_pstUpdateTimer, REFRESH) == osOK) ? TRUE : FALSE;
return (boOK);
}
//=================================================================================================
@ -141,20 +172,82 @@ VOID ANPO_vSetRefVoltage( FLOAT flVoltage )
// Descriptionn: Definition (implementation) of local functions.
//=================================================================================================
//-------------------------------------------------------------------------------------------------
// Function: vTask
// Description: Task
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
VOID vTask(PVOID arg)
{
UNUSED(arg);
U32 u32EventFlags = 0;
while (TRUE)
{
u32EventFlags = osEventFlagsWait(m_pstEventID, EVENT_FLAGS_ALL, osFlagsWaitAny, osWaitForever);
if (u32EventFlags & EVENT_TIMER_UPDATE)
{
boUpdateVoltage();
// BOOL boPowerGood = DIPO_boGetInput(DIPO_ePG);
/** @todo check power good pin */
}
}
}
//-------------------------------------------------------------------------------------------------
// Function: ANPO_boSetVoltage
// Description: Sets the DAC Output to a specific Voltage
// Description: Sets the Variable to a specific Voltage
// Parameters: FLOAT Voltage
// Returns: Boolean, TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL ANPO_boSetVoltage( FLOAT flVoltage ){
BOOL boOK = TRUE;
U32 u32RawData = u32ConvertVoltagetoRaw( flVoltage );
boOK &= HAL_DAC_SetValue( &hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, u32RawData );
return( boOK );
BOOL ANPO_boSetVoltage(FLOAT flVoltage)
{
BOOL boOK = TRUE;
flVoltageSet = flVoltage;
boOK &= osEventFlagsSet(m_pstEventID, EVENT_TIMER_UPDATE) == osOK ? TRUE : FALSE;
return (boOK);
}
//-------------------------------------------------------------------------------------------------
// Function: boUpdateVoltage
// Description: Updates the Voltage of the DAC Output with a ramp
// Parameters: FLOAT Voltage
// Returns: Boolean, TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL boUpdateVoltage(VOID)
{
BOOL boOK = TRUE;
if (flVoltageActual < flVoltageSet)
{
flVoltageActual += 0.1;
if (flVoltageActual > flVoltageSet)
{
flVoltageActual = flVoltageSet;
}
}
else if (flVoltageActual > flVoltageSet)
{
flVoltageActual -= 0.1;
if (flVoltageActual < flVoltageSet)
{
flVoltageActual = flVoltageSet;
}
}
U32 u32RawData = u32ConvertVoltagetoRaw(flVoltageActual);
boOK &= HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, u32RawData) == HAL_OK ? TRUE : FALSE;
return (boOK);
}
//-------------------------------------------------------------------------------------------------
@ -163,14 +256,24 @@ BOOL ANPO_boSetVoltage( FLOAT flVoltage ){
// Parameters: FLOAT Voltage
// Returns: U32
//-------------------------------------------------------------------------------------------------
U32 u32ConvertVoltagetoRaw( FLOAT flVoltage ){
U32 RawData;
RawData = flVoltage * 4095 / flRefVoltage;
return RawData;
U32 u32ConvertVoltagetoRaw(FLOAT flVoltage)
{
U32 RawData;
FLOAT flTempVoltage = (((FLOAT)flVoltage) + OFFSET) / FACTOR;
RawData = flTempVoltage * 4095 / VARH_flGetVariableData(VARH_eRef_U);
return RawData;
}
//-------------------------------------------------------------------------------------------------
// Function: vEventCallback
// Description: Callback for events
// Parameters: None
// Returns: None
//-------------------------------------------------------------------------------------------------
PRIVATE VOID vEventCallback(PVOID pvData)
{
osEventFlagsSet(m_pstEventID, (U32)pvData);
}

1
Core/Drivers/ANPO_AnalogPortsOut.h
View File

@ -88,7 +88,6 @@ typedef enum
BOOL ANPO_boInitializeModule( VOID );
BOOL ANPO_boSetVoltage( FLOAT flVoltage );
VOID ANPO_vSetRefVoltage( FLOAT flVoltage );
#ifdef __cplusplus
}

4
Core/Drivers/CAND_CanDriver.c
View File

@ -38,6 +38,8 @@
// Driver
#include "DIPO_DigitalPorts.h"
#include "ERRH_ErrorHandler.h"
// include STM32 drivers
#include "stm32l4xx_hal.h"
@ -259,7 +261,7 @@ void HAL_CAN_RxFifo0MsgPendingCallback( CAN_HandleTypeDef *hcan ){
//-------------------------------------------------------------------------------------------------
void HAL_CAN_ErrorCallback( CAN_HandleTypeDef *hcan ){
U32 u32Error = hcan->ErrorCode;
// TODO: Can Error Handling
ERRH_vSetError(CAN_ERROR_MASK | u32Error);
}

23
Core/Drivers/ERRH_ErrorHandler.c
View File

@ -31,6 +31,7 @@
//=================================================================================================
#include "ERRH_ErrorHandler.h"
#include "VARH_VariableHandler.h"
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
@ -106,12 +107,32 @@ BOOL ERRH_boInitializeModule( VOID )
{
BOOL boOK = TRUE;
// nothing to do yet in init
return( boOK );
}
VOID ERRH_vClearError( VOID )
{
VARH_vSetVariableDataFromSystemU32( VARH_eError, NO_ERROR );
}
VOID ERRH_vSetError( U32 u32Error )
{
VARH_vSetVariableDataFromSystemU32( VARH_eError, u32Error );
}
U32 ERRH_u32GetError( VOID )
{
return( VARH_u32GetVariableData( VARH_eError ) );
}
//=================================================================================================
// Section: LOCAL FUNCTIONS

125
Core/Drivers/ERRH_ErrorHandler.h
View File

@ -42,6 +42,128 @@ extern "C" {
// Description: Definition of global constants (visible by all modules).
//=================================================================================================
// Error Definition
#define NO_ERROR 0x00000000
// CAN Errors
#define CAN_ERROR_MASK 0x01000000
// #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
// #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
// #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
// #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
// #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
// #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
// #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
// #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
// #define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
// #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
// #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
// #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
// #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
// #define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
// #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
// #define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
// #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
// #define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
// #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
// #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
// #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
// #define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
// #define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
// #define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
// SPI Errors
#define SPI_ERROR_MASK 0x02000000
// #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
// #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
// #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
// #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
// #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
// #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
// #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
// #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
// Analog In Errors
#define AI_ERROR_MASK 0x03000000
// #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
// #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
// enable/disable, erroneous state, ...) */
// #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
// #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
// #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
#define AI_DMA_ERROR_MASK 0x04000000
// #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
// #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
// #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
// #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
// #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
// #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
// #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
// Temperature Errors
#define TEMP_ERROR_MASK 0x05000000
#define TEMP_ERROR_SENSORM_MASK 0x00100000
#define TEMP_ERROR_SENSORW_MASK 0x00200000
#define TEMP_ERROR_SPI_FAILURE 0x00010000
#define TEMP_ERROR_GENERAL_FAILURE 0x00020000
#define TEMP_ERROR_SENSOR_FAILURE 0x00040000
// #define ADCD_FAULT_HIGHTHRESH 0x80
// #define ADCD_FAULT_LOWTHRESH 0x40
// #define ADCD_FAULT_REFINLOW 0x20
// #define ADCD_FAULT_REFINHIGH 0x10
// #define ADCD_FAULT_RTDINLOW 0x08
// #define ADCD_FAULT_OVUV 0x04
// Variable Handler Errors
#define VARH_ERROR_MASK 0x06000000
#define VARH_ERROR_INVALID_VARIABLE 0x00000001
#define VARH_ERROR_INVALID_DATA 0x00000002
#define VARH_ERROR_READONLY 0x00000004
#define VARH_ERROR_OUTOFRANGE 0x00000008
#define VARH_ERROR_OUTOFRANGE_INT 0x00000010
#define VARH_ERROR_LOAD_FLASH 0x00000020 // Error while loading from flash -> sets all variables to default
// Peltier Controller Errors
#define PELTIER_ERROR_MASK 0x07000000
#define PELTIER_ERROR_SETVOLTAGE 0x00000001
#define PELTIER_ERROR_SETVOLTAGE_PID 0x00000002
#define PELTIER_ERROR_MAX_POWER 0x00000004
// Main Application Errors
#define MAIN_ERROR_MASK 0x08000000
#define MAIN_ERROR_REG_NOT_FOUND 0x00000001
#define MAIN_ERROR_CMD_NOT_FOUND 0x00000002
#define MAIN_ERROR_SAVE_FLASH 0x00000004
#define MAIN_ERROR_WATCHDOG 0x00000008 // not implemented
// HardFault Errors
#define HARDFAULT_ERROR_MASK 0x09000000
#define HARDFAULT_ERROR_IWDG 0x00000001
#define HARDFAULT_ERROR_SWRST 0x00000002 // Software Reset (if any hardfault occurs or user requests it via command)
//=================================================================================================
@ -87,6 +209,9 @@ extern "C" {
//=================================================================================================
BOOL ERRH_boInitializeModule( VOID );
VOID ERRH_vSetError( U32 u32Error );
U32 ERRH_u32GetError( VOID );
VOID ERRH_vClearError( VOID );
#ifdef __cplusplus
}

72
Core/Drivers/SPID_SpiDriver.c
View File

@ -41,6 +41,8 @@
// Drivers
#include "DIPO_DigitalPorts.h"
#include "ERRH_ErrorHandler.h"
// include STM32 drivers
#include "stm32l4xx_hal.h"
@ -173,14 +175,6 @@ BOOL SPID_boSend( SPID_StHandle* pstHandle )
BOOL boOK;
U32 u32Flags = 0;
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( pstHandle == NULL || pstHandle->enSPI >= SPID_eNumberOfSPIs )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return( FALSE );
}
#endif
osMutexAcquire( m_astSPI[pstHandle->enSPI].pstMutexID, osWaitForever );
// clear all flags
@ -214,14 +208,6 @@ BOOL SPID_boSendReceive( SPID_StHandle* pstHandle )
{
BOOL boOK;
U32 u32Flags = 0;
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( pstHandle == NULL || pstHandle->enSPI >= SPID_eNumberOfSPIs )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return( FALSE );
}
#endif
osMutexAcquire( m_astSPI[pstHandle->enSPI].pstMutexID, osWaitForever );
@ -257,13 +243,6 @@ BOOL SPID_boSendReceive( SPID_StHandle* pstHandle )
//-------------------------------------------------------------------------------------------------
VOID HAL_SPI_TxRxCpltCallback( SPI_HandleTypeDef *hspi )
{
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( hspi == NULL )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return;
}
#endif
SPID_EnSPIs enSPI = enGetSPI( hspi );
osEventFlagsSet( m_pstEventID, m_astSPI[enSPI].u32SPICompleteFlag );
@ -277,13 +256,6 @@ VOID HAL_SPI_TxRxCpltCallback( SPI_HandleTypeDef *hspi )
//-------------------------------------------------------------------------------------------------
VOID HAL_SPI_TxCpltCallback( SPI_HandleTypeDef *hspi )
{
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( hspi == NULL )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return;
}
#endif
SPID_EnSPIs enSPI = enGetSPI( hspi );
osEventFlagsSet( m_pstEventID, m_astSPI[enSPI].u32SPICompleteFlag );
@ -297,13 +269,6 @@ VOID HAL_SPI_TxCpltCallback( SPI_HandleTypeDef *hspi )
//-------------------------------------------------------------------------------------------------
VOID HAL_SPI_RxCpltCallback( SPI_HandleTypeDef *hspi )
{
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( hspi == NULL )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return;
}
#endif
SPID_EnSPIs enSPI = enGetSPI( hspi );
osEventFlagsSet( m_pstEventID, m_astSPI[enSPI].u32SPICompleteFlag );
@ -317,31 +282,7 @@ VOID HAL_SPI_RxCpltCallback( SPI_HandleTypeDef *hspi )
//-------------------------------------------------------------------------------------------------
VOID HAL_SPI_ErrorCallback( SPI_HandleTypeDef *hspi )
{
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( hspi == NULL )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
return;
}
#endif
// check rx overrun error
if( hspi->ErrorCode & HAL_SPI_ERROR_OVR )
{
//ELOG_ADD_LOG( ELOG_eSPIOverrunError );
}
// check rx dma transfer error
if( hspi->hdmarx->ErrorCode & HAL_DMA_ERROR_TE )
{
//ELOG_ADD_LOG( ELOG_eDMAHTransferError );
}
// check tx dma transfer error
if( hspi->hdmatx->ErrorCode & HAL_DMA_ERROR_TE )
{
//ELOG_ADD_LOG( ELOG_eDMAHTransferError );
}
ERRH_vSetError(SPI_ERROR_MASK | hspi->ErrorCode);
SPID_EnSPIs enSPI = enGetSPI( hspi );
osEventFlagsSet( m_pstEventID, m_astSPI[enSPI].u32SPIErrorFlag );
@ -355,13 +296,6 @@ VOID HAL_SPI_ErrorCallback( SPI_HandleTypeDef *hspi )
//-------------------------------------------------------------------------------------------------
PRIVATE SPID_EnSPIs enGetSPI( SPI_HandleTypeDef* pstSPI )
{
#if defined(PDEF_FUNCTION_PARAMETER_CHECK_ENABLED) && PDEF_FUNCTION_PARAMETER_CHECK_ENABLED == TRUE
if( pstSPI == NULL )
{
ELOG_ADD_LOG( ELOG_eInvalidFunctionParameter );
ASRT_ASSERT( FALSE );
}
#endif
for( U8 u8Cnt = 0; u8Cnt < SPID_eNumberOfSPIs; u8Cnt++ )
{

86
Core/Drivers/TEMP_Temperature.c
View File

@ -36,6 +36,8 @@
// Toolbox
#include "../Toolbox/UTIL_Utility.h"
#include "ERRH_ErrorHandler.h"
// Drivers
#include "ADCD_AdcDriver.h"
@ -160,20 +162,44 @@ PRIVATE VOID vTask( PVOID arg )
{
flTempData[ADCD_eWater] = flConvertADCData( u16ADC_data );
} else {
if( (u8error & ADCD_STATUS_DATA_ERROR) == ADCD_STATUS_DATA_ERROR ){
if( (u8error & ADCD_STATUS_DATA_ERROR) == ADCD_STATUS_DATA_ERROR ){
BOOL boFatal = TRUE;
if( (u8error & ADCD_FAULT_HIGHTHRESH) == ADCD_FAULT_HIGHTHRESH ){ // open
flTempData[ADCD_eWater] = 4200.0f;
boFatal &= FALSE;
}else if( (u8error & ADCD_FAULT_LOWTHRESH) == ADCD_FAULT_LOWTHRESH ){ // shorted
flTempData[ADCD_eWater] = -273.16f;
boFatal &= FALSE;
}else if( (u8error & ADCD_FAULT_REFINLOW) == ADCD_FAULT_REFINLOW ){
flTempData[ADCD_eWater] = -273.16f;
}else if( (u8error & ADCD_FAULT_REFINHIGH) == ADCD_FAULT_REFINHIGH ){
flTempData[ADCD_eWater] = -273.16f;
}else if( (u8error & ADCD_FAULT_RTDINLOW) == ADCD_FAULT_RTDINLOW ){
flTempData[ADCD_eWater] = -273.16f;
}else if( (u8error & ADCD_FAULT_OVUV) == ADCD_FAULT_OVUV ){
flTempData[ADCD_eWater] = -273.16f;
} else {
flTempData[ADCD_eWater] = -273.16f;
}
/** @todo call error handler temp data */
} else if( (u8error & ADCD_SPI_FAILURE) == ADCD_SPI_FAILURE ){
if(boFatal) ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORW_MASK | TEMP_ERROR_SENSOR_FAILURE | u8error);
/** @todo call error handler onchip spi failure */
/** @todo call error handler temp data */
} else if( (u8error & ADCD_SPI_FAILURE) == ADCD_SPI_FAILURE ){
flTempData[ADCD_eWater] = -273.16f;
ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORW_MASK | TEMP_ERROR_SPI_FAILURE);
} else {
flTempData[ADCD_eWater] = -273.16f;
ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORW_MASK | TEMP_ERROR_GENERAL_FAILURE);
}
u8error = 0;
boOK = TRUE;
}
flTempData[ADCD_eWater] = -273.16f;
u8error = 0;
boOK = TRUE;
}
boOK &= ADCD_boReadData( ADCD_eModule, &u8error, &u16ADC_data );
@ -183,41 +209,63 @@ PRIVATE VOID vTask( PVOID arg )
flTempData[ADCD_eModule] = flConvertADCData( u16ADC_data );
} else {
if( (u8error & ADCD_STATUS_DATA_ERROR) == ADCD_STATUS_DATA_ERROR ){
BOOL boFatal = TRUE;
if( (u8error & ADCD_FAULT_HIGHTHRESH) == ADCD_FAULT_HIGHTHRESH ){ // open
flTempData[ADCD_eModule] = 4200.0f;
boFatal &= FALSE;
}else if( (u8error & ADCD_FAULT_LOWTHRESH) == ADCD_FAULT_LOWTHRESH ){ // shorted
flTempData[ADCD_eModule] = -273.16f;
boFatal &= FALSE;
}else if( (u8error & ADCD_FAULT_REFINLOW) == ADCD_FAULT_REFINLOW ){
flTempData[ADCD_eModule] = -273.16f;
}else if( (u8error & ADCD_FAULT_REFINHIGH) == ADCD_FAULT_REFINHIGH ){
flTempData[ADCD_eModule] = -273.16f;
}else if( (u8error & ADCD_FAULT_RTDINLOW) == ADCD_FAULT_RTDINLOW ){
flTempData[ADCD_eModule] = -273.16f;
}else if( (u8error & ADCD_FAULT_OVUV) == ADCD_FAULT_OVUV ){
flTempData[ADCD_eModule] = -273.16f;
} else {
flTempData[ADCD_eModule] = -273.16f;
}
/** @todo call error handler temp data */
if(boFatal) ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORM_MASK | TEMP_ERROR_SENSOR_FAILURE | u8error);
} else if( (u8error & ADCD_SPI_FAILURE) == ADCD_SPI_FAILURE ){
flTempData[ADCD_eModule] = -273.16f;
/** @todo call error handler onchip spi failure */
ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORM_MASK | TEMP_ERROR_SPI_FAILURE);
} else {
flTempData[ADCD_eModule] = -273.16f;
ERRH_vSetError(TEMP_ERROR_MASK | TEMP_ERROR_SENSORM_MASK | TEMP_ERROR_GENERAL_FAILURE);
}
flTempData[ADCD_eModule] = -273.16f;
u8error = 0;
boOK = TRUE;
}
VARH_vSetVariableDataFromSystemFloat( VARH_eTemp_Water, flTempData[ADCD_eWater] );
VARH_vSetVariableDataFromSystemFloat( VARH_eTemp_Module, flTempData[ADCD_eModule] );
VARH_vSetVariableDataFromSystemFloat( VARH_eTemp_Diff, flTempData[ADCD_eWater] - flTempData[ADCD_eModule] );
// VARH_vSetVariableDataFromSystemFloat( VARH_eTemp_Diff, flTempData[ADCD_eWater] - flTempData[ADCD_eModule] );
osDelay(REFRESH_MS);
osDelay(REFRESH_MS);
}
}
//-------------------------------------------------------------------------------------------------
// Function: flConvertADCData
// Description: Converts resistor value to temperature data
// Description: Converts resistor value(PT1000) to temperature data
// Parameters: U16 u16RTemp
// Returns: U16, temperature in Celcius
//-------------------------------------------------------------------------------------------------
PRIVATE FLOAT flConvertADCData( U16 u16RTemp )
{
FLOAT u16R = u16RTemp / 8192.0f;
FLOAT u16R = u16RTemp / 8151.24f;
FLOAT flT = 9.9714f * u16R;
flT += 235.904f;

242
Core/Drivers/USFL_UserFlash.c
View File

@ -19,23 +19,11 @@
//
//-------------------------------------------------------------------------------------------------
//
// Description: This source file contains all functions dealing with internal flash for User Settings
// Description: This source file contains all functions dealing with the virtual eeprom
//
// STM32L432KBUX_FLASH.ld
// More info in the AN4894 or this link:
// https://www.st.com/en/embedded-software/x-cube-eeprom.html
//
// DATA (rwx) : ORIGIN = 0x801F800, LENGTH = 2K
//
// /* Sections */
// SECTIONS
// {
// /* NOLOAD is required for not ereasing this block */
// .user_data (NOLOAD) :
// {
// . = ALIGN(4);
// *(.user_data)
// . = ALIGN(4);
// } > DATA*/
// ...
//=================================================================================================
@ -46,27 +34,20 @@
//=================================================================================================
#include "USFL_UserFlash.h"
// Toolbox
#include "../Application/VARH_VariableHandler.h"
#include "UTIL_Utility.h"
// include STM32 drivers
#include "stm32l4xx_hal.h"
#include "cmsis_os2.h"
#include "eeprom_emul.h"
//=================================================================================================
// Section: DEFINITIONS
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
#define USERFLASHSIZE (2000/4) // Bytes -> 64 Bits
#define USERFLASHPAGE (63)
#define VARDEF 0xABCDEF
#define STARTDEF (((U64)0xAA01F055 << 32) + (VARDEF << 2))
//=================================================================================================
@ -88,12 +69,6 @@
// Description: Definition of local Structures (visible by this module only).
//=================================================================================================
FLASH_EraseInitTypeDef stEreaseInit = {
FLASH_TYPEERASE_PAGES,
FLASH_BANK_1,
USERFLASHPAGE,
1
};
//=================================================================================================
@ -101,24 +76,27 @@ FLASH_EraseInitTypeDef stEreaseInit = {
// Description: Definition of local variables (visible by this module only).
//=================================================================================================
U32 u32VarPointer = 0;
LOCAL osMutexId_t m_pstMutexID = NULL;
//=================================================================================================
// Section: LOCAL CONSTANTS
// Description: Definition of local constants (visible by this module only).
//=================================================================================================
__attribute__((__section__(".user_data"))) const U64 UserFlash[USERFLASHSIZE];
LOCAL CONST osMutexAttr_t m_stMutexAttr =
{
"USFL_Mutex", // human readable mutex name
osMutexRecursive | osMutexPrioInherit, // attr_bits
NULL, // memory for control block
0U // size for control block
};
//=================================================================================================
// Section: LOCAL FUNCTIONS (PROTOTYPES)
// Description: Definition of local functions (visible by this module only).
//=================================================================================================
BOOL vEreaseUserFlash( void );
U32 vFindNextFreePointer( void );
U32 u32FindLastPointer( void );
U8 u8ConvertWordsToDoubleWords( U8 u8Words );
//=================================================================================================
// Section: GLOBAL FUNCTIONS
@ -131,28 +109,87 @@ U8 u8ConvertWordsToDoubleWords( U8 u8Words );
// Parameters: None
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL USFL_boInitializeModule( VOID )
{
BOOL boOK = TRUE;
if( UserFlash[0] != STARTDEF ){
boOK &= vEreaseUserFlash();
}
boOK &= ( ( m_pstMutexID = osMutexNew( &m_stMutexAttr )) == NULL) ? FALSE : TRUE;
boOK &= USFL_vUnlock();
boOK &= EE_Init(EE_FORCED_ERASE) == EE_OK ? TRUE : FALSE;
boOK &= USFL_vLock();
return( boOK );
}
VARH_UVariable USFL_uGetVariable ( void ){
//-------------------------------------------------------------------------------------------------
// Function: USFL_boGetVariable
// Description: Gets a variable out of the virtual eeprom
// Parameters: U8 u8Variable -> virtual address of variable
// U32 * u32Variable -> pointer to data
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL USFL_boGetVariable ( U8 u8Variable, VARH_UVariable * uVariable ){
BOOL boOK = TRUE;
if( u32VarPointer == 0 ) u32VarPointer = u32FindLastPointer();
boOK &= EE_ReadVariable32bits( (U16) u8Variable, (PU32)uVariable ) == EE_OK ? TRUE : FALSE;
return boOK;
}
//-------------------------------------------------------------------------------------------------
// Function: USFL_boSetVariable
// Description: Writes a variable into the virtual eeprom
// Parameters: U8 u8Variable -> virtual address of variable
// U32 u32Variable -> data to write
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL USFL_boSetVariable ( U8 u8Variable, VARH_UVariable uVariable ){
BOOL boOK = TRUE;
EE_Status ee_status = EE_OK;
ee_status = EE_WriteVariable32bits( (U16) u8Variable, uVariable.u32Val );
/* Start cleanup mode, if cleanup is needed */
if ((ee_status & EE_STATUSMASK_CLEANUP) == EE_STATUSMASK_CLEANUP) {
boOK &= (ee_status |= EE_CleanUp()) == EE_OK ? TRUE : FALSE;
boOK &= EE_WriteVariable32bits( (U16) u8Variable, uVariable.u32Val ) == EE_OK ? TRUE : FALSE;
}
if ((ee_status & EE_STATUSMASK_ERROR) == EE_STATUSMASK_ERROR) {boOK &= FALSE;}
return boOK;
}
//-------------------------------------------------------------------------------------------------
// Function: USFL_vLock
// Description: Locks the Flash, no more clearing and programming possible
// Parameters: None
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL USFL_vLock( VOID ){
BOOL boOK = TRUE;
boOK &= HAL_FLASH_Lock() == HAL_OK ? TRUE : FALSE;
osMutexRelease( m_pstMutexID ); // release mutex
return boOK;
}
//-------------------------------------------------------------------------------------------------
// Function: USFL_vUnlock
// Description: Unlocks the Flash, clearing and programming possible
// Parameters: None
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL USFL_vUnlock( VOID ){
BOOL boOK = TRUE;
osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex
boOK &= HAL_FLASH_Unlock() == HAL_OK ? TRUE : FALSE;
return boOK;
}
//=================================================================================================
@ -160,116 +197,3 @@ VARH_UVariable USFL_uGetVariable ( void ){
// Descriptionn: Definition (implementation) of local functions.
//=================================================================================================
//-------------------------------------------------------------------------------------------------
// Function: u32FindNextFreePointer
// Description: Finds the next free sector in the flash for saving variables
// Parameters: None
// Returns: U32 next free pointer
//-------------------------------------------------------------------------------------------------
U32 u32FindNextFreePointer( void ){
BOOL boFound = FALSE;
U32 u32Pointer = u32VarPointer;
while(!boFound){
if( ( ( UserFlash[u32Pointer] >> 8 ) & 0xFFFFFF ) == VARDEF ){
U8 u8Size = UserFlash[u32Pointer] & 0xFF;
if( u8Size == 0 ){
boFound = TRUE;
} else {
u32Pointer += u8ConvertWordsToDoubleWords(u8Size);
}
} else {
u32Pointer += 1;
}
if( u32Pointer >= USERFLASHSIZE ){
u32Pointer = 1;
break;
}
}
return u32Pointer;
}
//-------------------------------------------------------------------------------------------------
// Function: u32FindLastPointer
// Description: Finds the next free sector in the flash for saving variables
// Parameters: None
// Returns: U32 next free pointer
//-------------------------------------------------------------------------------------------------
U32 u32FindLastPointer( void ){
BOOL boFound = FALSE;
U32 u32Pointer = 0;
U8 u8LastSize = 0;
while(!boFound){
if( ( UserFlash[u32Pointer] >> 40) == VARDEF ){
U8 u8Size = UserFlash[u32Pointer] & 0xFF;
if( u8Size == 0 ){
boFound = TRUE;
u32Pointer -= u8ConvertWordsToDoubleWords(u8LastSize);
} else {
u32Pointer += u8ConvertWordsToDoubleWords(u8Size);
u8LastSize = u8Size;
}
} else {
u32Pointer += 1;
}
if( u32Pointer >= USERFLASHSIZE ){
u32Pointer = 1;
break;
}
}
return u32Pointer;
}
//-------------------------------------------------------------------------------------------------
// Function: u8ConvertWordsToDoubleWords
// Description: Converts 32Bit Word size to 64 Bit Double Word size for saving Vars
// Parameters: U8 u8Words
// Returns: U8 Double Words
//-------------------------------------------------------------------------------------------------
U8 u8ConvertWordsToDoubleWords( U8 u8Words ) {
U8 u8DWords;
u8Words += 1; // + VARDEF
u8DWords = u8Words / 2;
u8DWords += u8Words % 2;
return u8DWords;
}
//-------------------------------------------------------------------------------------------------
// Function: vEreaseUserFlash
// Description: Ereases the User Flash Sector
// Parameters: None
// Returns: Boolean TRUE if successful
//-------------------------------------------------------------------------------------------------
BOOL vEreaseUserFlash( void ){
uint32_t u32PageError = 0;
BOOL boOK = TRUE;
HAL_FLASH_Unlock();
boOK &= HAL_FLASHEx_Erase(&stEreaseInit, &u32PageError) == HAL_OK ? TRUE : FALSE;
if( !boOK ){
return FALSE;
}
HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, (U32) &UserFlash[0], STARTDEF);
HAL_FLASH_Lock();
return TRUE;
}

7
Core/Drivers/USFL_UserFlash.h
View File

@ -34,7 +34,7 @@ extern "C" {
//=================================================================================================
#include "../SDEF_StandardDefinitions.h"
#include "VARH_VariableHandler.h"
//=================================================================================================
@ -87,6 +87,11 @@ extern "C" {
//=================================================================================================
BOOL USFL_boInitializeModule( VOID );
BOOL USFL_boGetVariable ( U8 u8Variable, VARH_UVariable * uVariable );
BOOL USFL_boSetVariable ( U8 u8Variable, VARH_UVariable uVariable );
BOOL USFL_vLock( VOID );
BOOL USFL_vUnlock( VOID );
#ifdef __cplusplus
}

1
Core/Inc/main.h
View File

@ -76,6 +76,7 @@ void Error_Handler(void);
#define CS2_GPIO_Port GPIOB
#define PG_Pin GPIO_PIN_7
#define PG_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */

4
Core/Inc/stm32l4xx_hal_conf.h
View File

@ -40,7 +40,8 @@
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_CAN_MODULE_ENABLED
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
#define HAL_I2C_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_DCMI_MODULE_ENABLED */
@ -85,7 +86,6 @@
/*#define HAL_PSSI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED

2
Core/Inc/stm32l4xx_it.h
View File

@ -23,7 +23,7 @@
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/

61
Core/Src/main.c
View File

@ -30,6 +30,7 @@
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "../Application/INIT_Initialization.h"
#include "../Application/PECO_PeltierController.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -52,6 +53,8 @@ DMA_HandleTypeDef hdma_adc1;
CAN_HandleTypeDef hcan1;
CRC_HandleTypeDef hcrc;
DAC_HandleTypeDef hdac1;
I2C_HandleTypeDef hi2c1;
@ -83,6 +86,7 @@ static void MX_DAC1_Init(void);
static void MX_SPI1_Init(void);
static void MX_I2C1_Init(void);
static void MX_IWDG_Init(void);
static void MX_CRC_Init(void);
void vDefaultTask(void *argument);
/* USER CODE BEGIN PFP */
@ -117,6 +121,7 @@ static void VectorBase_Config(void)
*/
int main(void)
{
/* USER CODE BEGIN 1 */
VectorBase_Config();
/* USER CODE END 1 */
@ -146,6 +151,7 @@ int main(void)
MX_SPI1_Init();
MX_I2C1_Init();
MX_IWDG_Init();
MX_CRC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@ -185,6 +191,7 @@ int main(void)
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
@ -211,6 +218,7 @@ void SystemClock_Config(void)
{
Error_Handler();
}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
@ -228,6 +236,7 @@ void SystemClock_Config(void)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
@ -260,6 +269,7 @@ static void MX_ADC1_Init(void)
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
@ -285,6 +295,7 @@ static void MX_ADC1_Init(void)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_6;
@ -297,6 +308,7 @@ static void MX_ADC1_Init(void)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_16;
@ -305,6 +317,7 @@ static void MX_ADC1_Init(void)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_7;
@ -313,6 +326,7 @@ static void MX_ADC1_Init(void)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_15;
@ -366,6 +380,37 @@ static void MX_CAN1_Init(void)
}
/**
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
/* USER CODE BEGIN CRC_Init 0 */
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
if (HAL_CRC_Init(&hcrc) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
/**
* @brief DAC1 Initialization Function
* @param None
@ -383,6 +428,7 @@ static void MX_DAC1_Init(void)
/* USER CODE BEGIN DAC1_Init 1 */
/* USER CODE END DAC1_Init 1 */
/** DAC Initialization
*/
hdac1.Instance = DAC1;
@ -390,6 +436,7 @@ static void MX_DAC1_Init(void)
{
Error_Handler();
}
/** DAC channel OUT1 config
*/
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
@ -428,7 +475,7 @@ static void MX_I2C1_Init(void)
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
hi2c1.Init.Timing = 0x10909CEC;
hi2c1.Init.Timing = 0x10D19CE4;
hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
@ -440,12 +487,14 @@ static void MX_I2C1_Init(void)
{
Error_Handler();
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
Error_Handler();
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
@ -558,6 +607,8 @@ static void MX_DMA_Init(void)
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
@ -612,6 +663,8 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
@ -641,6 +694,11 @@ void vDefaultTask(void *argument)
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
@ -665,4 +723,3 @@ void assert_failed(uint8_t *file, uint32_t line)
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

234
Core/Src/stm32l4xx_hal_msp.c
View File

@ -68,6 +68,7 @@ extern DMA_HandleTypeDef hdma_spi1_tx;
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
@ -85,20 +86,21 @@ void HAL_MspInit(void)
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
@ -150,26 +152,27 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(ADC1_IRQn);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC_CLK_DISABLE();
@ -188,27 +191,27 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
/* ADC1 interrupt DeInit */
HAL_NVIC_DisableIRQ(ADC1_IRQn);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief CAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
* @brief CAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hcan->Instance==CAN1)
{
/* USER CODE BEGIN CAN1_MspInit 0 */
/* USER CODE BEGIN CAN1_MspInit 0 */
/* USER CODE END CAN1_MspInit 0 */
/* USER CODE END CAN1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
@ -233,26 +236,27 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
/* USER CODE BEGIN CAN1_MspInit 1 */
/* USER CODE BEGIN CAN1_MspInit 1 */
/* USER CODE END CAN1_MspInit 1 */
/* USER CODE END CAN1_MspInit 1 */
}
}
/**
* @brief CAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
* @brief CAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
{
if(hcan->Instance==CAN1)
{
/* USER CODE BEGIN CAN1_MspDeInit 0 */
/* USER CODE BEGIN CAN1_MspDeInit 0 */
/* USER CODE END CAN1_MspDeInit 0 */
/* USER CODE END CAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CAN1_CLK_DISABLE();
@ -267,27 +271,72 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn);
/* USER CODE BEGIN CAN1_MspDeInit 1 */
/* USER CODE BEGIN CAN1_MspDeInit 1 */
/* USER CODE END CAN1_MspDeInit 1 */
/* USER CODE END CAN1_MspDeInit 1 */
}
}
/**
* @brief DAC MSP Initialization
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
* @brief CRC MSP Initialization
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
/**
* @brief CRC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspDeInit 0 */
/* USER CODE END CRC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CRC_CLK_DISABLE();
/* USER CODE BEGIN CRC_MspDeInit 1 */
/* USER CODE END CRC_MspDeInit 1 */
}
}
/**
* @brief DAC MSP Initialization
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspInit 0 */
/* USER CODE BEGIN DAC1_MspInit 0 */
/* USER CODE END DAC1_MspInit 0 */
/* USER CODE END DAC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC1_CLK_ENABLE();
@ -300,26 +349,27 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN DAC1_MspInit 1 */
/* USER CODE BEGIN DAC1_MspInit 1 */
/* USER CODE END DAC1_MspInit 1 */
/* USER CODE END DAC1_MspInit 1 */
}
}
/**
* @brief DAC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
* @brief DAC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspDeInit 0 */
/* USER CODE BEGIN DAC1_MspDeInit 0 */
/* USER CODE END DAC1_MspDeInit 0 */
/* USER CODE END DAC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DAC1_CLK_DISABLE();
@ -328,28 +378,29 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
/* USER CODE BEGIN DAC1_MspDeInit 1 */
/* USER CODE BEGIN DAC1_MspDeInit 1 */
/* USER CODE END DAC1_MspDeInit 1 */
/* USER CODE END DAC1_MspDeInit 1 */
}
}
/**
* @brief I2C MSP Initialization
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
* @brief I2C MSP Initialization
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
@ -373,26 +424,27 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
/**
* @brief I2C MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
* @brief I2C MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C1_CLK_DISABLE();
@ -404,27 +456,27 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10);
/* USER CODE BEGIN I2C1_MspDeInit 1 */
/* USER CODE BEGIN I2C1_MspDeInit 1 */
/* USER CODE END I2C1_MspDeInit 1 */
/* USER CODE END I2C1_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
@ -479,26 +531,27 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
/* SPI1 interrupt Init */
HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(SPI1_IRQn);
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
/**
* @brief SPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
* @brief SPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
{
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspDeInit 0 */
/* USER CODE BEGIN SPI1_MspDeInit 0 */
/* USER CODE END SPI1_MspDeInit 0 */
/* USER CODE END SPI1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
@ -515,9 +568,9 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
/* SPI1 interrupt DeInit */
HAL_NVIC_DisableIRQ(SPI1_IRQn);
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
}
}
@ -525,4 +578,3 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

16
Core/Src/stm32l4xx_it.c
View File

@ -25,6 +25,7 @@
#include "task.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "../Application/PECO_PeltierController.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -77,6 +78,8 @@ extern SPI_HandleTypeDef hspi1;
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
@ -93,6 +96,9 @@ void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
@ -108,6 +114,9 @@ void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
@ -123,6 +132,9 @@ void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
@ -138,6 +150,9 @@ void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
PECO_Enable( FALSE );
HAL_NVIC_SystemReset();
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
@ -317,4 +332,3 @@ void DMA2_Channel3_IRQHandler(void)
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

10
Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h
View File

@ -930,7 +930,7 @@ typedef struct
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL)
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
@ -1153,7 +1153,7 @@ typedef struct
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
/* Note: No specific macro feature on this device */
@ -5797,7 +5797,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
@ -8825,7 +8825,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
@ -13136,7 +13136,7 @@ typedef struct
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
#define USART_TCBGT_SUPPORT

2
Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
View File

@ -106,7 +106,7 @@
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

542
Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

@ -37,14 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5)
#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@ -110,6 +108,10 @@ extern "C" {
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
#if defined(STM32H5)
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
#endif /* STM32H5 */
/**
* @}
*/
@ -137,7 +139,8 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@ -211,6 +214,11 @@ extern "C" {
#endif
#endif
#if defined(STM32U5)
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
#endif
/**
* @}
*/
@ -231,9 +239,13 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
#if defined(STM32H5) || defined(STM32C0)
#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
#endif
/**
* @}
*/
@ -275,7 +287,13 @@ extern "C" {
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#if defined(STM32H5)
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -340,7 +358,8 @@ extern "C" {
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@ -500,7 +519,7 @@ extern "C" {
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0)
#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@ -525,7 +544,20 @@ extern "C" {
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
#if defined(STM32U0)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_USER_nBOOT1 OB_USER_NBOOT1
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U0 */
/**
* @}
@ -569,6 +601,106 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
#if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
#define SYSCFG_ETH_MII SBS_ETH_MII
#define SYSCFG_ETH_RMII SBS_ETH_RMII
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SYSCFG_SAU SBS_SAU
#define SYSCFG_MPU_SEC SBS_MPU_SEC
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#else
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#endif /* __ARM_FEATURE_CMSE */
#define SYSCFG_CLK SBS_CLK
#define SYSCFG_CLASSB SBS_CLASSB
#define SYSCFG_FPU SBS_FPU
#define SYSCFG_ALL SBS_ALL
#define SYSCFG_SEC SBS_SEC
#define SYSCFG_NSEC SBS_NSEC
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
#define HAL_SYSCFG_Lock HAL_SBS_Lock
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
#endif /* __ARM_FEATURE_CMSE */
#endif /* STM32H5 */
/**
* @}
*/
@ -636,14 +768,16 @@ extern "C" {
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@ -665,13 +799,28 @@ extern "C" {
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5)
#if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */
#endif /* STM32U5 || STM32H5 */
#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
#if defined(STM32WBA)
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
#endif /* STM32WBA */
/**
* @}
*/
@ -681,7 +830,25 @@ extern "C" {
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
#if defined(STM32H5)
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
#endif /* STM32H5 */
#if defined(STM32H5) || defined(STM32U5)
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@ -862,7 +1029,8 @@ extern "C" {
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -1000,7 +1168,7 @@ extern "C" {
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -1084,8 +1252,8 @@ extern "C" {
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@ -1096,15 +1264,42 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
#endif /* STM32F7 */
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@ -1271,7 +1466,7 @@ extern "C" {
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
#if defined(STM32U5) || defined(STM32MP2)
#if defined(STM32U5)
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
#endif
@ -1384,30 +1579,40 @@ extern "C" {
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@ -1415,6 +1620,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
/**
* @}
*/
@ -1578,7 +1785,8 @@ extern "C" {
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@ -1587,8 +1795,10 @@ extern "C" {
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@ -1622,16 +1832,21 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@ -1756,6 +1971,17 @@ extern "C" {
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
@ -1764,6 +1990,8 @@ extern "C" {
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
@ -1774,6 +2002,7 @@ extern "C" {
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif
@ -1782,6 +2011,20 @@ extern "C" {
* @}
*/
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@ -1807,7 +2050,8 @@ extern "C" {
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@ -2064,7 +2308,8 @@ extern "C" {
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@ -2089,8 +2334,8 @@ extern "C" {
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F302xE) || defined(STM32F302xC)
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@ -2123,8 +2368,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@ -2181,8 +2426,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F373xC) ||defined(STM32F378xx)
#endif
#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@ -2199,7 +2444,7 @@ extern "C" {
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif
#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@ -2236,8 +2481,10 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
/**
* @}
*/
@ -2396,7 +2643,9 @@ extern "C" {
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@ -2405,8 +2654,12 @@ extern "C" {
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
} while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
} while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@ -2442,8 +2695,8 @@ extern "C" {
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@ -2493,6 +2746,12 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#if defined(STM32C0)
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@ -2947,6 +3206,11 @@ extern "C" {
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@ -3411,7 +3675,12 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#if defined(STM32U0)
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
#endif
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3513,8 +3782,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@ -3524,8 +3795,8 @@ extern "C" {
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@ -3541,16 +3812,106 @@ extern "C" {
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
#endif
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
#if defined(STM32H5)
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
#endif /* STM32H5 */
/**
* @}
@ -3568,7 +3929,9 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3603,6 +3966,13 @@ extern "C" {
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
defined (STM32H7) || \
defined (STM32L0) || defined (STM32L1) || \
defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@ -3621,6 +3991,11 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
#if defined (STM32H5)
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
#endif /* STM32H5 */
/**
* @}
*/
@ -3632,7 +4007,7 @@ extern "C" {
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@ -3879,6 +4254,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/
@ -3969,6 +4347,16 @@ extern "C" {
* @}
*/
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32F7)
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
#endif /* STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/

672
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h
View File

@ -60,9 +60,10 @@ typedef struct
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
sequence interruption.
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
If oversampling is enabled on both regular and injected groups, this
parameter is discarded and forced to setting
"ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
during injection sequence).
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
} ADC_OversamplingTypeDef;
@ -77,23 +78,31 @@ typedef struct
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled
* without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
* on groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update another
* parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
clock derived from system clock or PLL (Refer to reference manual for list of
clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
Note: In case of usage of channels on injected group, ADC frequency should be
lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits,
AHB clock frequency /2 for resolution 6 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must
be enabled only if the system clock has a 50% duty clock cycle (APB
prescaler configured inside RCC must be bypassed and PCLK clock must have
50% duty cycle). Refer to reference manual for details.
Note: In case of usage of asynchronous clock, the selected clock must be
preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
@ -104,84 +113,131 @@ typedef struct
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
Scan direction is upward: from rank 1 to rank 'n'.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have
main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the
one defined in rank 1). Parameters 'NbrOfConversion' and
'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined
by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each
channel in sequencer). Scan direction is upward: from rank 1 to
rank 'n'.
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
previous conversion (for ADC group regular) or previous sequence (for ADC group
injected) has been retrieved by user software, using function HAL_ADC_GetValue()
or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to
the speed of the system that reads the data. Moreover, this avoids risk of
overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
flag (by CPU to free the IRQ pending event or by DMA).
Auto wait will work but fort a very short time, discarding its intended
benefit (except specific case of high load of CPU or DMA transfers which
can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and
HAL_ADC_GetValue() to retrieve conversion result and trig another
conversion start. (in case of usage of ADC group injected, use the
equivalent functions HAL_ADCExInjected_Start(),
HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
or continuous mode for ADC group regular, after the first ADC conversion
start trigger occurred (software start or external trigger). This parameter
can be set to ENABLE or DISABLE. */
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16.
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
sequencer.
This parameter is dependent on ScanConvMode:
- sequencer configured to fully configurable:
Number of ranks in the scan sequence is configurable using this parameter.
Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
Afterwards, when all needed sequencer ranks are set, parameter
'NbrOfConversion' can be updated without modifying configuration of
sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
- sequencer configured to not fully configurable:
Number of ranks in the scan sequence is defined by number of channels set in
the sequence. This parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8.
Note: This parameter must be modified when no conversion is on going on regular
group (ADC disabled, or ADC enabled without continuous mode or external
trigger that could launch a conversion). */
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled.
If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: On this STM32 series, ADC group regular number of discontinuous
ranks increment is fixed to one-by-one. */
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence
of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
transfer stops when number of conversions is reached) or in continuous
mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode.
Otherwise an overrun will be triggered when DMA buffer maximum
pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: In case of overrun set to data preserved and usage with programming model
with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
conversion flags, this induces the release of the preserved data. If
needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
placed in user program code (called before end of conversion flags clear)
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
- Usage with ADC conversion by polling for event or interruption: Error is
reported only if overrun is set to data preserved. If overrun is set to
data overwritten, user can willingly not read all the converted data,
this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun
setting (DMA is expected to process all data from data register). */
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
Note: This parameter can be modified only if there is no conversion is
ongoing on ADC groups regular and injected */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
Caution: this setting overwrites the previous oversampling configuration
if oversampling is already enabled. */
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM.
This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
Note: This parameter can be modified only if there is no conversion is ongoing
(both ADSTART and JADSTART cleared). */
#endif /* ADC_CFGR_DFSDMCFG */
} ADC_InitTypeDef;
@ -191,56 +247,72 @@ typedef struct
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
* on going on regular group.
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
* regular and injected groups.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
* on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update another
* parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
Note: Depending on devices and ADC instances, some channels may not be available
on device package pins. Refer to device datasheet for channels
availability. */
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
Note: to disable a channel or change order of conversion sequencer, rank
containing a previous channel setting can be overwritten by the new channel
setting (or parameter number of conversions adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
Caution: This parameter applies to a channel that can be used into regular and/or injected group.
It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Caution: This parameter applies to a channel that can be used into regular
and/or injected group. It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...),
sampling time constraints must be respected (sampling time can be adjusted
in function of ADC clock frequency and sampling time setting).
Refer to device datasheet for timings values. */
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
In differential mode: Differential measurement is carried out between the
selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
Caution: This parameter applies to a channel that can be used in a regular
and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
Note: Refer to Reference Manual to ensure the selected channel is available in
differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is
not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start
conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error
reporting (as it can be the expected behavior in case of another parameter
update on the fly) */
uint32_t OffsetNumber; /*!< Select the offset number
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
Caution: Only one offset is allowed per channel. This parameter overwrites the
last setting. */
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
Note: This parameter must be modified when no conversion is on going on both
regular and injected groups (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */
} ADC_ChannelConfTypeDef;
@ -248,47 +320,66 @@ typedef struct
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and
injected.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
channels, ADC groups regular and-or injected.
For Analog Watchdog 2 and 3: Several channels can be monitored by applying
successively the AWD init structure. Channels on ADC
group regular and injected are not differentiated: Set
value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
channel.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
is configured on single channel (only 1 channel can be
monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
call successively the function HAL_ADC_AnalogWDGConfig()
for each channel to be added (or removed with value
'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
ADC data register bitfield [15:4] (12 most significant bits).*/
} ADC_AnalogWDGConfTypeDef;
/**
@ -319,7 +410,8 @@ typedef struct
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization,
calibration, ...) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
/* States of ADC errors */
@ -328,15 +420,20 @@ typedef struct
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
(either by continuous mode, external trigger, low power
auto power-on (if feature available), multimode ADC master
control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur
(either by auto-injection mode, external trigger, low
power auto power-on (if feature available), multimode
ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
@ -346,7 +443,8 @@ typedef struct
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC
master (when feature available) */
/**
* @}
@ -361,20 +459,25 @@ typedef struct __ADC_HandleTypeDef
typedef struct
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
conversions setting */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up
structure */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete
callback */
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
overflow callback */
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
@ -439,22 +542,37 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
without prescaler */
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
with prescaler division by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
prescaler */
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
division by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
division by 4 */
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
division by 6 */
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
division by 8 */
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
division by 10 */
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
division by 12 */
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
division by 16 */
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
division by 32 */
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
division by 64 */
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
division by 128 */
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
division by 256 */
/**
* @}
*/
@ -473,8 +591,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
(alignment on data register LSB bit 0)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
(alignment on data register MSB bit 15)*/
/**
* @}
*/
@ -492,23 +612,40 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion
trigger software start */
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM1 TRGO. */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
trigger from external peripheral: TIM1 TRGO2. */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion
trigger from external peripheral: TIM1 channel 1 event (capture compare). */
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion
trigger from external peripheral: TIM1 channel 2 event (capture compare). */
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion
trigger from external peripheral: TIM1 channel 3 event (capture compare). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM2 TRGO. */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion
trigger from external peripheral: TIM2 channel 2 event (capture compare). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM3 TRGO. */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM4 TRGO. */
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion
trigger from external peripheral: TIM4 channel 4 event (capture compare). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM6 TRGO. */
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM8 TRGO. */
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion
trigger from external peripheral: TIM8 TRGO2. */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
trigger from external peripheral: TIM15 TRGO. */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion
trigger from external peripheral: external interrupt line 11. */
/**
* @}
*/
@ -516,10 +653,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
disabled (SW start)*/
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion
trigger polarity set to rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion
trigger polarity set to falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
trigger polarity set to both rising and falling edges */
/**
* @}
*/
@ -536,8 +677,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case
of overrun: data preserved */
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case
of overrun: data overwritten */
/**
* @}
*/
@ -577,7 +720,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
#if defined(ADC_SMPR1_SMPPLUS)
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5
ADC clock cycles. If selected, this sampling time replaces sampling time
2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
#endif /* ADC_SMPR1_SMPPLUS */
/**
* @}
@ -588,44 +733,56 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
/* all ADC instances (refer to Reference Manual). */
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal
voltage reference. */
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage
through a divider ladder of factor 1/3 to have channel voltage always below
Vdda. */
#if defined(ADC1) && !defined(ADC2)
#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< Internal channel DAC1 channel 1,
channel specific to ADC1. This channel is shared with Internal temperature
sensor, selection is done using function
@ref LL_ADC_SetCommonPathInternalCh(). */
#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< Internal channel DAC1 channel 2,
channel specific to ADC1. This channel is shared with Internal Vbat,
selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
#elif defined(ADC2)
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< Internal channel DAC1 channel 1,
channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< Internal channel DAC1 channel 2,
channel specific to ADC2 */
#if defined(ADC3)
#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< Internal channel DAC1 channel 1,
channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< Internal channel DAC1 channel 2,
channel specific to ADC3 */
#endif /* ADC3 */
#endif /* ADC1 && !ADC2 */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
* @{
*/
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
@ -635,16 +792,23 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @}
*/
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular
group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an
injected group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
| ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular
and injected groups single channel */
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular
group all channels */
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected
group all channels */
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular
and injected groups all channels */
/**
* @}
*/
@ -652,14 +816,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
* to result as the ADC oversampling conversion data (before potential shift)
*/
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
/**
* @}
*/
@ -667,15 +835,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
/**
* @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
* conversion data)
*/
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
/**
* @}
*/
@ -683,8 +855,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
continuous mode (all conversions of OVS ratio are done from 1 trigger) */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
discontinuous mode (each conversion of OVS ratio needs a trigger) */
/**
* @}
*/
@ -692,8 +866,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
* @{
*/
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
during injection sequence */
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during
injection sequence */
/**
* @}
*/
@ -701,16 +877,21 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
/**
* @note Analog watchdog 1 is available on all stm32 series
* Analog watchdog 2 and 3 are not available on all series
*/
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
/**
* @}
*/
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
with other STM32 devices having only one analog watchdog */
/** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{
@ -723,11 +904,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog
watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog
watchdog) */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< Analog watchdog 1 interrupt source: naming for compatibility
with other STM32 series having only one analog watchdog */
/**
* @}
@ -748,7 +932,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other
STM32 series having only one analog watchdog */
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
@ -829,7 +1014,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
* or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
@ -837,7 +1023,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
* @param NUMBER number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
* or RESET (NUMBER is null or too large)
*/
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
@ -1261,7 +1448,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
* (6) On STM32L4, parameter available on devices with several ADC instances.\n
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
* 4.21 Ms/s)).\n
* (1, 2, 3, 4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
@ -1324,7 +1512,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* (6) On STM32L4, parameter available on devices with several ADC instances.\n
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
* connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
@ -1668,11 +1857,15 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
* @note ADC measurement data must correspond to a resolution of 12bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
* On STM32L4, refer to device datasheet parameter "Avg_Slope".
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
* On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
(unit: uV/DegCelsius).
* On STM32L4, refer to device datasheet parameter "Avg_Slope".
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
temperature and Vref+ defined in parameters below) (unit: mV).
* On STM32L4, refer to device datasheet parameter "V30"
(corresponding to TS_CAL1).
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
@ -1753,7 +1946,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
@ -1770,8 +1963,9 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
/**
* @}
@ -1781,8 +1975,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
/**
* @}
@ -1792,7 +1986,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
* @}
*/
/* Private functions -----------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup ADC_Private_Functions ADC Private Functions
* @{
*/

475
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h
View File

@ -55,125 +55,190 @@ typedef struct
/**
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
* @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
* InjectedOffsetNumber, InjectedOffset
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
* InjectedDiscontinuousConvMode,
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
* InjecOversamplingMode, InjecOversampling.
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
* 'InjectedSingleDiff')
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
* without conversion on going on injected group.
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
* ADC enabled without conversion on going on regular and injected groups.
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
* 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
* on ADC groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update another
* parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
Note: Depending on devices and ADC instances, some channels may not be
available on device package pins. Refer to device datasheet for
channels availability. */
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
Note: to disable a channel or change order of conversion sequencer,
rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions
adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles.
Conversion time is the addition of sampling time and processing time
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
Caution: This parameter applies to a channel that can be used in a
regular and/or injected group. It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt, ...),
sampling time constraints must be respected (sampling time can be
adjusted in function of ADC clock frequency and sampling time
setting). Refer to device datasheet for timings values. */
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
In differential mode: Differential measurement is between the selected
channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured
automatically.
This parameter must be a value of
@ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
Caution: This parameter applies to a channel that can be used in a
regular and/or injected group. It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is
available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel
'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC
start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error
reporting (as it can be the expected behavior in case of another
parameter update on the fly) */
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
Caution: Only one offset is allowed per channel. This parameter
overwrites the last setting. */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going
on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a
conversion). */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group
injected sequencer.
To use the injected group sequencer and convert several ranks, parameter
'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
injected group can impact the configuration of other channels previously
set. */
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode is used only if sequencer is enabled (parameter
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
Note: This parameter must be modified when ADC is disabled (before ADC
start conversion or after ADC stop conversion).
Note: For injected group, discontinuous mode converts the sequence
channel by channel (discontinuous length fixed to 1 rank).
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the
configuration of other channels previously set. */
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion
after regular one
This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
To maintain JAUTO always enabled, DMA must be configured in circular mode.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
Note: To use Automatic injected conversion, discontinuous mode must
be disabled ('DiscontinuousConvMode' and
'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external
triggers must be disabled ('ExternalTrigInjecConv' set to
ADC_INJECTED_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in
normal mode (single shot) JAUTO will be stopped upon DMA transfer
complete.
To maintain JAUTO always enabled, DMA must be configured in
circular mode.
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
on injected group can impact the configuration of other channels
previously set. */
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
This parameter can be set to ENABLE or DISABLE.
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
new injected context is set when queue is full, error is triggered by interruption and through function
If context queue is enabled, injected sequencer&channels configurations
are queued on up to 2 contexts. If a
new injected context is set when queue is full, error is triggered by
interruption and through function
'HAL_ADCEx_InjectedQueueOverflowCallback'.
Caution: This feature request that the sequence is fully configured before injected conversion start.
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
Caution: This feature request that the sequence is fully configured
before injected conversion start.
Therefore, configure channels with as many calls to
HAL_ADCEx_InjectedConfigChannel() as the
'InjectedNbrOfConversion' parameter.
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the
configuration of other channels previously set.
Note: This parameter must be modified when ADC is disabled (before ADC
start conversion or after ADC stop conversion). */
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_injected_external_trigger_source.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of
injected group.
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
and software trigger is used instead.
This parameter can be a value of
@ref ADC_injected_external_trigger_source.
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
on injected group can impact the configuration of other channels
previously set. */
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
is discarded.
Caution: this setting impacts the entire injected group. Therefore,
call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the
configuration of other channels previously set. */
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
Note: This parameter can be modified only if there is no
conversion is ongoing (both ADSTART and JADSTART cleared). */
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
Caution: this setting overwrites the previous oversampling
configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no
conversion is ongoing (both ADSTART and JADSTART cleared).*/
} ADC_InjectionConfTypeDef;
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Structure definition of ADC multimode
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
* (both Master and Slave ADCs).
* Both Master and Slave ADCs must be disabled.
*/
typedef struct
@ -182,7 +247,8 @@ typedef struct
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
(one DMA channel for both ADC, DMA of ADC master).
This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
@ -207,23 +273,40 @@ typedef struct
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion
trigger software start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM1 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion
trigger from external peripheral: TIM1 TRGO2. */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion
trigger from external peripheral: TIM1 channel 4 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM2 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion
trigger from external peripheral: TIM2 channel 1 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM3 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion
trigger from external peripheral: TIM3 channel 1 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion
trigger from external peripheral: TIM3 channel 3 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM4 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM6 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion
trigger from external peripheral: TIM8 channel 4 event (capture compare). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM8 TRGO. */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion
trigger from external peripheral: TIM8 TRGO2. */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion
trigger from external peripheral: TIM15 TRGO. */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion
trigger from external peripheral: external interrupt line 15. */
/**
* @}
*/
@ -231,10 +314,14 @@ typedef struct
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger
disabled (SW start)*/
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger
polarity set to rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger
polarity set to falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger
polarity set to both rising and falling edges */
/**
* @}
*/
@ -242,8 +329,8 @@ typedef struct
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */
/**
* @}
*/
@ -251,11 +338,20 @@ typedef struct
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
ADC channel */
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
the offset programmed will be applied (independently of channel mapped
on ADC group regular or group injected) */
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
the offset programmed will be applied (independently of channel mapped
on ADC group regular or group injected) */
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
the offset programmed will be applied (independently of channel mapped
on ADC group regular or group injected) */
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
the offset programmed will be applied (independently of channel mapped
on ADC group regular or group injected) */
/**
* @}
*/
@ -275,21 +371,33 @@ typedef struct
/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
* @{
*/
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled
(ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular
simultaneous */
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined
group regular interleaved */
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group
injected simultaneous */
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group
injected alternate trigger. Works only with external triggers (not internal
SW start) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
group regular simultaneous + group injected simultaneous */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
group regular simultaneous + group injected alternate trigger */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
group regular interleaved + group injected simultaneous */
/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own
DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC,
DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC,
DMA of ADC master) for 8 and 6 bits resolution */
/**
* @}
*/
@ -297,18 +405,30 @@ typedef struct
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two
sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two
sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two
sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two
sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two
sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two
sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two
sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two
sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two
sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two
sampling phases: 10 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two
sampling phases: 11 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two
sampling phases: 12 ADC clock cycles */
/**
* @}
*/
@ -321,9 +441,11 @@ typedef struct
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on
all STM32 devices) */
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on
all STM32 devices) */
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
/**
* @}
*/
@ -386,8 +508,12 @@ typedef struct
/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
* @{
*/
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred
by DFSDM. */
#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred
to DFSDM for post processing. The ADC conversion data format must be 16-bit
signed and right aligned, refer to reference manual.
DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
@ -470,15 +596,16 @@ typedef struct
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
)? \
SET \
: \
RESET \
SET \
: \
RESET \
)
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
#elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
#endif /* (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) ||
defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
/**
* @brief Set the selected injected Channel rank.
@ -486,36 +613,41 @@ typedef struct
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
& ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
* @retval None
*/
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
/**
* @brief Configure ADC discontinuous conversion mode for injected group
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
* @retval None
*/
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
/**
* @brief Configure ADC discontinuous conversion mode for regular group
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
* @retval None
*/
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
/**
* @brief Configure the number of discontinuous conversions for regular group.
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
* @retval None
*/
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
(((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
/**
* @brief Configure the ADC auto delay mode.
@ -557,8 +689,8 @@ typedef struct
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval None
*/
#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\
& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) \
(((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
/**
* @brief Calibration factor in differential mode to be retrieved from calibration register.
@ -661,12 +793,15 @@ typedef struct
* @brief Set handle instance of the ADC slave associated to the ADC master.
* @param __HANDLE_MASTER__ ADC master handle.
* @param __HANDLE_SLAVE__ ADC slave handle.
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is
* set to NULL.
* @retval None
*/
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
( (((__HANDLE_MASTER__)->Instance == ADC1)) ? \
((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) ||
defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
/**
@ -681,7 +816,11 @@ typedef struct
/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\
|| (((__HANDLE__)->Instance) == ADC3))
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
/**
* @brief Verify the ADC instance connected to the battery voltage VBAT.
@ -695,7 +834,11 @@ typedef struct
/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\
|| (((__HANDLE__)->Instance) == ADC3))
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
/**
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
@ -708,7 +851,8 @@ typedef struct
/**
* @brief Verify the length of scheduled injected conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
* or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
@ -892,7 +1036,10 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
#endif /* (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
#endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) ||
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) ||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
/**
* @brief Verify the ADC channel setting in differential mode.
@ -949,7 +1096,11 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) )))
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
/**
* @brief Verify the ADC single-ended input or differential mode setting.
@ -1071,13 +1222,13 @@ typedef struct
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
*/
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
/**
* @brief Verify the ADC conversion (regular or injected or both).
@ -1191,7 +1342,7 @@ typedef struct
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
@ -1208,11 +1359,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
#endif /* ADC_MULTIMODE_SUPPORT */
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
@ -1222,11 +1373,11 @@ void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *h
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
/* ADC group regular conversions stop */
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* ADC_MULTIMODE_SUPPORT */
/**
@ -1238,10 +1389,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
ADC_InjectionConfTypeDef *sConfigInjected);
const ADC_InjectionConfTypeDef *pConfigInjected);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
const ADC_MultiModeTypeDef *pMultimode);
#endif /* ADC_MULTIMODE_SUPPORT */
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);

4
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h
View File

@ -209,7 +209,11 @@ typedef struct
/**
* @brief CAN handle Structure definition
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */

2
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
View File

@ -296,6 +296,8 @@ void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**

342
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h Normal file
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@ -0,0 +1,342 @@
/**
******************************************************************************
* @file stm32l4xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CRC_H
#define STM32L4xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal,
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
into 0x22CC4488 */
} CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
(8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
error must occur if InputBufferFormat is not one of the three values listed
above */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32l4xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_CRC_H */

150
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h Normal file
View File

@ -0,0 +1,150 @@
/**
******************************************************************************
* @file stm32l4xx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CRC_EX_H
#define STM32L4xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_CRC_EX_H */

2
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
View File

@ -54,7 +54,9 @@ typedef enum
/* Exported macros -----------------------------------------------------------*/
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU

24
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
View File

@ -21,7 +21,7 @@
#define STM32L4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -82,7 +82,7 @@ typedef enum
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
@ -91,7 +91,7 @@ typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
} HAL_DMA_LevelCompleteTypeDef;
/**
@ -104,7 +104,7 @@ typedef enum
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
@ -121,13 +121,13 @@ typedef struct __DMA_HandleTypeDef
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
@ -150,7 +150,7 @@ typedef struct __DMA_HandleTypeDef
#endif /* DMAMUX1 */
}DMA_HandleTypeDef;
} DMA_HandleTypeDef;
/**
* @}
*/
@ -753,7 +753,7 @@ typedef struct __DMA_HandleTypeDef
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
@ -762,13 +762,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**

14
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
View File

@ -69,7 +69,7 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxSyncConfigTypeDef;
} HAL_DMA_MuxSyncConfigTypeDef;
/**
@ -77,7 +77,7 @@ typedef struct
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
@ -86,7 +86,7 @@ typedef struct
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
@ -211,10 +211,10 @@ typedef struct
*/
/* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/

1
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
View File

@ -783,6 +783,7 @@
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */

13
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
View File

@ -118,8 +118,6 @@ typedef enum
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

2
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
View File

@ -4441,7 +4441,7 @@ typedef struct
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source

46
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
View File

@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0U)
} while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
#define SPI_RESET_CRC(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
} while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
/**
* @}
*/

2
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
View File

@ -48,7 +48,7 @@ extern "C" {
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
/**
* @}
*/

2390
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
View File

File diff suppressed because it is too large Load Diff

439
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
View File

@ -1,439 +0,0 @@
/**
******************************************************************************
* @file stm32l4xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_TIM_EX_H
#define STM32L4xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct
{
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#if defined (ADC3)
#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#endif /* ADC3 */
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#endif /* COMP2 */
#if defined (USB_OTG_FS)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */
#else
#if defined(STM32L471xx)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */
#else
#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
#endif /* STM32L471xx */
#endif /* USB_OTG_FS */
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */
#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#endif /* COMP2 */
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#endif /* COMP2 */
#if defined (TIM3)
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */
#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
#endif /* TIM3 */
#if defined (TIM8)
#if defined(ADC2) && defined(ADC3)
#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#endif /* ADC2 && ADC3 */
#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */
#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */
#endif /* TIM8 */
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */
#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */
#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */
#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#if defined (TIM3)
#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM3 */
#if defined (TIM4)
#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM4 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */
#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */
#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
#if defined (TIM16_OR1_TI1_RMP_2)
#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */
#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
#endif /* TIM16_OR1_TI1_RMP_2 */
#if defined (TIM17)
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */
#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */
#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
#endif /* TIM17 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#if defined (DFSDM1_Channel0)
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#endif /* DFSDM1_Channel0 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined (DFSDM1_Channel0)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#endif /* DFSDM1_Channel0 */
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_TIM_EX_H */

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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h
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/**
******************************************************************************
* @file stm32l4xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_CORTEX_H
#define STM32L4xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M4 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC24 for Cortex-M4
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_CORTEX_H */

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/**
******************************************************************************
* @file stm32l4xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_CRC_H
#define STM32L4xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
/**
* @}
*/
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
*/
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
/**
* @}
*/
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
* @{
*/
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
* @{
*/
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @brief Configure size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
{
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
}
/**
* @brief Return size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
/**
* @brief Configure the reversal of the bit order of the input data
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
}
/**
* @brief Return type of reversal for input data bit order
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
}
/**
* @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
/**
* @brief Initialize the Programmable initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to write the correct value
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
* @rmtoll INIT INIT LL_CRC_SetInitialData
* @param CRCx CRC Instance
* @param InitCrc Value to be programmed in Programmable initial CRC value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
{
WRITE_REG(CRCx->INIT, InitCrc);
}
/**
* @brief Return current Initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to read the correct value
* @rmtoll INIT INIT LL_CRC_GetInitialData
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
* @param CRCx CRC Instance
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
{
WRITE_REG(CRCx->POL, PolynomCoef);
}
/**
* @brief Return current Programmable polynomial value
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Write given 16-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData16
* @param CRCx CRC Instance
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
/**
* @brief Write given 8-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData8
* @param CRCx CRC Instance
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
{
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location.
* @note Refer to the Reference Manual to get the authorized data length in bits.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location.
* @note Refer to the Reference Manual to get the authorized data length in bits.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
#if (CRC_IDR_IDR == 0x0FFU)
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
#else
WRITE_REG(CRCx->IDR, InData);
#endif
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_CRC_H */

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/**
******************************************************************************
* @file stm32l4xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_CRS_H
#define STM32L4xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds
* to the middle of the trimming interval.
* The trimming step is around 67 kHz between two consecutive TRIM steps.
* A higher TRIM value corresponds to a higher output frequency
*/
#if defined (STM32L412xx) || defined (STM32L422xx)
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U)
#else
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U)
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_CRS_H */

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/**
******************************************************************************
* @file stm32l4xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_IWDG_H
#define STM32L4xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
/**
* @brief Specify high limit of the window value to be compared to the down-counter.
* @rmtoll WINR WIN LL_IWDG_SetWindow
* @param IWDGx IWDG Instance
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
{
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
}
/**
* @brief Get the high limit of the window value specified.
* @rmtoll WINR WIN LL_IWDG_GetWindow
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->WINR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Window Value Update is set or not
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady\n
* SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_IWDG_H */

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@ -0,0 +1,329 @@
/**
******************************************************************************
* @file stm32l4xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_UTILS_H
#define STM32L4xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLR; /*!< Division for the main system clock.
This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U /*!< BGA132 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_CSP115 0x00000010U /*!< UFBGA169 or WLCSP115 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */
#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_UTILS_H */

5
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
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@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
@ -381,7 +381,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
* @retval tick period in Hz
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{

303
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
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@ -220,11 +220,11 @@
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_ADC_RegisterCallback()
Use Functions @ref HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
Function HAL_ADC_RegisterCallback() allows to register following callbacks:
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
@ -240,11 +240,11 @@
and a pointer to the user callback function.
[..]
Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
@ -260,27 +260,27 @@
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
or HAL_ADC_Init() function.
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
or @ref HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@ -312,10 +312,11 @@
* @{
*/
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can
be updated when no regular conversion is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
@ -393,11 +394,10 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpCFGR;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
/* Check ADC handle */
if (hadc == NULL)
@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
#endif
#endif /* DFSDM */
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@ -516,10 +516,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
)
{
/* Set ADC state */
@ -566,15 +566,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
}
/* Enable external trigger if trigger selection is different of software */
@ -584,13 +584,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
| hadc->Init.ExternalTrigConvEdge
);
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
| hadc->Init.ExternalTrigConvEdge
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@ -598,17 +598,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
if (hadc->Init.OversamplingMode == ENABLE)
{
@ -1207,7 +1206,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1241,7 +1240,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
@ -1310,7 +1309,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -1398,7 +1397,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1458,7 +1457,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
{
tmp_Flag_End = (ADC_FLAG_EOC);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Get tick count */
@ -1531,7 +1530,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
#else
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_EOS)
@ -1559,9 +1558,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
* @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
* all STM32 series)
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
* all STM32 series)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
* all STM32 series)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
* @param Timeout Timeout value in millisecond.
@ -1728,7 +1730,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1762,7 +1764,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
@ -1904,7 +1906,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -1987,7 +1989,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2031,7 +2033,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
@ -2100,7 +2102,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
/* Process unlocked */
__HAL_UNLOCK(hadc);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
@ -2209,7 +2211,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2237,7 +2239,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2301,7 +2303,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Carry on if continuous mode is disabled */
if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
@ -2391,7 +2393,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Disable interruption if no further conversion upcoming by injected */
/* external trigger or by automatic injected conversion with regular */
@ -2537,7 +2539,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
}
}
else
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
{
/* Multimode not set or feature not available or ADC independent */
if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
@ -2693,10 +2695,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* The setting of these parameters is conditioned to ADC state:
* Refer to comments of structure "ADC_ChannelConfTypeDef".
* @param hadc ADC handle
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
@ -2707,24 +2709,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
ignored (considered as reset) */
assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
/* Verification of channel number */
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
}
else
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
@ -2738,37 +2740,40 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
#if !defined (USE_FULL_ASSERT)
uint32_t config_rank = pConfig->Rank;
/* Correspondence for compatibility with legacy definition of */
/* sequencer ranks in direct number format. This correspondence can */
/* be done only on ranks 1 to 5 due to literal values. */
/* Note: Sequencer ranks in direct number format are no more used */
/* and are detected by activating USE_FULL_ASSERT feature. */
if (sConfig->Rank <= 5U)
if (pConfig->Rank <= 5U)
{
switch (sConfig->Rank)
switch (pConfig->Rank)
{
case 2U:
sConfig->Rank = ADC_REGULAR_RANK_2;
config_rank = ADC_REGULAR_RANK_2;
break;
case 3U:
sConfig->Rank = ADC_REGULAR_RANK_3;
config_rank = ADC_REGULAR_RANK_3;
break;
case 4U:
sConfig->Rank = ADC_REGULAR_RANK_4;
config_rank = ADC_REGULAR_RANK_4;
break;
case 5U:
sConfig->Rank = ADC_REGULAR_RANK_5;
config_rank = ADC_REGULAR_RANK_5;
break;
/* case 1U */
default:
sConfig->Rank = ADC_REGULAR_RANK_1;
config_rank = ADC_REGULAR_RANK_1;
break;
}
}
#endif
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
LL_ADC_REG_SetSequencerRanks(hadc->Instance, config_rank, pConfig->Channel);
#else
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
#endif/* USE_FULL_ASSERT */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@ -2783,10 +2788,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
{
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
@ -2794,26 +2799,26 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
#endif
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
#endif /* ADC_SMPR1_SMPPLUS */
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
}
else
@ -2821,22 +2826,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@ -2849,16 +2854,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
/* Configuration of differential mode */
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
sConfig->SamplingTime);
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
}
}
@ -2869,13 +2876,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
@ -2895,7 +2902,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
}
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
@ -2903,7 +2911,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
@ -2950,28 +2958,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
* @note On this STM32 series, analog watchdog thresholds cannot be modified
* while ADC conversion is on going.
* @param hadc ADC handle
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
uint32_t tmp_awd_high_threshold_shifted;
uint32_t tmp_awd_low_threshold_shifted;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
{
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
}
/* Verify thresholds range */
@ -2980,14 +2988,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Case of oversampling enabled: depending on ratio and shift configuration,
analog watchdog thresholds can be higher than ADC resolution.
Verify if thresholds are within maximum thresholds range. */
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
}
else
{
/* Verify if thresholds are within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
}
/* Process locked */
@ -3005,26 +3013,29 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
)
{
/* Analog watchdog configuration */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
{
/* Configuration of analog watchdog: */
/* - Set the analog watchdog enable mode: one or overall group of */
/* channels, on groups regular and-or injected. */
switch (AnalogWDGConfig->WatchdogMode)
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
break;
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
@ -3047,12 +3058,12 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Shift the offset in function of the selected ADC resolution: */
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
/* are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
tmpAWDLowThresholdShifted);
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
@ -3064,7 +3075,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD1(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD1(hadc->Instance);
}
@ -3076,44 +3087,47 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
switch (AnalogWDGConfig->WatchdogMode)
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
SET_BIT(hadc->Instance->AWD2CR,
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
else
{
SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
SET_BIT(hadc->Instance->AWD3CR,
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
break;
}
/* Shift the thresholds in function of the selected ADC resolution */
/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
tmpAWDLowThresholdShifted);
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Update state, clear previous result related to AWD2 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
@ -3125,7 +3139,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD2(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD2(hadc->Instance);
}
@ -3134,7 +3148,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_DisableIT_AWD2(hadc->Instance);
}
}
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
/* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
else
{
/* Update state, clear previous result related to AWD3 */
@ -3147,7 +3161,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_ClearFlag_AWD3(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (AnalogWDGConfig->ITMode == ENABLE)
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD3(hadc->Instance);
}
@ -3207,7 +3221,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
* @param hadc ADC handle
* @retval ADC handle state (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -3221,7 +3235,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle
* @retval ADC error code (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -3410,7 +3424,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
{
/* Delay for temperature sensor buffer stabilization time */
/* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
@ -3423,7 +3438,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}

319
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
View File

@ -50,9 +50,10 @@
* @{
*/
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
be updated anytime once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: maximum ratio between ADC */
@ -189,7 +190,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -272,7 +273,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
uint32_t tmp_config_injected_queue;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -338,7 +339,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@ -385,7 +386,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
/* Start ADC group injected conversion */
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
@ -473,14 +474,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t tmp_Flag_End;
uint32_t tmp_flag_end;
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -488,18 +489,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
/* If end of sequence selected */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_Flag_End = ADC_FLAG_JEOS;
tmp_flag_end = ADC_FLAG_JEOS;
}
else /* end of conversion selected */
{
tmp_Flag_End = ADC_FLAG_JEOC;
tmp_flag_end = ADC_FLAG_JEOC;
}
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait until End of Conversion or Sequence flag is raised */
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
@ -507,7 +508,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@ -543,7 +544,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
@ -579,7 +580,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
}
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_JEOS)
if (tmp_flag_end == ADC_FLAG_JEOS)
{
/* Clear end of sequence JEOS flag of injected group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
@ -617,7 +618,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
uint32_t tmp_config_injected_queue;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -683,7 +684,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@ -751,7 +752,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
/* Start ADC group injected conversion */
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
@ -854,7 +855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmphadcSlave;
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
@ -873,13 +874,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -895,7 +896,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
tmp_hal_status = ADC_Enable(&tmphadcSlave);
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
/* Start multimode conversion of ADCs pair */
@ -974,9 +975,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t tickstart;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
HAL_StatusTypeDef tmphadcSlave_disable_status;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
HAL_StatusTypeDef tmp_hadc_slave_disable_status;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -984,7 +985,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* 1. Stop potential multimode conversion on going, on regular and injected groups */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
@ -992,13 +992,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1015,17 +1015,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
/* Update ADC state machine to error */
@ -1038,7 +1038,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
}
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@ -1062,9 +1062,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* memory a potential failing status. */
if (tmp_hal_status == HAL_OK)
{
tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
if ((ADC_Disable(hadc) == HAL_OK) &&
(tmphadcSlave_disable_status == HAL_OK))
(tmp_hadc_slave_disable_status == HAL_OK))
{
tmp_hal_status = HAL_OK;
}
@ -1073,7 +1073,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
/* In case of error, attempt to disable ADC master and slave without status assert */
(void) ADC_Disable(hadc);
(void) ADC_Disable(&tmphadcSlave);
(void) ADC_Disable(&tmp_hadc_slave);
}
/* Set ADC state (ADC master) */
@ -1094,7 +1094,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmpADC_Common;
@ -1127,7 +1127,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
* both flags JEOC and EOS are raised.
* Flag JEOS must not be cleared by this function because
* it would not be compliant with low power features
* (feature low power auto-wait, not available on all STM32 families).
* (feature low power auto-wait, not available on all STM32 series).
* To clear this flag, either use function:
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
@ -1141,7 +1141,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
* @retval ADC group injected conversion data
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
uint32_t tmp_jdr;
@ -1451,7 +1451,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
* conversion is on-going.
* @note Multimode is kept enabled after this function. Multimode DMA bits
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
* multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
@ -1467,8 +1468,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t tickstart;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -1487,13 +1488,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1510,17 +1511,17 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmphadcSlave_conversion_on_going == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
/* Update ADC state machine to error */
@ -1533,7 +1534,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
}
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@ -1563,9 +1564,9 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
tmp_hal_status = ADC_Disable(hadc);
if (tmp_hal_status == HAL_OK)
{
if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
{
tmp_hal_status = ADC_Disable(&tmphadcSlave);
tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
}
}
}
@ -1644,59 +1645,62 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
* start once the 1st context is set, that is after the first three
* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
* @param hadc ADC handle
* @param sConfigInjected Structure of ADC injected group and ADC channel for
* @param pConfigInjected Structure of ADC injected group and ADC channel for
* injected group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
const ADC_InjectionConfTypeDef *pConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_offset_shifted;
uint32_t tmp_config_internal_channel;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0;
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
uint32_t tmp_jsqr_context_queue_being_built = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
{
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
}
/* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
ignored (considered as reset) */
assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
&& (pConfigInjected->InjecOversamplingMode == ENABLE)));
/* JDISCEN and JAUTO bits can't be set at the same time */
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
&& (pConfigInjected->AutoInjectedConv == ENABLE)));
/* DISCEN and JAUTO bits can't be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
/* Verification of channel number */
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
}
else
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
}
/* Process locked */
@ -1724,7 +1728,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* by software for alignment over all STM32 devices. */
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
(sConfigInjected->InjectedNbrOfConversion == 1U))
(pConfigInjected->InjectedNbrOfConversion == 1U))
{
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer: fixed to 1st rank */
@ -1733,28 +1737,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* - external trigger polarity */
/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
{
/* Enable external trigger if trigger selection is different of */
/* software start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
}
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
/* For debug and informative reasons, hadc handle saves JSQR setting */
hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
}
}
@ -1774,7 +1778,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
/* Initialize number of channels that will be configured on the context */
/* being built */
hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
call, this context will be written in JSQR register at the last call.
At this point, the context is merely reset */
@ -1790,16 +1794,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
}
}
@ -1807,18 +1811,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* 2. Continue setting of context under definition with parameter */
/* related to each channel: channel rank sequence */
/* Clear the old JSQx bits for the selected rank */
tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
/* Set the JSQx bits for the selected rank */
tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
/* Decrease channel count */
hadc->InjectionConfig.ChannelCount--;
/* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
/* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
call, aggregate the setting to those already built during the previous
HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
/* 4. End of context setting: if this is the last channel set, then write context
into register JSQR and make it enter into queue */
@ -1838,12 +1842,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* If auto-injected mode is disabled: no constraint */
if (sConfigInjected->AutoInjectedConv == DISABLE)
if (pConfigInjected->AutoInjectedConv == DISABLE)
{
MODIFY_REG(hadc->Instance->CFGR,
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
}
/* If auto-injected mode is enabled: Injected discontinuous setting is */
/* discarded. */
@ -1851,7 +1855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
MODIFY_REG(hadc->Instance->CFGR,
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
}
}
@ -1872,10 +1876,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
/* If injected group external triggers are disabled (set to injected */
/* software start): no constraint */
if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|| (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|| (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
{
if (sConfigInjected->AutoInjectedConv == ENABLE)
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
}
@ -1888,7 +1892,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* due to injected group external triggers enabled, error is reported. */
else
{
if (sConfigInjected->AutoInjectedConv == ENABLE)
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -1901,13 +1905,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
}
}
if (sConfigInjected->InjecOversamplingMode == ENABLE)
if (pConfigInjected->InjecOversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
== (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
/* Configuration of Injected Oversampler: */
/* - Oversampling Ratio */
@ -1919,8 +1924,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE |
sConfigInjected->InjecOversampling.Ratio |
sConfigInjected->InjecOversampling.RightBitShift
pConfigInjected->InjecOversampling.Ratio |
pConfigInjected->InjecOversampling.RightBitShift
);
}
else
@ -1931,10 +1936,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
@ -1942,27 +1947,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
pConfigInjected->InjectedSamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
#endif
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
pConfigInjected->InjectedSamplingTime);
#endif /* ADC_SMPR1_SMPPLUS */
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
tmpOffsetShifted);
LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
tmp_offset_shifted);
}
else
@ -1970,22 +1977,22 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@ -1999,16 +2006,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
/* Configuration of differential mode */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+ 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
(__LL_ADC_CHANNEL_TO_DECIMAL_NB(
(uint32_t)pConfigInjected->InjectedChannel)
+ 1UL) & 0x1FUL)),
pConfigInjected->InjectedSamplingTime);
}
}
@ -2019,13 +2029,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
@ -2038,14 +2048,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
* (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
}
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
@ -2054,7 +2065,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
@ -2090,35 +2101,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
* @note To move back configuration from multimode to single mode, ADC must
* be reset (using function HAL_ADC_Init() ).
* @param hadc Master ADC handle
* @param multimode Structure of ADC multimode configuration
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_ADC_MULTIMODE(multimode->Mode));
if (multimode->Mode != ADC_MODE_INDEPENDENT)
assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -2134,9 +2145,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
&& (tmphadcSlave_conversion_on_going == 0UL))
&& (tmp_hadc_slave_conversion_on_going == 0UL))
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
@ -2144,10 +2155,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (multimode->Mode != ADC_MODE_INDEPENDENT)
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
multimode->DMAAccessMode |
pMultimode->DMAAccessMode |
ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
/* Parameters that can be updated only when ADC is disabled: */
@ -2165,8 +2176,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
MODIFY_REG(tmpADC_Common->CCR,
ADC_CCR_DUAL |
ADC_CCR_DELAY,
multimode->Mode |
multimode->TwoSamplingDelay
pMultimode->Mode |
pMultimode->TwoSamplingDelay
);
}
}

51
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
View File

@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function open-drain
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif
#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
#endif
#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
if (count > timeout)
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@ -1524,7 +1523,15 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
@ -1600,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
@ -2066,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
@ -2316,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####

80
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
View File

@ -451,6 +451,37 @@ void HAL_MPU_Disable(void)
MPU->CTRL = 0;
}
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
@ -463,38 +494,31 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */

522
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c Normal file
View File

@ -0,0 +1,522 @@
/**
******************************************************************************
* @file stm32l4xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @{
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
#if defined(CRC_IDR32BITSLENGTH_SUPPORT)
/* Reset IDR register content */
__HAL_CRC_SET_IDR(hcrc, 0);
#else
/* Reset IDR register content */
CLEAR_REG(hcrc->Instance->IDR);
#endif /* CRC_IDR32BITSLENGTH_SUPPORT */
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CRC_Private_Functions
* @{
*/
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
uint16_t data;
__IO uint16_t *pReg;
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the peripheral */
for (i = 0U; i < (BufferLength / 4U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
(uint32_t)pBuffer[(4U * i) + 3U];
}
/* last bytes specific handling */
if ((BufferLength % 4U) != 0U)
{
if ((BufferLength % 4U) == 1U)
{
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
}
if ((BufferLength % 4U) == 2U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
}
if ((BufferLength % 4U) == 3U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
}
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
__IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the peripheral */
for (i = 0U; i < (BufferLength / 2U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
if ((BufferLength % 2U) != 0U)
{
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = pBuffer[2U * i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

230
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c Normal file
View File

@ -0,0 +1,230 @@
/**
******************************************************************************
* @file stm32l4xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the generating polynomial
(+) Configure the input data inversion
(+) Configure the output data inversion
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* Ensure that the generating polynomial is odd */
if ((Pol & (uint32_t)(0x1U)) == 0U)
{
status = HAL_ERROR;
}
else
{
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
}
if (status == HAL_OK)
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */
return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
* @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
* @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

48
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
View File

@ -171,14 +171,14 @@
A DMA1 request can be generated when an external trigger (but not a software trigger)
occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
DMA requests are mapped as following:
(#) When DMAMUX is NOT present:
(#) When DMAMUX is NOT present:
DMA1 requests are mapped as following:
(+) DAC channel1 mapped on DMA1 request 6 / channel3
(+) DAC channel2 mapped on DMA1 request 5 / channel4
DMA2 requests are mapped as following:
(+) DAC channel1 mapped on DMA2 request 3 / channel4
(+) DAC channel2 mapped on DMA2 request 3 / channel5
(#) When DMAMUX is present:
(#) When DMAMUX is present:
(+) DAC channel1 mapped on DMA1/DMA2 request 6 (can be any DMA channel)
(+) DAC channel2 mapped on DMA1/DMA2 request 7 (can be any DMA channel)
@ -264,7 +264,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@ -279,9 +279,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@ -296,7 +296,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
@ -405,7 +405,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
/* STM32L4P5xx STM32L4Q5xx */
/* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
if (hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
@ -1249,13 +1249,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* New check to avoid false timeout detection in case of preemption */
if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1);
@ -1271,13 +1275,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* New check to avoid false timeout detection in case of preemption */
if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1U);
@ -1437,7 +1445,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@ -1546,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* DAC Callback is redirected to the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:

13
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
View File

@ -425,10 +425,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
/* OPAMP_CSR_OUTCAL is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* Check trimming value below maximum */
if (trimmingvalue < 0x1FU)
{
/* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
}
/* Disable the selected DAC channel calibration */

186
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
View File

@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
uint32_t tmp;
/* Check the DMA handle allocation */
if(hdma == NULL)
if (hdma == NULL)
{
return HAL_ERROR;
}
@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -249,7 +249,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
#if !defined (DMAMUX1)
/* Set request selection */
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
{
/* Write to DMA channel selection register */
if (DMA1 == hdma->DmaBaseAddress)
@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA1 Channelx */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
}
else /* DMA2 */
{
@ -266,13 +266,13 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA2 Channelx */
DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
}
}
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -296,7 +296,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if (NULL == hdma )
if (NULL == hdma)
{
return HAL_ERROR;
}
@ -341,8 +341,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
}
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */
#if defined(DMAMUX1)
@ -358,7 +358,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Reset Request generator parameters if any */
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback )
if (NULL != hdma->XferHalfCpltCallback)
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
@ -509,13 +509,13 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
#ifdef DMAMUX1
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral state */
if(hdma->State != HAL_DMA_STATE_BUSY)
if (hdma->State != HAL_DMA_STATE_BUSY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
if (hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
uint32_t temp;
uint32_t tickstart;
if(HAL_DMA_STATE_BUSY != hdma->State)
if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -708,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Get tick */
tickstart = HAL_GetTick();
while((hdma->DmaBaseAddress->ISR & temp) == 0U)
while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
{
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
@ -729,9 +729,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@ -749,10 +749,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
#if defined(DMAMUX1)
/*Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
@ -776,10 +776,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
}
#endif /* DMAMUX1 */
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
/* Process unlocked */
__HAL_UNLOCK(hdma);
@ -811,29 +811,29 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
if (hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
/* Disable the transfer complete and error interrupt */
@ -849,7 +849,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
if (hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
@ -895,40 +895,40 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to
* @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
default:
status = HAL_ERROR;
break;
}
}
else
@ -954,39 +954,39 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
default:
status = HAL_ERROR;
break;
default:
status = HAL_ERROR;
break;
}
}
else
@ -1072,7 +1072,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if (hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
@ -1086,7 +1086,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->CNDTR = DataLength;
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;

64
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
View File

@ -114,17 +114,17 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY)
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID), \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process UnLocked */
__HAL_UNLOCK(hdma);
@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -160,24 +160,24 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -194,18 +194,18 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -222,7 +222,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Disable the request generator*/
@ -245,7 +245,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
@ -256,17 +256,17 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL)
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if(hdma->DMAmuxRequestGen != 0)
if (hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
@ -277,7 +277,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL)
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);

12
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
View File

@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@ -346,7 +346,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@ -538,6 +538,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@ -572,6 +575,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));

8
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
View File

@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)

874
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

3
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
View File

@ -126,7 +126,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}

8
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
View File

@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void)
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void)
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void)
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@ -264,7 +264,7 @@ void HAL_PWR_DisableBkUpAccess(void)
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,

4
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
View File

@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
/**
* @brief Enable battery charging.
* When VDD is present, charge the external battery on VBAT thru an internal resistor.
* When VDD is present, charge the external battery on VBAT through an internal resistor.
* @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
/* Configure EXTI 35 to 38 interrupts if so required:
scan thru PVMType to detect which PVMx is set and
scan through PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{

10
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
View File

@ -398,6 +398,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@ -1318,7 +1320,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
@ -1852,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
else
{
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
/* nothing to do */
}
}
#endif
}

6
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
View File

@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret;
}
}
else
{
/* nothing to do */
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and sychronization frequencies values
directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration

484
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
View File

File diff suppressed because it is too large Load Diff

2
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
View File

@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;

7896
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

2841
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
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Makefile
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##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Tue Sep 27 08:33:11 CEST 2022]
##########################################################################################################################
# ------------------------------------------------
# Generic Makefile (based on gcc)
#
# ChangeLog :
# 2017-02-10 - Several enhancements + project update mode
# 2015-07-22 - first version
# ------------------------------------------------
######################################
# target
######################################
TARGET = PeltierControllerV3
######################################
# building variables
######################################
# debug build?
DEBUG = 1
# optimization
OPT = -Og
#######################################
# paths
#######################################
# Build path
BUILD_DIR = build
######################################
# source
######################################
# C sources
C_SOURCES = \
Core/Src/main.c \
Core/Src/freertos.c \
Core/Src/stm32l4xx_it.c \
Core/Src/stm32l4xx_hal_msp.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \
Core/Src/system_stm32l4xx.c \
Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
Middlewares/Third_Party/FreeRTOS/Source/list.c \
Middlewares/Third_Party/FreeRTOS/Source/queue.c \
Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
Middlewares/Third_Party/FreeRTOS/Source/timers.c \
Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \
Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \
Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
# ASM sources
ASM_SOURCES = \
startup_stm32l432xx.s
#######################################
# binaries
#######################################
PREFIX = arm-none-eabi-
# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
# either it can be added to the PATH environment variable.
ifdef GCC_PATH
CC = $(GCC_PATH)/$(PREFIX)gcc
AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
CP = $(GCC_PATH)/$(PREFIX)objcopy
SZ = $(GCC_PATH)/$(PREFIX)size
else
CC = $(PREFIX)gcc
AS = $(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy
SZ = $(PREFIX)size
endif
HEX = $(CP) -O ihex
BIN = $(CP) -O binary -S
#######################################
# CFLAGS
#######################################
# cpu
CPU = -mcpu=cortex-m4
# fpu
FPU = -mfpu=fpv4-sp-d16
# float-abi
FLOAT-ABI = -mfloat-abi=hard
# mcu
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
# macros for gcc
# AS defines
AS_DEFS =
# C defines
C_DEFS = \
-DUSE_HAL_DRIVER \
-DSTM32L432xx
# AS includes
AS_INCLUDES = \
-ICore\Inc
# C includes
C_INCLUDES = \
-ICore/Inc \
-IDrivers/STM32L4xx_HAL_Driver/Inc \
-IDrivers/STM32L4xx_HAL_Driver/Inc/Legacy \
-IMiddlewares/Third_Party/FreeRTOS/Source/include \
-IMiddlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \
-IMiddlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \
-IDrivers/CMSIS/Device/ST/STM32L4xx/Include \
-IDrivers/CMSIS/Include
# compile gcc flags
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2
endif
# Generate dependency information
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
#######################################
# LDFLAGS
#######################################
# link script
LDSCRIPT = STM32L432KBUx_FLASH.ld
# libraries
LIBS = -lc -lm -lnosys
LIBDIR =
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
# default action: build all
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
#######################################
# build the application
#######################################
# list of objects
OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
vpath %.c $(sort $(dir $(C_SOURCES)))
# list of ASM program objects
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
vpath %.s $(sort $(dir $(ASM_SOURCES)))
$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
$(AS) -c $(CFLAGS) $< -o $@
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
$(CC) $(OBJECTS) $(LDFLAGS) -o $@
$(SZ) $@
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(HEX) $< $@
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(BIN) $< $@
$(BUILD_DIR):
mkdir $@
#######################################
# size
#######################################
size:
"C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\12.2 mpacbti-bet1\bin\arm-none-eabi-size.exe" $(BUILD_DIR)/$(TARGET).elf
#######################################
# clean up
#######################################
clean:
-rm -fR $(BUILD_DIR)
#######################################
# dependencies
#######################################
-include $(wildcard $(BUILD_DIR)/*.d)
# *** EOF ***

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Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c Normal file
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Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h Normal file
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/**
******************************************************************************
* @file EEPROM_Emul/Core/eeprom_emul.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the EEPROM
* emulation firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __EEPROM_EMUL_H
#define __EEPROM_EMUL_H
/* Includes ------------------------------------------------------------------*/
#include "eeprom_emul_conf.h"
#include "eeprom_emul_types.h"
#include "flash_interface.h"
/** @addtogroup EEPROM_Emulation
* @{
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup EEPROM_Private_Constants EEPROM Private Constants
* @{
*/
/** @defgroup Private_Other_Constants Private Other Constants
* @{
*/
/* Page definitions */
#define PAGE_SIZE FLASH_PAGE_SIZE /*!< Page size */
#define PAGE_HEADER_SIZE EE_ELEMENT_SIZE * 4U /*!< Page Header is 4 elements to save page state */
#define NB_MAX_ELEMENTS_BY_PAGE ((PAGE_SIZE - PAGE_HEADER_SIZE) / EE_ELEMENT_SIZE) /*!< Max number of elements by page */
#define PAGES_NUMBER (((((NB_OF_VARIABLES + NB_MAX_ELEMENTS_BY_PAGE) / NB_MAX_ELEMENTS_BY_PAGE) * 2U) * CYCLES_NUMBER) + GUARD_PAGES_NUMBER)
/*!< Number of consecutives pages used by the application */
#define NB_MAX_WRITTEN_ELEMENTS ((NB_MAX_ELEMENTS_BY_PAGE * PAGES_NUMBER) / 2U) /*!< Max number of elements written before triggering pages transfer */
#define START_PAGE PAGE(START_PAGE_ADDRESS) /*!< Page index of the 1st page used for EEPROM emul, in the bank */
#define END_EEPROM_ADDRESS (START_PAGE_ADDRESS + (PAGES_NUMBER * FLASH_PAGE_SIZE) - 1) /*!< Last address of EEPROM emulation flash pages */
/* No page define */
#define EE_NO_PAGE_FOUND ((uint32_t)0xFFFFFFFFU)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup EEPROM_Private_Macros EEPROM Private Macros
* @{
*/
/** @defgroup Macros_Pages Macros to manipulate pages
* @{
*/
/* Macros to manipulate pages */
#ifdef SECURE_FEATURES
#define PAGE_ADDRESS(__PAGE__) (uint32_t)(FLASH_BASE_NS + (__PAGE__) * PAGE_SIZE + ((START_PAGE_ADDRESS - FLASH_BASE_NS) / BANK_SIZE) * BANK_SIZE) /*!< Get page address from page index */
#define PAGE(__ADDRESS__) (uint32_t)((((__ADDRESS__) - FLASH_BASE_NS) % BANK_SIZE) / FLASH_PAGE_SIZE) /*!< Get page index from page address */
#else
#define PAGE_ADDRESS(__PAGE__) (uint32_t)(FLASH_BASE + (__PAGE__) * PAGE_SIZE + ((START_PAGE_ADDRESS - FLASH_BASE) / BANK_SIZE) * BANK_SIZE) /*!< Get page address from page index */
#define PAGE(__ADDRESS__) (uint32_t)((((__ADDRESS__) - FLASH_BASE) % BANK_SIZE) / FLASH_PAGE_SIZE) /*!< Get page index from page address */
#endif
#define PREVIOUS_PAGE(__PAGE__) (uint32_t)((((__PAGE__) - START_PAGE - 1U + PAGES_NUMBER) % PAGES_NUMBER) + START_PAGE) /*!< Get page index of previous page, among circular page list */
#define FOLLOWING_PAGE(__PAGE__) (uint32_t)((((__PAGE__) - START_PAGE + 1U) % PAGES_NUMBER) + START_PAGE) /*!< Get page index of following page, among circular page list */
/**
* @}
*/
/** @defgroup Macros_Elements Macros to manipulate elements
* @{
*/
/* Macros to manipulate elements */
#define EE_VIRTUALADDRESS_VALUE(__ELEMENT__) (EE_VIRTUALADDRESS_TYPE)((__ELEMENT__) & EE_MASK_VIRTUALADDRESS) /*!< Get virtual address value from element value */
#define EE_DATA_VALUE(__ELEMENT__) (EE_DATA_TYPE)(((__ELEMENT__) & EE_MASK_DATA) >> EE_DATA_SHIFT) /*!< Get Data value from element value */
#define EE_CRC_VALUE(__ELEMENT__) (EE_CRC_TYPE)(((__ELEMENT__) & EE_MASK_CRC) >> EE_CRC_SHIFT) /*!< Get Crc value from element value */
#define EE_ELEMENT_VALUE(__VIRTADDR__,__DATA__,__CRC__) (((EE_ELEMENT_TYPE)(__DATA__) << EE_DATA_SHIFT) | (__CRC__) << EE_CRC_SHIFT | (__VIRTADDR__)) /*!< Get element value from virtual addr, data and crc values */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/** @defgroup EEPROM_Exported_Functions EEPROM Exported Functions
* @{
*/
EE_Status EE_Format(EE_Erase_type EraseType);
EE_Status EE_Init(EE_Erase_type EraseType);
#if defined(EE_ACCESS_32BITS)
EE_Status EE_ReadVariable32bits(uint16_t VirtAddress, uint32_t* pData);
EE_Status EE_WriteVariable32bits(uint16_t VirtAddress, uint32_t Data);
#endif
#if defined(FLASH_LINES_128B)
EE_Status EE_ReadVariable96bits(uint16_t VirtAddress, uint64_t* pData);
EE_Status EE_WriteVariable96bits(uint16_t VirtAddress, uint64_t* Data);
#endif
EE_Status EE_ReadVariable16bits(uint16_t VirtAddress, uint16_t* pData);
EE_Status EE_WriteVariable16bits(uint16_t VirtAddress, uint16_t Data);
EE_Status EE_ReadVariable8bits(uint16_t VirtAddress, uint8_t* pData);
EE_Status EE_WriteVariable8bits(uint16_t VirtAddress, uint8_t Data);
EE_Status EE_CleanUp(void);
EE_Status EE_CleanUp_IT(void);
EE_Status EE_DeleteCorruptedFlashAddress(uint32_t Address);
void EE_EndOfCleanup_UserCallback(void);
/**
* @}
*/
/**
* @}
*/
#endif /* __EEPROM_EMUL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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