version13
version 11/12 auch noch
This commit is contained in:
parent
ec01320c33
commit
b98c372f7e
76
.cproject
76
.cproject
@ -23,7 +23,7 @@
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||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.144641403;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.144641403.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.678807872;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1276633769">
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/tecware"/>
|
||||
@ -209,4 +220,13 @@
|
||||
<resource resourceType="PROJECT" workspacePath="/tecware"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.144641403;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.144641403.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.678807872;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1276633769">
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1856972322;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1856972322.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.242899579;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1332080456">
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
File diff suppressed because one or more lines are too long
3
.settings/com.st.stm32cube.ide.mcu.sfr.prefs
Normal file
3
.settings/com.st.stm32cube.ide.mcu.sfr.prefs
Normal file
@ -0,0 +1,3 @@
|
||||
eclipse.preferences.version=1
|
||||
svd_custom_file_path=
|
||||
svd_file_path=platform\:/plugin/com.st.stm32cube.ide.mcu.productdb.debug/resources/cmsis/STMicroelectronics_CMSIS_SVD/STM32L432.svd
|
||||
@ -5,7 +5,7 @@
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1127258010717180053" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1209555183635287960" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
@ -16,7 +16,7 @@
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1127258010717180053" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1209555183635287960" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
2F62501ED4689FB349E356AB974DBE57=97AEA8F7A6DEDA08C53D5080FEC61304
|
||||
8DF89ED150041C4CBC7CB9A9CAA90856=97AEA8F7A6DEDA08C53D5080FEC61304
|
||||
DC22A860405A8BF2F2C095E5B6529F12=BDCA684B3CBB9004D0FD137F3977D13A
|
||||
2F62501ED4689FB349E356AB974DBE57=A086EFBE51DAEF3695BC2E933AC3927D
|
||||
8DF89ED150041C4CBC7CB9A9CAA90856=A086EFBE51DAEF3695BC2E933AC3927D
|
||||
DC22A860405A8BF2F2C095E5B6529F12=4D49891D8384AE8B8742A84C899C7E0C
|
||||
eclipse.preferences.version=1
|
||||
|
||||
@ -59,7 +59,7 @@
|
||||
//=================================================================================================
|
||||
|
||||
/* Software Version */
|
||||
#define SW_VERSION 10
|
||||
#define SW_VERSION 13
|
||||
|
||||
#define MSG_QUEUE_SIZE 8
|
||||
|
||||
|
||||
@ -82,13 +82,13 @@ LOCAL osMutexId_t m_pstMutexID = NULL;
|
||||
|
||||
LOCAL CONST VARH_StVarInfo m_astVarInfo[VARH_eNumberOfVariables] =
|
||||
{
|
||||
{ VARH_FLAGINFO_NONE, (VARH_UVariable)(U32)1, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1}, // VARH_eMode
|
||||
{ VARH_FLAGINFO_NONE, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1}, // VARH_eMode
|
||||
|
||||
{ VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-5.0f, (VARH_UVariable)12.0f}, // VARH_eControlVoltage
|
||||
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kp
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_ki
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kd
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.4f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kp
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.03f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_ki
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)3.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePID_kd
|
||||
{ VARH_FLAGINFO_FLOAT, (VARH_UVariable)23.0f, (VARH_UVariable)-40.0f, (VARH_UVariable)50.0f }, // VARH_ePID_Temp
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)10.0f, (VARH_UVariable)0.0f, (VARH_UVariable)12.0f }, // VARH_ePID_Max
|
||||
{ VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)-2.0f, (VARH_UVariable)-5.0f, (VARH_UVariable)0.0f }, // VARH_ePID_Min
|
||||
@ -98,13 +98,13 @@ LOCAL CONST VARH_StVarInfo m_astVarInfo[VARH_eNumberOfVariables] =
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-1000.0f, (VARH_UVariable)1000.0f }, // VARH_eTemp_Diff - not used anymore
|
||||
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-8.0f, (VARH_UVariable)15.0f }, // VARH_ePeltier_U
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-10.0f, (VARH_UVariable)10.0f }, // VARH_ePeltier_I
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)5.0f }, // VARH_ePeltier_R
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)150.0f }, // VARH_ePeltier_P
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-15.0f, (VARH_UVariable)15.0f }, // VARH_ePeltier_I
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)100.0f }, // VARH_ePeltier_R
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-50.0f, (VARH_UVariable)160.0f }, // VARH_ePeltier_P
|
||||
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)20.0f, (VARH_UVariable)30.0f }, // VARH_eSupply_U
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-10.0f, (VARH_UVariable)5.0f }, // VARH_eSupply_I
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)-10.0f, (VARH_UVariable)150.0f }, // VARH_eSupply_P
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)15.0f }, // VARH_eSupply_I
|
||||
{ VARH_FLAGINFO_READONLY | VARH_FLAGINFO_FLOAT, (VARH_UVariable)0.0f, (VARH_UVariable)0.0f, (VARH_UVariable)160.0f }, // VARH_eSupply_P
|
||||
|
||||
{ VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1 }, // VARH_ePowerState
|
||||
{ VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0xFFFFFFFF }, // VARH_eError
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
#include "stm32l4xx_hal.h"
|
||||
|
||||
#include "cmsis_os2.h"
|
||||
#include <math.h>
|
||||
|
||||
//=================================================================================================
|
||||
// Section: DEFINITIONS
|
||||
@ -65,7 +66,7 @@
|
||||
#define OVERSAMPLING_DIVISOR 16.0f // calculated with parameters from hardware oversampling
|
||||
// 6 bits(64x) - 2 bit shift = 4bit -> 16x
|
||||
|
||||
#define ALMOST_ZERO 0.05
|
||||
#define ALMOST_ZERO 0.1
|
||||
|
||||
//=================================================================================================
|
||||
// Section: MACROS
|
||||
@ -109,18 +110,26 @@ LOCAL FLOAT aflValues[ANPI_eInNumberOfInputs]; // values
|
||||
LOCAL CONST FLOAT m_aflConversionFactor[ANPI_eInNumberOfInputs] =
|
||||
{
|
||||
10, // 01 ANPI_eSupplyVoltage24V
|
||||
5, // 02 ANPI_eSupplyCurrent24V
|
||||
10, // 03 ANPI_eOutputVoltage
|
||||
5, // 04 ANPI_eOutputCurrent
|
||||
5, // 02 ANPI_eSupplyCurrent24V
|
||||
10, // 03 ANPI_eOutputVoltage
|
||||
5, // 04 ANPI_eOutputCurrent
|
||||
};
|
||||
|
||||
// Order must fit enumeration "ANPI_EnAnalogInput"
|
||||
LOCAL CONST FLOAT m_aflOffset[ANPI_eInNumberOfInputs] =
|
||||
{
|
||||
0.0f, // 01 ANPI_eSupplyVoltage24V
|
||||
8.25f, // 02 ANPI_eSupplyCurrent24V
|
||||
14.85f, // 03 ANPI_eOutputVoltage
|
||||
8.25f, // 04 ANPI_eOutputCurrent
|
||||
0.0f, // 01 ANPI_eSupplyVoltage24V
|
||||
8.25f, // 02 ANPI_eSupplyCurrent24V
|
||||
14.85f, // 03 ANPI_eOutputVoltage
|
||||
8.25f, // 04 ANPI_eOutputCurrent
|
||||
};
|
||||
|
||||
LOCAL CONST BOOL m_aboNegativeValuesAllowed[ANPI_eInNumberOfInputs] =
|
||||
{
|
||||
FALSE, // 01 ANPI_eSupplyVoltage24V
|
||||
FALSE, // 02 ANPI_eSupplyCurrent24V
|
||||
TRUE, // 03 ANPI_eOutputVoltage
|
||||
TRUE, // 04 ANPI_eOutputCurrent
|
||||
};
|
||||
|
||||
// inputs are connected to the following ADCs
|
||||
@ -250,13 +259,20 @@ VOID vTask( PVOID arg )
|
||||
aflValues[u16Cnt] = 0.0f;
|
||||
}
|
||||
|
||||
for( U16 u16Cnt = 0; u16Cnt < ANPI_eInNumberOfInputs; u16Cnt++ )
|
||||
{
|
||||
if( ! m_aboNegativeValuesAllowed[u16Cnt] ){
|
||||
if( aflValues[u16Cnt] < 0.0f) aflValues[u16Cnt] = 0.0f;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_U, aflValues[ANPI_eOutputVoltage] );
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_I, aflValues[ANPI_eOutputCurrent] );
|
||||
if ( aflValues[ANPI_eOutputCurrent] == 0.0f ){
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, 0.0f );
|
||||
} else {
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, aflValues[ANPI_eOutputVoltage] / aflValues[ANPI_eOutputCurrent] );
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_R, fabs( aflValues[ANPI_eOutputVoltage] / aflValues[ANPI_eOutputCurrent]) );
|
||||
}
|
||||
VARH_vSetVariableDataFromSystemFloat( VARH_ePeltier_P, aflValues[ANPI_eOutputVoltage] * aflValues[ANPI_eOutputCurrent] );
|
||||
|
||||
|
||||
@ -191,7 +191,7 @@ VOID vTask(PVOID arg)
|
||||
{
|
||||
boUpdateVoltage();
|
||||
|
||||
BOOL boPowerGood = DIPO_boGetInput(DIPO_ePG);
|
||||
// BOOL boPowerGood = DIPO_boGetInput(DIPO_ePG);
|
||||
/** @todo check power good pin */
|
||||
}
|
||||
}
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
#define __STM32L4xx_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
|
||||
@ -121,6 +121,7 @@ static void VectorBase_Config(void)
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
VectorBase_Config();
|
||||
/* USER CODE END 1 */
|
||||
@ -190,6 +191,7 @@ int main(void)
|
||||
osKernelStart();
|
||||
|
||||
/* We should never get here as control is now taken by the scheduler */
|
||||
|
||||
/* Infinite loop */
|
||||
/* USER CODE BEGIN WHILE */
|
||||
while (1)
|
||||
@ -473,7 +475,7 @@ static void MX_I2C1_Init(void)
|
||||
|
||||
/* USER CODE END I2C1_Init 1 */
|
||||
hi2c1.Instance = I2C1;
|
||||
hi2c1.Init.Timing = 0x10909CEC;
|
||||
hi2c1.Init.Timing = 0x10D19CE4;
|
||||
hi2c1.Init.OwnAddress1 = 0;
|
||||
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
||||
@ -605,8 +607,8 @@ static void MX_DMA_Init(void)
|
||||
static void MX_GPIO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
||||
/* USER CODE END MX_GPIO_Init_1 */
|
||||
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
||||
/* USER CODE END MX_GPIO_Init_1 */
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
@ -661,8 +663,8 @@ static void MX_GPIO_Init(void)
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
||||
/* USER CODE END MX_GPIO_Init_2 */
|
||||
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
||||
/* USER CODE END MX_GPIO_Init_2 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
|
||||
@ -21,7 +21,6 @@
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
@ -69,6 +68,7 @@ extern DMA_HandleTypeDef hdma_spi1_tx;
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN MspInit 0 */
|
||||
|
||||
/* USER CODE END MspInit 0 */
|
||||
@ -86,20 +86,20 @@ void HAL_MspInit(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hadc: ADC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief ADC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hadc: ADC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||
if(hadc->Instance==ADC1)
|
||||
{
|
||||
/* USER CODE BEGIN ADC1_MspInit 0 */
|
||||
/* USER CODE BEGIN ADC1_MspInit 0 */
|
||||
|
||||
/* USER CODE END ADC1_MspInit 0 */
|
||||
/* USER CODE END ADC1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
@ -152,26 +152,27 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
/* ADC1 interrupt Init */
|
||||
HAL_NVIC_SetPriority(ADC1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(ADC1_IRQn);
|
||||
/* USER CODE BEGIN ADC1_MspInit 1 */
|
||||
/* USER CODE BEGIN ADC1_MspInit 1 */
|
||||
|
||||
/* USER CODE END ADC1_MspInit 1 */
|
||||
|
||||
/* USER CODE END ADC1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hadc: ADC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief ADC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hadc: ADC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
if(hadc->Instance==ADC1)
|
||||
{
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 0 */
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END ADC1_MspDeInit 0 */
|
||||
/* USER CODE END ADC1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ADC_CLK_DISABLE();
|
||||
|
||||
@ -190,27 +191,27 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||||
|
||||
/* ADC1 interrupt DeInit */
|
||||
HAL_NVIC_DisableIRQ(ADC1_IRQn);
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 1 */
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END ADC1_MspDeInit 1 */
|
||||
/* USER CODE END ADC1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CAN MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hcan: CAN handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief CAN MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hcan: CAN handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
if(hcan->Instance==CAN1)
|
||||
{
|
||||
/* USER CODE BEGIN CAN1_MspInit 0 */
|
||||
/* USER CODE BEGIN CAN1_MspInit 0 */
|
||||
|
||||
/* USER CODE END CAN1_MspInit 0 */
|
||||
/* USER CODE END CAN1_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_CAN1_CLK_ENABLE();
|
||||
|
||||
@ -235,26 +236,27 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
|
||||
HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
|
||||
/* USER CODE BEGIN CAN1_MspInit 1 */
|
||||
/* USER CODE BEGIN CAN1_MspInit 1 */
|
||||
|
||||
/* USER CODE END CAN1_MspInit 1 */
|
||||
|
||||
/* USER CODE END CAN1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CAN MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hcan: CAN handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief CAN MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hcan: CAN handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
||||
{
|
||||
if(hcan->Instance==CAN1)
|
||||
{
|
||||
/* USER CODE BEGIN CAN1_MspDeInit 0 */
|
||||
/* USER CODE BEGIN CAN1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END CAN1_MspDeInit 0 */
|
||||
/* USER CODE END CAN1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_CAN1_CLK_DISABLE();
|
||||
|
||||
@ -269,71 +271,72 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
||||
HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
|
||||
HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn);
|
||||
/* USER CODE BEGIN CAN1_MspDeInit 1 */
|
||||
/* USER CODE BEGIN CAN1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END CAN1_MspDeInit 1 */
|
||||
/* USER CODE END CAN1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CRC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hcrc: CRC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief CRC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hcrc: CRC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
|
||||
{
|
||||
if(hcrc->Instance==CRC)
|
||||
{
|
||||
/* USER CODE BEGIN CRC_MspInit 0 */
|
||||
/* USER CODE BEGIN CRC_MspInit 0 */
|
||||
|
||||
/* USER CODE END CRC_MspInit 0 */
|
||||
/* USER CODE END CRC_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_CRC_CLK_ENABLE();
|
||||
/* USER CODE BEGIN CRC_MspInit 1 */
|
||||
/* USER CODE BEGIN CRC_MspInit 1 */
|
||||
|
||||
/* USER CODE END CRC_MspInit 1 */
|
||||
|
||||
/* USER CODE END CRC_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CRC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hcrc: CRC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief CRC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hcrc: CRC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
|
||||
{
|
||||
if(hcrc->Instance==CRC)
|
||||
{
|
||||
/* USER CODE BEGIN CRC_MspDeInit 0 */
|
||||
/* USER CODE BEGIN CRC_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END CRC_MspDeInit 0 */
|
||||
/* USER CODE END CRC_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_CRC_CLK_DISABLE();
|
||||
/* USER CODE BEGIN CRC_MspDeInit 1 */
|
||||
/* USER CODE BEGIN CRC_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END CRC_MspDeInit 1 */
|
||||
/* USER CODE END CRC_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DAC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hdac: DAC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief DAC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hdac: DAC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
if(hdac->Instance==DAC1)
|
||||
{
|
||||
/* USER CODE BEGIN DAC1_MspInit 0 */
|
||||
/* USER CODE BEGIN DAC1_MspInit 0 */
|
||||
|
||||
/* USER CODE END DAC1_MspInit 0 */
|
||||
/* USER CODE END DAC1_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_DAC1_CLK_ENABLE();
|
||||
|
||||
@ -346,26 +349,27 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN DAC1_MspInit 1 */
|
||||
/* USER CODE BEGIN DAC1_MspInit 1 */
|
||||
|
||||
/* USER CODE END DAC1_MspInit 1 */
|
||||
|
||||
/* USER CODE END DAC1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DAC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hdac: DAC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief DAC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hdac: DAC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
if(hdac->Instance==DAC1)
|
||||
{
|
||||
/* USER CODE BEGIN DAC1_MspDeInit 0 */
|
||||
/* USER CODE BEGIN DAC1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END DAC1_MspDeInit 0 */
|
||||
/* USER CODE END DAC1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_DAC1_CLK_DISABLE();
|
||||
|
||||
@ -374,28 +378,28 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
|
||||
|
||||
/* USER CODE BEGIN DAC1_MspDeInit 1 */
|
||||
/* USER CODE BEGIN DAC1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END DAC1_MspDeInit 1 */
|
||||
/* USER CODE END DAC1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2C MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hi2c: I2C handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief I2C MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hi2c: I2C handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||
if(hi2c->Instance==I2C1)
|
||||
{
|
||||
/* USER CODE BEGIN I2C1_MspInit 0 */
|
||||
/* USER CODE BEGIN I2C1_MspInit 0 */
|
||||
|
||||
/* USER CODE END I2C1_MspInit 0 */
|
||||
/* USER CODE END I2C1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
@ -420,26 +424,27 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||
/* USER CODE BEGIN I2C1_MspInit 1 */
|
||||
/* USER CODE BEGIN I2C1_MspInit 1 */
|
||||
|
||||
/* USER CODE END I2C1_MspInit 1 */
|
||||
|
||||
/* USER CODE END I2C1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2C MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hi2c: I2C handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief I2C MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hi2c: I2C handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
||||
{
|
||||
if(hi2c->Instance==I2C1)
|
||||
{
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 0 */
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END I2C1_MspDeInit 0 */
|
||||
/* USER CODE END I2C1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_I2C1_CLK_DISABLE();
|
||||
|
||||
@ -451,27 +456,27 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
||||
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10);
|
||||
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 1 */
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END I2C1_MspDeInit 1 */
|
||||
/* USER CODE END I2C1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SPI MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hspi: SPI handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief SPI MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param hspi: SPI handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
if(hspi->Instance==SPI1)
|
||||
{
|
||||
/* USER CODE BEGIN SPI1_MspInit 0 */
|
||||
/* USER CODE BEGIN SPI1_MspInit 0 */
|
||||
|
||||
/* USER CODE END SPI1_MspInit 0 */
|
||||
/* USER CODE END SPI1_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_SPI1_CLK_ENABLE();
|
||||
|
||||
@ -526,26 +531,27 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
||||
/* SPI1 interrupt Init */
|
||||
HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(SPI1_IRQn);
|
||||
/* USER CODE BEGIN SPI1_MspInit 1 */
|
||||
/* USER CODE BEGIN SPI1_MspInit 1 */
|
||||
|
||||
/* USER CODE END SPI1_MspInit 1 */
|
||||
|
||||
/* USER CODE END SPI1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SPI MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hspi: SPI handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
* @brief SPI MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hspi: SPI handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
||||
{
|
||||
if(hspi->Instance==SPI1)
|
||||
{
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 0 */
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SPI1_MspDeInit 0 */
|
||||
/* USER CODE END SPI1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SPI1_CLK_DISABLE();
|
||||
|
||||
@ -562,9 +568,9 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
||||
|
||||
/* SPI1 interrupt DeInit */
|
||||
HAL_NVIC_DisableIRQ(SPI1_IRQn);
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 1 */
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SPI1_MspDeInit 1 */
|
||||
/* USER CODE END SPI1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -930,7 +930,7 @@ typedef struct
|
||||
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
|
||||
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
|
||||
|
||||
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
|
||||
#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL)
|
||||
|
||||
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
|
||||
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
|
||||
@ -1153,7 +1153,7 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
|
||||
*/
|
||||
/* Note: No specific macro feature on this device */
|
||||
|
||||
@ -5797,7 +5797,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
|
||||
*/
|
||||
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
|
||||
|
||||
@ -8825,7 +8825,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
|
||||
*/
|
||||
#define RCC_PLLSAI1_SUPPORT
|
||||
#define RCC_PLLP_SUPPORT
|
||||
@ -13136,7 +13136,7 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
|
||||
*/
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
|
||||
@ -106,7 +106,7 @@
|
||||
*/
|
||||
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32L4_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
|
||||
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
||||
@ -37,14 +37,12 @@ extern "C" {
|
||||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5)
|
||||
#if defined(STM32H7) || defined(STM32MP1)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
#endif /* STM32H7 || STM32MP1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -110,6 +108,10 @@ extern "C" {
|
||||
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
|
||||
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
|
||||
#endif /* STM32H5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -137,7 +139,8 @@ extern "C" {
|
||||
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
|
||||
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
|
||||
#if defined(STM32L0)
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
|
||||
input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#endif
|
||||
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
@ -211,6 +214,11 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -231,9 +239,13 @@ extern "C" {
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32C0)
|
||||
#else
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -275,7 +287,13 @@ extern "C" {
|
||||
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
|
||||
#if defined(STM32H5)
|
||||
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
|
||||
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
|
||||
defined(STM32F4) || defined(STM32G4)
|
||||
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@ -340,7 +358,8 @@ extern "C" {
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
|
||||
defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
@ -500,7 +519,7 @@ extern "C" {
|
||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||
#if defined(STM32G0)
|
||||
#if defined(STM32G0) || defined(STM32C0)
|
||||
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||
#else
|
||||
@ -525,7 +544,20 @@ extern "C" {
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
|
||||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -569,6 +601,106 @@ extern "C" {
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
|
||||
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
|
||||
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
|
||||
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
|
||||
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
|
||||
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
|
||||
|
||||
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
|
||||
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
|
||||
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
|
||||
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
|
||||
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
|
||||
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
|
||||
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
|
||||
|
||||
#define SYSCFG_ETH_MII SBS_ETH_MII
|
||||
#define SYSCFG_ETH_RMII SBS_ETH_RMII
|
||||
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
|
||||
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
|
||||
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
|
||||
|
||||
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
|
||||
|
||||
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
|
||||
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SYSCFG_SAU SBS_SAU
|
||||
#define SYSCFG_MPU_SEC SBS_MPU_SEC
|
||||
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#else
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define SYSCFG_CLK SBS_CLK
|
||||
#define SYSCFG_CLASSB SBS_CLASSB
|
||||
#define SYSCFG_FPU SBS_FPU
|
||||
#define SYSCFG_ALL SBS_ALL
|
||||
|
||||
#define SYSCFG_SEC SBS_SEC
|
||||
#define SYSCFG_NSEC SBS_NSEC
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
|
||||
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
|
||||
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
|
||||
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
|
||||
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
|
||||
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
|
||||
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
|
||||
|
||||
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
|
||||
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
|
||||
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
|
||||
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
|
||||
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
|
||||
|
||||
#define HAL_SYSCFG_Lock HAL_SBS_Lock
|
||||
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
|
||||
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -636,14 +768,16 @@ extern "C" {
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
|
||||
STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
|
||||
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
@ -665,13 +799,28 @@ extern "C" {
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
||||
#if defined(STM32U5)
|
||||
#if defined(STM32U5) || defined(STM32H5)
|
||||
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
|
||||
#endif /* STM32U5 */
|
||||
#endif /* STM32U5 || STM32H5 */
|
||||
#if defined(STM32U5)
|
||||
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
|
||||
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
|
||||
#endif /* STM32WBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -681,7 +830,25 @@ extern "C" {
|
||||
*/
|
||||
#if defined(STM32U5)
|
||||
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
|
||||
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32H5)
|
||||
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
|
||||
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
|
||||
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
|
||||
#endif /* STM32H5 */
|
||||
#if defined(STM32H5) || defined(STM32U5)
|
||||
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
|
||||
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
|
||||
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
|
||||
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
|
||||
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
|
||||
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
|
||||
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
|
||||
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
|
||||
#endif /* STM32H5 || STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -862,7 +1029,8 @@ extern "C" {
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
|
||||
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
|
||||
defined(STM32L1) || defined(STM32F7)
|
||||
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
@ -1000,7 +1168,7 @@ extern "C" {
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
|
||||
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@ -1084,8 +1252,8 @@ extern "C" {
|
||||
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
|
||||
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
|
||||
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
|
||||
|
||||
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
|
||||
@ -1096,15 +1264,42 @@ extern "C" {
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 || STM32H7RS */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
|
||||
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
|
||||
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
|
||||
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
|
||||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
|
||||
#endif /* STM32F7 */
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
|
||||
#endif /* STM32H7 */
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
|
||||
#endif /* STM32F7 || STM32H7 || STM32L0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1271,7 +1466,7 @@ extern "C" {
|
||||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5) || defined(STM32MP2)
|
||||
#if defined(STM32U5)
|
||||
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
|
||||
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
|
||||
#endif
|
||||
@ -1384,30 +1579,40 @@ extern "C" {
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
|
||||
the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
|
||||
MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
|
||||
or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
|
||||
of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
|
||||
transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
|
||||
frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
|
||||
de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
|
||||
activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
|
||||
(or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
|
||||
status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
@ -1415,6 +1620,8 @@ extern "C" {
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1578,7 +1785,8 @@ extern "C" {
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
|
||||
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
@ -1587,8 +1795,10 @@ extern "C" {
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
|
||||
HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
|
||||
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
@ -1622,16 +1832,21 @@ extern "C" {
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
|
||||
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
|
||||
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
|
||||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
|
||||
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
@ -1756,6 +1971,17 @@ extern "C" {
|
||||
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
|
||||
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
|
||||
|
||||
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
|
||||
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
|
||||
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
|
||||
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
|
||||
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
|
||||
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
|
||||
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
|
||||
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
|
||||
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
|
||||
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
|
||||
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
|
||||
@ -1764,6 +1990,8 @@ extern "C" {
|
||||
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
|
||||
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
|
||||
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
|
||||
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
|
||||
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
|
||||
@ -1774,6 +2002,7 @@ extern "C" {
|
||||
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
|
||||
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
|
||||
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
|
||||
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
|
||||
|
||||
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
|
||||
#endif
|
||||
@ -1782,6 +2011,20 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
@ -1807,7 +2050,8 @@ extern "C" {
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
|
||||
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
@ -2064,7 +2308,8 @@ extern "C" {
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
|
||||
defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2089,8 +2334,8 @@ extern "C" {
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2123,8 +2368,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2181,8 +2426,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
@ -2199,7 +2444,7 @@ extern "C" {
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2236,8 +2481,10 @@ extern "C" {
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -2396,7 +2643,9 @@ extern "C" {
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
@ -2405,8 +2654,12 @@ extern "C" {
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
|
||||
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
|
||||
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
@ -2442,8 +2695,8 @@ extern "C" {
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
|
||||
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
@ -2493,6 +2746,12 @@ extern "C" {
|
||||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#if defined(STM32C0)
|
||||
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
|
||||
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
|
||||
#endif /* STM32C0 */
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
@ -2947,6 +3206,11 @@ extern "C" {
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
|
||||
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
|
||||
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
|
||||
#endif
|
||||
|
||||
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
||||
@ -3411,7 +3675,12 @@ extern "C" {
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
@ -3513,8 +3782,10 @@ extern "C" {
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
@ -3524,8 +3795,8 @@ extern "C" {
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
#if defined(STM32U5)
|
||||
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
|
||||
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
|
||||
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
|
||||
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
|
||||
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
|
||||
@ -3541,16 +3812,106 @@ extern "C" {
|
||||
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
|
||||
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
|
||||
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
|
||||
#endif
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
|
||||
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
|
||||
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
|
||||
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
|
||||
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
|
||||
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
|
||||
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
|
||||
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
|
||||
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
|
||||
|
||||
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
|
||||
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
|
||||
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
|
||||
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
|
||||
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
|
||||
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
|
||||
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
|
||||
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
|
||||
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
|
||||
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
|
||||
|
||||
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
|
||||
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
|
||||
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
|
||||
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
|
||||
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
|
||||
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
|
||||
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
|
||||
|
||||
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
|
||||
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
|
||||
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
|
||||
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
|
||||
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
|
||||
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
|
||||
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
|
||||
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
|
||||
|
||||
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
|
||||
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
|
||||
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
|
||||
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
|
||||
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
|
||||
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
|
||||
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
|
||||
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
|
||||
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -3568,7 +3929,9 @@ extern "C" {
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@ -3603,6 +3966,13 @@ extern "C" {
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
@ -3621,6 +3991,11 @@ extern "C" {
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
#if defined (STM32H5)
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3632,7 +4007,7 @@ extern "C" {
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
|
||||
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
|
||||
@ -3879,6 +4254,9 @@ extern "C" {
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3969,6 +4347,16 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F7)
|
||||
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
|
||||
#endif /* STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
@ -60,9 +60,10 @@ typedef struct
|
||||
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
|
||||
The oversampling is either temporary stopped or reset upon an injected
|
||||
sequence interruption.
|
||||
If oversampling is enabled on both regular and injected groups, this parameter
|
||||
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
|
||||
(the oversampling buffer is zeroed during injection sequence).
|
||||
If oversampling is enabled on both regular and injected groups, this
|
||||
parameter is discarded and forced to setting
|
||||
"ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
|
||||
during injection sequence).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
|
||||
|
||||
} ADC_OversamplingTypeDef;
|
||||
@ -77,23 +78,31 @@ typedef struct
|
||||
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
|
||||
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
|
||||
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled
|
||||
* without conversion on going on group regular.
|
||||
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
|
||||
* on groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
|
||||
* (which fulfills the ADC state condition) on the fly).
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
|
||||
clock derived from system clock or PLL (Refer to reference manual for list of
|
||||
clocks available)) and clock prescaler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
|
||||
Note: The ADC clock configuration is common to all ADC instances.
|
||||
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
|
||||
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
|
||||
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
|
||||
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
|
||||
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
|
||||
Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
|
||||
Note: In case of usage of channels on injected group, ADC frequency should be
|
||||
lower than AHB clock frequency /4 for resolution 12 or 10 bits,
|
||||
AHB clock frequency /3 for resolution 8 bits,
|
||||
AHB clock frequency /2 for resolution 6 bits.
|
||||
Note: In case of synchronous clock mode based on HCLK/1, the configuration must
|
||||
be enabled only if the system clock has a 50% duty clock cycle (APB
|
||||
prescaler configured inside RCC must be bypassed and PCLK clock must have
|
||||
50% duty cycle). Refer to reference manual for details.
|
||||
Note: In case of usage of asynchronous clock, the selected clock must be
|
||||
preliminarily enabled at RCC top level.
|
||||
Note: This parameter can be modified only if all ADC instances are disabled. */
|
||||
|
||||
uint32_t Resolution; /*!< Configure the ADC resolution.
|
||||
@ -104,84 +113,131 @@ typedef struct
|
||||
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
|
||||
|
||||
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
|
||||
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
|
||||
Scan direction is upward: from rank 1 to rank 'n'.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have
|
||||
main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the
|
||||
one defined in rank 1). Parameters 'NbrOfConversion' and
|
||||
'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined
|
||||
by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each
|
||||
channel in sequencer). Scan direction is upward: from rank 1 to
|
||||
rank 'n'.
|
||||
This parameter can be a value of @ref ADC_Scan_mode */
|
||||
|
||||
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
|
||||
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
|
||||
interruption: end of unitary conversion or end of sequence conversions.
|
||||
This parameter can be a value of @ref ADC_EOCSelection. */
|
||||
|
||||
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
|
||||
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
|
||||
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
|
||||
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
|
||||
for low frequency applications.
|
||||
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
|
||||
previous conversion (for ADC group regular) or previous sequence (for ADC group
|
||||
injected) has been retrieved by user software, using function HAL_ADC_GetValue()
|
||||
or HAL_ADCEx_InjectedGetValue().
|
||||
This feature automatically adapts the frequency of ADC conversions triggers to
|
||||
the speed of the system that reads the data. Moreover, this avoids risk of
|
||||
overrun for low frequency applications.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
|
||||
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
|
||||
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
|
||||
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
|
||||
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
|
||||
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
|
||||
HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
|
||||
flag (by CPU to free the IRQ pending event or by DMA).
|
||||
Auto wait will work but fort a very short time, discarding its intended
|
||||
benefit (except specific case of high load of CPU or DMA transfers which
|
||||
can justify usage of auto wait).
|
||||
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
|
||||
when ADC conversion data is needed:
|
||||
use HAL_ADC_PollForConversion() to ensure that conversion is completed and
|
||||
HAL_ADC_GetValue() to retrieve conversion result and trig another
|
||||
conversion start. (in case of usage of ADC group injected, use the
|
||||
equivalent functions HAL_ADCExInjected_Start(),
|
||||
HAL_ADCEx_InjectedGetValue(), ...). */
|
||||
|
||||
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
|
||||
after the first ADC conversion start trigger occurred (software start or external trigger).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
|
||||
or continuous mode for ADC group regular, after the first ADC conversion
|
||||
start trigger occurred (software start or external trigger). This parameter
|
||||
can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
|
||||
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16.
|
||||
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
|
||||
continuous mode or external trigger that could launch a conversion). */
|
||||
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
|
||||
sequencer.
|
||||
This parameter is dependent on ScanConvMode:
|
||||
- sequencer configured to fully configurable:
|
||||
Number of ranks in the scan sequence is configurable using this parameter.
|
||||
Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
|
||||
parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
|
||||
Afterwards, when all needed sequencer ranks are set, parameter
|
||||
'NbrOfConversion' can be updated without modifying configuration of
|
||||
sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
|
||||
- sequencer configured to not fully configurable:
|
||||
Number of ranks in the scan sequence is defined by number of channels set in
|
||||
the sequence. This parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8.
|
||||
Note: This parameter must be modified when no conversion is on going on regular
|
||||
group (ADC disabled, or ADC enabled without continuous mode or external
|
||||
trigger that could launch a conversion). */
|
||||
|
||||
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
|
||||
(main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
|
||||
in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
|
||||
successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter
|
||||
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: On this STM32 series, ADC group regular number of discontinuous
|
||||
ranks increment is fixed to one-by-one. */
|
||||
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence
|
||||
of ADC group regular (parameter NbrOfConversion) will be subdivided.
|
||||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
|
||||
|
||||
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
|
||||
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
|
||||
start.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
|
||||
is used instead.
|
||||
This parameter can be a value of @ref ADC_regular_external_trigger_source.
|
||||
Caution: external trigger source is common to all ADC instances. */
|
||||
|
||||
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
|
||||
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
|
||||
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
|
||||
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
|
||||
|
||||
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
|
||||
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
|
||||
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
|
||||
transfer stops when number of conversions is reached) or in continuous
|
||||
mode (DMA transfer unlimited, whatever number of conversions).
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: In continuous mode, DMA must be configured in circular mode.
|
||||
Otherwise an overrun will be triggered when DMA buffer maximum
|
||||
pointer is reached. */
|
||||
|
||||
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
|
||||
This parameter applies to ADC group regular only.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
|
||||
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
|
||||
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
|
||||
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
|
||||
Note: In case of overrun set to data preserved and usage with programming model
|
||||
with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
|
||||
conversion flags, this induces the release of the preserved data. If
|
||||
needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
|
||||
placed in user program code (called before end of conversion flags clear)
|
||||
Note: Error reporting with respect to the conversion mode:
|
||||
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
|
||||
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
|
||||
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
|
||||
- Usage with ADC conversion by polling for event or interruption: Error is
|
||||
reported only if overrun is set to data preserved. If overrun is set to
|
||||
data overwritten, user can willingly not read all the converted data,
|
||||
this is not considered as an erroneous case.
|
||||
- Usage with ADC conversion by DMA: Error is reported whatever overrun
|
||||
setting (DMA is expected to process all data from data register). */
|
||||
|
||||
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
|
||||
Note: This parameter can be modified only if there is no conversion is
|
||||
ongoing on ADC groups regular and injected */
|
||||
|
||||
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
|
||||
Caution: this setting overwrites the previous oversampling configuration
|
||||
if oversampling is already enabled. */
|
||||
|
||||
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
|
||||
uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing
|
||||
(both ADSTART and JADSTART cleared). */
|
||||
|
||||
#endif /* ADC_CFGR_DFSDMCFG */
|
||||
} ADC_InitTypeDef;
|
||||
@ -191,56 +247,72 @@ typedef struct
|
||||
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
|
||||
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
|
||||
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
|
||||
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
|
||||
* on going on regular group.
|
||||
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
|
||||
* regular and injected groups.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
|
||||
* on the fly).
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
|
||||
Note: Depending on devices and ADC instances, some channels may not be available
|
||||
on device package pins. Refer to device datasheet for channels
|
||||
availability. */
|
||||
|
||||
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
|
||||
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions adjusted) */
|
||||
Note: to disable a channel or change order of conversion sequencer, rank
|
||||
containing a previous channel setting can be overwritten by the new channel
|
||||
setting (or parameter number of conversions adjusted) */
|
||||
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
|
||||
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
|
||||
Caution: This parameter applies to a channel that can be used into regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Caution: This parameter applies to a channel that can be used into regular
|
||||
and/or injected group. It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...),
|
||||
sampling time constraints must be respected (sampling time can be adjusted
|
||||
in function of ADC clock frequency and sampling time setting).
|
||||
Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t SingleDiff; /*!< Select single-ended or differential input.
|
||||
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
|
||||
In differential mode: Differential measurement is carried out between the
|
||||
selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically
|
||||
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
Caution: This parameter applies to a channel that can be used in a regular
|
||||
and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
|
||||
of another parameter update on the fly) */
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in
|
||||
differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is
|
||||
not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start
|
||||
conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error
|
||||
reporting (as it can be the expected behavior in case of another parameter
|
||||
update on the fly) */
|
||||
|
||||
uint32_t OffsetNumber; /*!< Select the offset number
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the
|
||||
last setting. */
|
||||
|
||||
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
|
||||
must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
|
||||
0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
Note: This parameter must be modified when no conversion is on going on both
|
||||
regular and injected groups (ADC disabled, or ADC enabled without
|
||||
continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
} ADC_ChannelConfTypeDef;
|
||||
|
||||
@ -248,47 +320,66 @@ typedef struct
|
||||
* @brief Structure definition of ADC analog watchdog
|
||||
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
|
||||
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and
|
||||
injected.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
|
||||
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
|
||||
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
|
||||
by setting parameter 'WatchdogMode')
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
|
||||
of 'HAL_ADC_AnalogWDGConfig()' for each channel)
|
||||
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
|
||||
|
||||
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
|
||||
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
|
||||
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
|
||||
channels, ADC groups regular and-or injected.
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored by applying
|
||||
successively the AWD init structure. Channels on ADC
|
||||
group regular and injected are not differentiated: Set
|
||||
value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
|
||||
channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
|
||||
all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
|
||||
channel.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
|
||||
|
||||
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
|
||||
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
|
||||
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
|
||||
is configured on single channel (only 1 channel can be
|
||||
monitored).
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
|
||||
call successively the function HAL_ADC_AnalogWDGConfig()
|
||||
for each channel to be added (or removed with value
|
||||
'ADC_ANALOGWATCHDOG_NONE').
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
|
||||
|
||||
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
|
||||
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
|
||||
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
|
||||
respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
|
||||
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
|
||||
LSB are ignored.
|
||||
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
|
||||
impacted: the comparison of analog watchdog thresholds is done on
|
||||
oversampling final computation (after ratio and shift application):
|
||||
ADC data register bitfield [15:4] (12 most significant bits). */
|
||||
|
||||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
|
||||
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
|
||||
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
|
||||
respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
|
||||
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
|
||||
LSB are ignored.
|
||||
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
|
||||
impacted: the comparison of analog watchdog thresholds is done on
|
||||
oversampling final computation (after ratio and shift application):
|
||||
ADC data register bitfield [15:4] (12 most significant bits). */
|
||||
ADC data register bitfield [15:4] (12 most significant bits).*/
|
||||
} ADC_AnalogWDGConfTypeDef;
|
||||
|
||||
/**
|
||||
@ -319,7 +410,8 @@ typedef struct
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization,
|
||||
calibration, ...) */
|
||||
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
@ -328,15 +420,20 @@ typedef struct
|
||||
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
|
||||
(either by continuous mode, external trigger, low power
|
||||
auto power-on (if feature available), multimode ADC master
|
||||
control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
|
||||
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
|
||||
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
|
||||
raised */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur
|
||||
(either by auto-injection mode, external trigger, low
|
||||
power auto power-on (if feature available), multimode
|
||||
ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
|
||||
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
|
||||
|
||||
@ -346,7 +443,8 @@ typedef struct
|
||||
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
|
||||
|
||||
/* States of ADC multi-mode */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC
|
||||
master (when feature available) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -361,20 +459,25 @@ typedef struct __ADC_HandleTypeDef
|
||||
typedef struct
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
|
||||
conversions setting */
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up
|
||||
structure */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
|
||||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
|
||||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
|
||||
callback */
|
||||
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
|
||||
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
|
||||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
|
||||
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
|
||||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete
|
||||
callback */
|
||||
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
|
||||
overflow callback */
|
||||
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
|
||||
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
|
||||
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
|
||||
@ -439,22 +542,37 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
|
||||
|
||||
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
|
||||
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
|
||||
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
|
||||
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
|
||||
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
|
||||
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
|
||||
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
|
||||
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
|
||||
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
|
||||
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
|
||||
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
|
||||
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
|
||||
without prescaler */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
|
||||
with prescaler division by 2 */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
|
||||
with prescaler division by 4 */
|
||||
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
|
||||
prescaler */
|
||||
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
|
||||
division by 2 */
|
||||
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
|
||||
division by 4 */
|
||||
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
|
||||
division by 6 */
|
||||
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
|
||||
division by 8 */
|
||||
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
|
||||
division by 10 */
|
||||
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
|
||||
division by 12 */
|
||||
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
|
||||
division by 16 */
|
||||
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
|
||||
division by 32 */
|
||||
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
|
||||
division by 64 */
|
||||
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
|
||||
division by 128 */
|
||||
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
|
||||
division by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -473,8 +591,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
|
||||
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
|
||||
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
|
||||
(alignment on data register LSB bit 0)*/
|
||||
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
|
||||
(alignment on data register MSB bit 15)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -492,23 +612,40 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion
|
||||
trigger software start */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 TRGO2. */
|
||||
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM3 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM4 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM4 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM6 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM8 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM8 TRGO2. */
|
||||
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM15 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: external interrupt line 11. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -516,10 +653,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
|
||||
disabled (SW start)*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion
|
||||
trigger polarity set to rising edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion
|
||||
trigger polarity set to falling edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
|
||||
trigger polarity set to both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -536,8 +677,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
|
||||
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
|
||||
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case
|
||||
of overrun: data preserved */
|
||||
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case
|
||||
of overrun: data overwritten */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -577,7 +720,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
|
||||
#if defined(ADC_SMPR1_SMPPLUS)
|
||||
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
|
||||
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5
|
||||
ADC clock cycles. If selected, this sampling time replaces sampling time
|
||||
2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
|
||||
#endif /* ADC_SMPR1_SMPPLUS */
|
||||
/**
|
||||
* @}
|
||||
@ -588,44 +733,56 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
*/
|
||||
/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
|
||||
/* all ADC instances (refer to Reference Manual). */
|
||||
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
|
||||
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
|
||||
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
|
||||
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
|
||||
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
|
||||
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
|
||||
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
|
||||
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
|
||||
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
|
||||
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
|
||||
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
|
||||
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
|
||||
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
|
||||
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
|
||||
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
|
||||
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
|
||||
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
|
||||
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
|
||||
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
|
||||
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
|
||||
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
|
||||
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
|
||||
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
|
||||
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
|
||||
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
|
||||
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
|
||||
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
|
||||
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
|
||||
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
|
||||
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
|
||||
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
|
||||
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
|
||||
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
|
||||
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
|
||||
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
|
||||
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
|
||||
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
|
||||
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
|
||||
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
|
||||
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
|
||||
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
|
||||
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal
|
||||
voltage reference. */
|
||||
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */
|
||||
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage
|
||||
through a divider ladder of factor 1/3 to have channel voltage always below
|
||||
Vdda. */
|
||||
#if defined(ADC1) && !defined(ADC2)
|
||||
#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
|
||||
#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
|
||||
#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< Internal channel DAC1 channel 1,
|
||||
channel specific to ADC1. This channel is shared with Internal temperature
|
||||
sensor, selection is done using function
|
||||
@ref LL_ADC_SetCommonPathInternalCh(). */
|
||||
#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< Internal channel DAC1 channel 2,
|
||||
channel specific to ADC1. This channel is shared with Internal Vbat,
|
||||
selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
|
||||
#elif defined(ADC2)
|
||||
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
|
||||
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
|
||||
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< Internal channel DAC1 channel 1,
|
||||
channel specific to ADC2 */
|
||||
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< Internal channel DAC1 channel 2,
|
||||
channel specific to ADC2 */
|
||||
#if defined(ADC3)
|
||||
#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
|
||||
#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
|
||||
#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< Internal channel DAC1 channel 1,
|
||||
channel specific to ADC3 */
|
||||
#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< Internal channel DAC1 channel 2,
|
||||
channel specific to ADC3 */
|
||||
#endif /* ADC3 */
|
||||
#endif /* ADC1 && !ADC2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
|
||||
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
|
||||
@ -635,16 +792,23 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
|
||||
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
|
||||
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular
|
||||
group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an
|
||||
injected group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
|
||||
| ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular
|
||||
and injected groups single channel */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular
|
||||
group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected
|
||||
group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular
|
||||
and injected groups all channels */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -652,14 +816,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
|
||||
/**
|
||||
* @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
|
||||
* to result as the ADC oversampling conversion data (before potential shift)
|
||||
*/
|
||||
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -667,15 +835,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
|
||||
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
|
||||
/**
|
||||
* @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
|
||||
* conversion data)
|
||||
*/
|
||||
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
|
||||
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -683,8 +855,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
|
||||
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
|
||||
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
|
||||
continuous mode (all conversions of OVS ratio are done from 1 trigger) */
|
||||
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
|
||||
discontinuous mode (each conversion of OVS ratio needs a trigger) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -692,8 +866,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
|
||||
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
|
||||
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
|
||||
during injection sequence */
|
||||
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during
|
||||
injection sequence */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -701,16 +877,21 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/** @defgroup ADC_Event_type ADC Event type
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @note Analog watchdog 1 is available on all stm32 series
|
||||
* Analog watchdog 2 and 3 are not available on all series
|
||||
*/
|
||||
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
|
||||
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
|
||||
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
|
||||
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
|
||||
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
|
||||
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
|
||||
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
|
||||
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
|
||||
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
|
||||
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
|
||||
with other STM32 devices having only one analog watchdog */
|
||||
|
||||
/** @defgroup ADC_interrupts_definition ADC interrupts definition
|
||||
* @{
|
||||
@ -723,11 +904,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
|
||||
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
|
||||
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
|
||||
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
|
||||
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
|
||||
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog
|
||||
watchdog) */
|
||||
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog
|
||||
watchdog) */
|
||||
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
|
||||
|
||||
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
|
||||
#define ADC_IT_AWD ADC_IT_AWD1 /*!< Analog watchdog 1 interrupt source: naming for compatibility
|
||||
with other STM32 series having only one analog watchdog */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -748,7 +932,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
|
||||
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
|
||||
#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other
|
||||
STM32 series having only one analog watchdog */
|
||||
|
||||
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
|
||||
ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
|
||||
@ -829,7 +1014,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/**
|
||||
* @brief Verify the length of the scheduled regular conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
|
||||
* or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
|
||||
|
||||
@ -837,7 +1023,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
/**
|
||||
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
|
||||
* @param NUMBER number of scheduled regular conversions in discontinuous mode.
|
||||
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
|
||||
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
|
||||
* or RESET (NUMBER is null or too large)
|
||||
*/
|
||||
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
|
||||
|
||||
@ -1261,7 +1448,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
|
||||
* (6) On STM32L4, parameter available on devices with several ADC instances.\n
|
||||
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
|
||||
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
|
||||
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
|
||||
* 4.21 Ms/s)).\n
|
||||
* (1, 2, 3, 4) For ADC channel read back from ADC register,
|
||||
* comparison with internal channel parameter to be done
|
||||
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
|
||||
@ -1324,7 +1512,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
||||
* (6) On STM32L4, parameter available on devices with several ADC instances.\n
|
||||
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
|
||||
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
|
||||
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
|
||||
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
|
||||
* connected to a GPIO pin).
|
||||
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
|
||||
*/
|
||||
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
|
||||
@ -1668,11 +1857,15 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
|
||||
* @note ADC measurement data must correspond to a resolution of 12bits
|
||||
* (full scale digital value 4095). If not the case, the data must be
|
||||
* preliminarily rescaled to an equivalent resolution of 12 bits.
|
||||
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
|
||||
* On STM32L4, refer to device datasheet parameter "Avg_Slope".
|
||||
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
|
||||
* On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
|
||||
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
|
||||
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
|
||||
(unit: uV/DegCelsius).
|
||||
* On STM32L4, refer to device datasheet parameter "Avg_Slope".
|
||||
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
|
||||
temperature and Vref+ defined in parameters below) (unit: mV).
|
||||
* On STM32L4, refer to device datasheet parameter "V30"
|
||||
(corresponding to TS_CAL1).
|
||||
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
|
||||
parameter above) is corresponding (unit: mV)
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
|
||||
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
|
||||
@ -1753,7 +1946,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
|
||||
@ -1770,8 +1963,9 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
|
||||
const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1781,8 +1975,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana
|
||||
/** @addtogroup ADC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1792,7 +1986,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
@ -55,125 +55,190 @@ typedef struct
|
||||
/**
|
||||
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
|
||||
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
|
||||
* InjectedOffsetNumber, InjectedOffset
|
||||
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
|
||||
* InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
|
||||
* InjecOversamplingMode, InjecOversampling.
|
||||
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
|
||||
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
|
||||
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
|
||||
* 'InjectedSingleDiff')
|
||||
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
|
||||
* without conversion on going on injected group.
|
||||
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
|
||||
* ADC enabled without conversion on going on regular and injected groups.
|
||||
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
|
||||
* 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
|
||||
* on ADC groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
|
||||
Note: Depending on devices and ADC instances, some channels may not be
|
||||
available on device package pins. Refer to device datasheet for
|
||||
channels availability. */
|
||||
|
||||
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
|
||||
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
|
||||
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions adjusted) */
|
||||
Note: to disable a channel or change order of conversion sequencer,
|
||||
rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions
|
||||
adjusted) */
|
||||
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles.
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
|
||||
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values. */
|
||||
Caution: This parameter applies to a channel that can be used in a
|
||||
regular and/or injected group. It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt, ...),
|
||||
sampling time constraints must be respected (sampling time can be
|
||||
adjusted in function of ADC clock frequency and sampling time
|
||||
setting). Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
|
||||
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
|
||||
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
|
||||
of another parameter update on the fly) */
|
||||
In differential mode: Differential measurement is between the selected
|
||||
channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured
|
||||
automatically.
|
||||
This parameter must be a value of
|
||||
@ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
|
||||
Caution: This parameter applies to a channel that can be used in a
|
||||
regular and/or injected group. It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is
|
||||
available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel
|
||||
'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error
|
||||
reporting (as it can be the expected behavior in case of another
|
||||
parameter update on the fly) */
|
||||
|
||||
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
|
||||
Caution: Only one offset is allowed per channel. This parameter
|
||||
overwrites the last setting. */
|
||||
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
|
||||
parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
|
||||
0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going
|
||||
on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a
|
||||
conversion). */
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group
|
||||
injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter
|
||||
'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
|
||||
injected group can impact the configuration of other channels previously
|
||||
set. */
|
||||
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
|
||||
is performed in Complete-sequence/Discontinuous-sequence
|
||||
(main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter
|
||||
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion).
|
||||
Note: For injected group, discontinuous mode converts the sequence
|
||||
channel by channel (discontinuous length fixed to 1 rank).
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set. */
|
||||
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion
|
||||
after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
Note: To use Automatic injected conversion, discontinuous mode must
|
||||
be disabled ('DiscontinuousConvMode' and
|
||||
'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external
|
||||
triggers must be disabled ('ExternalTrigInjecConv' set to
|
||||
ADC_INJECTED_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in
|
||||
normal mode (single shot) JAUTO will be stopped upon DMA transfer
|
||||
complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in
|
||||
circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
|
||||
on injected group can impact the configuration of other channels
|
||||
previously set. */
|
||||
|
||||
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
|
||||
new injected context is set when queue is full, error is triggered by interruption and through function
|
||||
If context queue is enabled, injected sequencer&channels configurations
|
||||
are queued on up to 2 contexts. If a
|
||||
new injected context is set when queue is full, error is triggered by
|
||||
interruption and through function
|
||||
'HAL_ADCEx_InjectedQueueOverflowCallback'.
|
||||
Caution: This feature request that the sequence is fully configured before injected conversion start.
|
||||
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
|
||||
Caution: This feature request that the sequence is fully configured
|
||||
before injected conversion start.
|
||||
Therefore, configure channels with as many calls to
|
||||
HAL_ADCEx_InjectedConfigChannel() as the
|
||||
'InjectedNbrOfConversion' parameter.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion). */
|
||||
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_source.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of
|
||||
injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
|
||||
and software trigger is used instead.
|
||||
This parameter can be a value of
|
||||
@ref ADC_injected_external_trigger_source.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
|
||||
on injected group can impact the configuration of other channels
|
||||
previously set. */
|
||||
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
|
||||
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
|
||||
is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
Note: This parameter can be modified only if there is no
|
||||
conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
|
||||
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
Caution: this setting overwrites the previous oversampling
|
||||
configuration if oversampling already enabled.
|
||||
Note: This parameter can be modified only if there is no
|
||||
conversion is ongoing (both ADSTART and JADSTART cleared).*/
|
||||
} ADC_InjectionConfTypeDef;
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Structure definition of ADC multimode
|
||||
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
|
||||
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
|
||||
* (both Master and Slave ADCs).
|
||||
* Both Master and Slave ADCs must be disabled.
|
||||
*/
|
||||
typedef struct
|
||||
@ -182,7 +247,8 @@ typedef struct
|
||||
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
|
||||
|
||||
uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
|
||||
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
|
||||
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
|
||||
(one DMA channel for both ADC, DMA of ADC master).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
|
||||
|
||||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
@ -207,23 +273,40 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion
|
||||
trigger software start */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 TRGO2. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM2 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM2 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM4 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM6 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 TRGO2. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM15 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: external interrupt line 15. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -231,10 +314,14 @@ typedef struct
|
||||
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger
|
||||
disabled (SW start)*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger
|
||||
polarity set to rising edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger
|
||||
polarity set to falling edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger
|
||||
polarity set to both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -242,8 +329,8 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
|
||||
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
|
||||
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */
|
||||
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -251,11 +338,20 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
|
||||
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
|
||||
ADC channel */
|
||||
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -275,21 +371,33 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
|
||||
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
|
||||
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
|
||||
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
|
||||
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
|
||||
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
|
||||
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled
|
||||
(ADC independent mode) */
|
||||
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular
|
||||
simultaneous */
|
||||
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined
|
||||
group regular interleaved */
|
||||
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group
|
||||
injected simultaneous */
|
||||
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group
|
||||
injected alternate trigger. Works only with external triggers (not internal
|
||||
SW start) */
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
|
||||
group regular simultaneous + group injected simultaneous */
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
|
||||
group regular simultaneous + group injected alternate trigger */
|
||||
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
|
||||
group regular interleaved + group injected simultaneous */
|
||||
|
||||
/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
|
||||
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
|
||||
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
|
||||
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own
|
||||
DMA channel */
|
||||
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC,
|
||||
DMA of ADC master) for 12 and 10 bits resolution */
|
||||
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC,
|
||||
DMA of ADC master) for 8 and 6 bits resolution */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -297,18 +405,30 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
|
||||
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two
|
||||
sampling phases: 1 ADC clock cycle */
|
||||
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 2 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 3 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 4 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 5 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 6 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 7 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 8 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 9 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 10 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 11 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 12 ADC clock cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -321,9 +441,11 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
|
||||
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
|
||||
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
|
||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on
|
||||
all STM32 devices) */
|
||||
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on
|
||||
all STM32 devices) */
|
||||
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -386,8 +508,12 @@ typedef struct
|
||||
/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
|
||||
#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
|
||||
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred
|
||||
by DFSDM. */
|
||||
#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred
|
||||
to DFSDM for post processing. The ADC conversion data format must be 16-bit
|
||||
signed and right aligned, refer to reference manual.
|
||||
DFSDM transfer cannot be used if DMA transfer is enabled. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -470,15 +596,16 @@ typedef struct
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) \
|
||||
( ( ( ((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
SET \
|
||||
: \
|
||||
RESET \
|
||||
SET \
|
||||
: \
|
||||
RESET \
|
||||
)
|
||||
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
|
||||
#elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
|
||||
#endif /* (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
|
||||
#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) ||
|
||||
defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
@ -486,36 +613,41 @@ typedef struct
|
||||
* @param __RANKNB__ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
|
||||
& ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
|
||||
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
|
||||
((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
|
||||
<< ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
|
||||
|
||||
/**
|
||||
* @brief Configure ADC injected context queue
|
||||
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
|
||||
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
|
||||
((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for injected group
|
||||
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
|
||||
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
|
||||
((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for regular group
|
||||
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
|
||||
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
|
||||
((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the number of discontinuous conversions for regular group.
|
||||
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
|
||||
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
|
||||
(((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC auto delay mode.
|
||||
@ -557,8 +689,8 @@ typedef struct
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\
|
||||
& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
|
||||
#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) \
|
||||
(((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
|
||||
|
||||
/**
|
||||
* @brief Calibration factor in differential mode to be retrieved from calibration register.
|
||||
@ -661,12 +793,15 @@ typedef struct
|
||||
* @brief Set handle instance of the ADC slave associated to the ADC master.
|
||||
* @param __HANDLE_MASTER__ ADC master handle.
|
||||
* @param __HANDLE_SLAVE__ ADC slave handle.
|
||||
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
|
||||
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is
|
||||
* set to NULL.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
|
||||
( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
|
||||
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
|
||||
( (((__HANDLE_MASTER__)->Instance == ADC1)) ? \
|
||||
((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
|
||||
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) ||
|
||||
defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
|
||||
|
||||
|
||||
/**
|
||||
@ -681,7 +816,11 @@ typedef struct
|
||||
/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
|
||||
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\
|
||||
|| (((__HANDLE__)->Instance) == ADC3))
|
||||
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
|
||||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
|
||||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
|
||||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the battery voltage VBAT.
|
||||
@ -695,7 +834,11 @@ typedef struct
|
||||
/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\
|
||||
|| (((__HANDLE__)->Instance) == ADC3))
|
||||
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
|
||||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
|
||||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
|
||||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
|
||||
@ -708,7 +851,8 @@ typedef struct
|
||||
/**
|
||||
* @brief Verify the length of scheduled injected conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
|
||||
* or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
|
||||
@ -892,7 +1036,10 @@ typedef struct
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
|
||||
#endif /* (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
#endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) ||
|
||||
defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) ||
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
|
||||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting in differential mode.
|
||||
@ -949,7 +1096,11 @@ typedef struct
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) )))
|
||||
#endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) ||
|
||||
defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) ||
|
||||
defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) ||
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) ||
|
||||
defined (STM32L4S7xx) || defined (STM32L4S9xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC single-ended input or differential mode setting.
|
||||
@ -1071,13 +1222,13 @@ typedef struct
|
||||
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
|
||||
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC conversion (regular or injected or both).
|
||||
@ -1191,7 +1342,7 @@ typedef struct
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
|
||||
uint32_t CalibrationFactor);
|
||||
|
||||
@ -1208,11 +1359,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
|
||||
/* ADC multimode */
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
|
||||
@ -1222,11 +1373,11 @@ void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *h
|
||||
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC group regular conversions stop */
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
@ -1238,10 +1389,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
|
||||
ADC_InjectionConfTypeDef *sConfigInjected);
|
||||
const ADC_InjectionConfTypeDef *pConfigInjected);
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
|
||||
const ADC_MultiModeTypeDef *pMultimode);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
|
||||
|
||||
@ -209,7 +209,11 @@ typedef struct
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CAN_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
||||
@ -296,6 +296,8 @@ void HAL_SYSTICK_Callback(void);
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
|
||||
@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -54,7 +54,9 @@ typedef enum
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#define STM32L4xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
@ -82,7 +82,7 @@ typedef enum
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
@ -91,7 +91,7 @@ typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
@ -104,7 +104,7 @@ typedef enum
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
@ -121,13 +121,13 @@ typedef struct __DMA_HandleTypeDef
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
@ -150,7 +150,7 @@ typedef struct __DMA_HandleTypeDef
|
||||
|
||||
#endif /* DMAMUX1 */
|
||||
|
||||
}DMA_HandleTypeDef;
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -753,7 +753,7 @@ typedef struct __DMA_HandleTypeDef
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -762,13 +762,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
|
||||
@ -69,7 +69,7 @@ typedef struct
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
|
||||
}HAL_DMA_MuxSyncConfigTypeDef;
|
||||
} HAL_DMA_MuxSyncConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
@ -77,7 +77,7 @@ typedef struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||
@ -86,7 +86,7 @@ typedef struct
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -211,10 +211,10 @@ typedef struct
|
||||
*/
|
||||
|
||||
/* ------------------------- REQUEST -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
|
||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
/* ------------------------- SYNCHRO -----------------------------------------*/
|
||||
|
||||
@ -783,6 +783,7 @@
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
|
||||
|
||||
@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
@ -4441,7 +4441,7 @@ typedef struct
|
||||
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
||||
|
||||
@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef
|
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
}while(0U)
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
#define SPI_RESET_CRC(__HANDLE__) \
|
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -48,7 +48,7 @@ extern "C" {
|
||||
/** @addtogroup SPIEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,439 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l4xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32L4xx_HAL_TIM_EX_H
|
||||
#define STM32L4xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32L4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Break/Break2 input configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Specifies the source of the timer break input.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source */
|
||||
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
uint32_t Polarity; /*!< Specifies the break input source polarity.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
|
||||
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
|
||||
} TIMEx_BreakInputConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#if defined (ADC3)
|
||||
#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
|
||||
#endif /* ADC3 */
|
||||
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */
|
||||
#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */
|
||||
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
|
||||
#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
|
||||
#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */
|
||||
#else
|
||||
#if defined(STM32L471xx)
|
||||
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
|
||||
#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */
|
||||
#else
|
||||
#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
|
||||
#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
|
||||
#endif /* STM32L471xx */
|
||||
#endif /* USB_OTG_FS */
|
||||
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
|
||||
#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */
|
||||
#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */
|
||||
#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */
|
||||
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
|
||||
#endif /* COMP2 */
|
||||
|
||||
#if defined (TIM3)
|
||||
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */
|
||||
#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */
|
||||
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
|
||||
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
|
||||
#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
|
||||
#endif /* TIM3 */
|
||||
|
||||
#if defined (TIM8)
|
||||
#if defined(ADC2) && defined(ADC3)
|
||||
#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
|
||||
#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
|
||||
#endif /* ADC2 && ADC3 */
|
||||
|
||||
#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */
|
||||
#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */
|
||||
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
|
||||
#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */
|
||||
#endif /* TIM8 */
|
||||
|
||||
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */
|
||||
#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */
|
||||
#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */
|
||||
#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
|
||||
#if defined (TIM3)
|
||||
#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
|
||||
#endif /* TIM3 */
|
||||
#if defined (TIM4)
|
||||
#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
|
||||
#endif /* TIM4 */
|
||||
|
||||
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
|
||||
#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */
|
||||
#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */
|
||||
#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
|
||||
#if defined (TIM16_OR1_TI1_RMP_2)
|
||||
#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */
|
||||
#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
|
||||
#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
|
||||
#endif /* TIM16_OR1_TI1_RMP_2 */
|
||||
|
||||
#if defined (TIM17)
|
||||
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
|
||||
#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */
|
||||
#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */
|
||||
#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
|
||||
#endif /* TIM17 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
|
||||
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
|
||||
#if defined (DFSDM1_Channel0)
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
#endif /* DFSDM1_Channel0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
|
||||
|
||||
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||||
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||||
|
||||
#if defined (DFSDM1_Channel0)
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
|
||||
#else
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
|
||||
#endif /* DFSDM1_Channel0 */
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||||
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
|
||||
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
const TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
|
||||
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32L4xx_HAL_TIM_EX_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -586,7 +586,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
@ -408,7 +408,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
@ -439,7 +439,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -454,7 +454,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
|
||||
MODIFY_REG(CRS->CFGR,
|
||||
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
|
||||
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
|
||||
|
||||
@ -358,7 +358,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
|
||||
#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
|
||||
#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -745,7 +745,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_TRIG_SOFTWARE
|
||||
@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param WaveAutoGeneration This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
|
||||
@ -803,7 +803,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
|
||||
@ -832,7 +832,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param NoiseLFSRMask This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
|
||||
@ -866,7 +866,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
|
||||
@ -904,7 +904,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param TriangleAmplitude This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
|
||||
@ -939,7 +939,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
|
||||
@ -973,7 +973,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
|
||||
* - @ref LL_DAC_SetOutputBuffer()
|
||||
* - @ref LL_DAC_SetOutputMode()
|
||||
* - @ref LL_DAC_SetOutputConnection()
|
||||
* @note On this STM32 serie, output connection depends on output mode
|
||||
* @note On this STM32 series, output connection depends on output mode
|
||||
* (normal or sample and hold) and output buffer state.
|
||||
* - if output connection is set to internal path and output buffer
|
||||
* is enabled (whatever output mode):
|
||||
@ -996,7 +996,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param OutputMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
|
||||
@ -1033,7 +1033,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param OutputMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
|
||||
@ -1056,7 +1056,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
|
||||
@ -1071,7 +1071,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch
|
||||
|
||||
/**
|
||||
* @brief Set the output buffer for the selected DAC channel.
|
||||
* @note On this STM32 serie, when buffer is enabled, its offset can be
|
||||
* @note On this STM32 series, when buffer is enabled, its offset can be
|
||||
* trimmed: factory calibration default values can be
|
||||
* replaced by user trimming values, using function
|
||||
* @ref LL_DAC_SetTrimmingValue().
|
||||
@ -1082,7 +1082,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param OutputBuffer This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
|
||||
@ -1105,7 +1105,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
|
||||
@ -1120,7 +1120,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
|
||||
/**
|
||||
* @brief Set the output connection for the selected DAC channel.
|
||||
* @note On this STM32 serie, output connection depends on output mode (normal or
|
||||
* @note On this STM32 series, output connection depends on output mode (normal or
|
||||
* sample and hold) and output buffer state.
|
||||
* - if output connection is set to internal path and output buffer
|
||||
* is enabled (whatever output mode):
|
||||
@ -1137,7 +1137,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param OutputConnection This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
|
||||
@ -1153,7 +1153,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
|
||||
/**
|
||||
* @brief Get the output connection for the selected DAC channel.
|
||||
* @note On this STM32 serie, output connection depends on output mode (normal or
|
||||
* @note On this STM32 series, output connection depends on output mode (normal or
|
||||
* sample and hold) and output buffer state.
|
||||
* - if output connection is set to internal path and output buffer
|
||||
* is enabled (whatever output mode):
|
||||
@ -1170,7 +1170,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
|
||||
@ -1197,7 +1197,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
* @retval None
|
||||
@ -1221,7 +1221,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
*/
|
||||
@ -1242,7 +1242,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, ui
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
* @retval None
|
||||
@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
*/
|
||||
@ -1285,7 +1285,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
* @retval None
|
||||
@ -1307,7 +1307,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
@ -1337,7 +1337,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, u
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1358,7 +1358,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
@ -1415,7 +1415,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param Register This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
|
||||
@ -1450,7 +1450,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1469,7 +1469,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1489,7 +1489,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
@ -1517,7 +1517,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1536,7 +1536,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1556,7 +1556,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
@ -1587,7 +1587,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
@ -1608,7 +1608,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
@ -1633,7 +1633,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval None
|
||||
@ -1658,7 +1658,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
* @retval None
|
||||
@ -1745,7 +1745,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 serie, parameter not available on all devices.
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
*/
|
||||
|
||||
@ -70,7 +70,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] =
|
||||
#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
|
||||
|
||||
/* Defines used for the bit position in the register and perform offsets */
|
||||
#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U))
|
||||
#define DMA_POSITION_CSELR_CXS(Channel) POSITION_VAL(DMA_CSELR_C1S << (((Channel)*4U) & 0x1FU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -593,7 +593,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
||||
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
|
||||
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -752,8 +752,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
|
||||
PeriphOrM2MSrcIncMode);
|
||||
}
|
||||
|
||||
@ -848,7 +848,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha
|
||||
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
|
||||
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
|
||||
PeriphOrM2MSrcDataSize);
|
||||
}
|
||||
|
||||
@ -1512,7 +1512,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha
|
||||
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
|
||||
{
|
||||
MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
|
||||
DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
|
||||
DMA_CSELR_C1S << (((Channel) * 4U) & 0x1FU), PeriphRequest << DMA_POSITION_CSELR_CXS(Channel));
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1546,7 +1546,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
|
||||
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
|
||||
{
|
||||
return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
|
||||
DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS);
|
||||
DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS(Channel));
|
||||
}
|
||||
|
||||
#endif /* DMAMUX1 */
|
||||
@ -2225,7 +2225,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
|
||||
}
|
||||
|
||||
@ -2347,7 +2347,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
||||
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
|
||||
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2368,7 +2368,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
||||
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
|
||||
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Chann
|
||||
{
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
||||
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
|
||||
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -968,7 +968,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM
|
||||
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
|
||||
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint
|
||||
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
|
||||
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1207,7 +1207,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx
|
||||
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
|
||||
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1606,7 +1606,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA
|
||||
* @param DMAMUXx DMAMUXx DMAMUXx Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)
|
||||
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
|
||||
@ -1902,7 +1902,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin
|
||||
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
|
||||
return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui
|
||||
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
|
||||
{
|
||||
(void)(DMAMUXx);
|
||||
return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL);
|
||||
return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
|
||||
}
|
||||
@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
{
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
|
||||
}
|
||||
@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
|
||||
}
|
||||
@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
|
||||
}
|
||||
@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
|
||||
}
|
||||
@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
|
||||
}
|
||||
@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
|
||||
}
|
||||
@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
|
||||
}
|
||||
@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
|
||||
}
|
||||
@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
|
||||
}
|
||||
@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
|
||||
}
|
||||
@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
|
||||
(ClockTimeout)) ? 1UL : 0UL);
|
||||
@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
|
||||
}
|
||||
@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
|
||||
* @arg @ref LL_I2C_REQUEST_WRITE
|
||||
* @arg @ref LL_I2C_REQUEST_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
|
||||
}
|
||||
@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
|
||||
}
|
||||
@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
||||
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
|
||||
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
|
||||
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
||||
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
|
||||
* @arg @ref LL_I2C_DIRECTION_WRITE
|
||||
* @arg @ref LL_I2C_DIRECTION_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
|
||||
}
|
||||
@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
|
||||
}
|
||||
@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
|
||||
}
|
||||
@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
|
||||
}
|
||||
@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
|
||||
|
||||
|
||||
@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->PR));
|
||||
}
|
||||
@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->WINR));
|
||||
}
|
||||
@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
@ -435,21 +435,21 @@ typedef struct
|
||||
/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
|
||||
* @{
|
||||
*/
|
||||
#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
|
||||
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
|
||||
#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
|
||||
#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
|
||||
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
|
||||
#define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
|
||||
#if defined(RCC_CCIPR_I2C2SEL)
|
||||
#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
|
||||
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
|
||||
#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
|
||||
#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
|
||||
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
|
||||
#define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
|
||||
#endif /* RCC_CCIPR_I2C2SEL */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
|
||||
#define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
|
||||
#if defined(RCC_CCIPR2_I2C4SEL)
|
||||
#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
|
||||
#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
|
||||
#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
|
||||
#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
|
||||
#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
|
||||
#define LL_RCC_I2C4_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
|
||||
#endif /* RCC_CCIPR2_I2C4SEL */
|
||||
/**
|
||||
* @}
|
||||
@ -705,13 +705,13 @@ typedef struct
|
||||
/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
|
||||
* @{
|
||||
*/
|
||||
#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
|
||||
#define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
|
||||
#if defined(RCC_CCIPR_I2C2SEL)
|
||||
#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
|
||||
#define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
|
||||
#endif /* RCC_CCIPR_I2C2SEL */
|
||||
#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
|
||||
#define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
|
||||
#if defined(RCC_CCIPR2_I2C4SEL)
|
||||
#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
|
||||
#define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
|
||||
#endif /* RCC_CCIPR2_I2C4SEL */
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -55,53 +55,66 @@ typedef struct
|
||||
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetTransferDirection().*/
|
||||
|
||||
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
|
||||
This parameter can be a value of @ref SPI_LL_EC_MODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetMode().*/
|
||||
|
||||
uint32_t DataWidth; /*!< Specifies the SPI data width.
|
||||
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetDataWidth().*/
|
||||
|
||||
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetClockPolarity().*/
|
||||
|
||||
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_LL_EC_PHASE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetClockPhase().*/
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
|
||||
or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetNSSMode().*/
|
||||
|
||||
uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
|
||||
uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
|
||||
to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
|
||||
@note The communication clock is derived from the master clock. The slave clock does not need to be set.
|
||||
@note The communication clock is derived from the master clock.
|
||||
The slave clock does not need to be set.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetBaudRatePrescaler().*/
|
||||
|
||||
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetTransferBitOrder().*/
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
|
||||
|
||||
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
|
||||
This feature can be modified afterwards using unitary
|
||||
function @ref LL_SPI_SetCRCPolynomial().*/
|
||||
|
||||
} LL_SPI_InitTypeDef;
|
||||
|
||||
@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
|
||||
* @arg @ref LL_SPI_MODE_MASTER
|
||||
* @arg @ref LL_SPI_MODE_SLAVE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
|
||||
}
|
||||
@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
|
||||
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
|
||||
* @arg @ref LL_SPI_PROTOCOL_TI
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
|
||||
}
|
||||
@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase
|
||||
* @arg @ref LL_SPI_PHASE_1EDGE
|
||||
* @arg @ref LL_SPI_PHASE_2EDGE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
|
||||
}
|
||||
@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
|
||||
* @arg @ref LL_SPI_POLARITY_LOW
|
||||
* @arg @ref LL_SPI_POLARITY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
|
||||
}
|
||||
@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau
|
||||
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
|
||||
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
|
||||
}
|
||||
@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
|
||||
* @arg @ref LL_SPI_LSB_FIRST
|
||||
* @arg @ref LL_SPI_MSB_FIRST
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
|
||||
}
|
||||
@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_RX
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_TX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
|
||||
}
|
||||
@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
|
||||
* @arg @ref LL_SPI_DATAWIDTH_15BIT
|
||||
* @arg @ref LL_SPI_DATAWIDTH_16BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
|
||||
}
|
||||
@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres
|
||||
* @arg @ref LL_SPI_RX_FIFO_TH_HALF
|
||||
* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
|
||||
}
|
||||
@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
|
||||
* @arg @ref LL_SPI_CRC_8BIT
|
||||
* @arg @ref LL_SPI_CRC_16BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
|
||||
}
|
||||
@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->CRCPR));
|
||||
}
|
||||
@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->RXCRCR));
|
||||
}
|
||||
@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->TXCRCR));
|
||||
}
|
||||
@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
||||
* @arg @ref LL_SPI_NSS_HARD_INPUT
|
||||
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
||||
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
||||
@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||
* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
|
||||
* @arg @ref LL_SPI_RX_FIFO_FULL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
|
||||
}
|
||||
@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
|
||||
* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
|
||||
* @arg @ref LL_SPI_TX_FIFO_FULL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
|
||||
}
|
||||
@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
|
||||
|
||||
/**
|
||||
* @brief Enable error interrupt
|
||||
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
||||
* @note This bit controls the generation of an interrupt when an error condition
|
||||
* occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
||||
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
|
||||
|
||||
/**
|
||||
* @brief Disable error interrupt
|
||||
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
||||
* @note This bit controls the generation of an interrupt when an error condition
|
||||
* occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
||||
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
|
||||
* @param SPIx SPI Instance
|
||||
* @retval None
|
||||
@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
|
||||
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
||||
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
|
||||
}
|
||||
@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
|
||||
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
||||
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
|
||||
}
|
||||
@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t) &(SPIx->DR);
|
||||
}
|
||||
@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
|
||||
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
|
||||
|
||||
|
||||
@ -60,6 +60,8 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */
|
||||
|
||||
/**
|
||||
* @brief Power-down in Run mode Flash key
|
||||
*/
|
||||
@ -154,22 +156,22 @@ extern "C" {
|
||||
/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
|
||||
#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
|
||||
#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
|
||||
#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
|
||||
#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -772,7 +774,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
|
||||
{
|
||||
MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
|
||||
MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << POSITION_VAL((Line >> LL_EXTI_REGISTER_PINPOS_SHFT)));
|
||||
}
|
||||
|
||||
/**
|
||||
@ -813,7 +815,7 @@ __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
|
||||
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
*/
|
||||
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
|
||||
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||
#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
|
||||
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|
||||
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
|
||||
@ -381,7 +381,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
|
||||
@ -220,11 +220,11 @@
|
||||
|
||||
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions HAL_ADC_RegisterCallback()
|
||||
Use Functions @ref HAL_ADC_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function HAL_ADC_RegisterCallback() allows to register following callbacks:
|
||||
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
|
||||
(+) ConvCpltCallback : ADC conversion complete callback
|
||||
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
|
||||
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
|
||||
@ -240,11 +240,11 @@
|
||||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
|
||||
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) ConvCpltCallback : ADC conversion complete callback
|
||||
@ -260,27 +260,27 @@
|
||||
(+) MspDeInitCallback : ADC Msp DeInit callback
|
||||
[..]
|
||||
|
||||
By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
|
||||
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
|
||||
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
|
||||
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
|
||||
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
|
||||
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
|
||||
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
|
||||
or HAL_ADC_Init() function.
|
||||
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
|
||||
or @ref HAL_ADC_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
|
||||
@ -312,10 +312,11 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
|
||||
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
|
||||
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
|
||||
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
|
||||
#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\
|
||||
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
|
||||
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
|
||||
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can
|
||||
be updated when no regular conversion is on-going */
|
||||
|
||||
/* Timeout values for ADC operations (enable settling time, */
|
||||
/* disable settling time, ...). */
|
||||
@ -393,11 +394,10 @@
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmpCFGR;
|
||||
uint32_t tmp_adc_reg_is_conversion_on_going;
|
||||
__IO uint32_t wait_loop_index = 0UL;
|
||||
uint32_t tmp_cfgr;
|
||||
uint32_t tmp_adc_is_conversion_on_going_regular;
|
||||
uint32_t tmp_adc_is_conversion_on_going_injected;
|
||||
__IO uint32_t wait_loop_index = 0UL;
|
||||
|
||||
/* Check ADC handle */
|
||||
if (hadc == NULL)
|
||||
@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
|
||||
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
|
||||
assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
|
||||
#endif
|
||||
#endif /* DFSDM */
|
||||
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
|
||||
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
||||
@ -516,10 +516,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
/* correctly completed and if there is no conversion on going on regular */
|
||||
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
|
||||
/* called to update a parameter on the fly). */
|
||||
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
||||
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
||||
|
||||
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
|
||||
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
|
||||
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
|
||||
)
|
||||
{
|
||||
/* Set ADC state */
|
||||
@ -566,15 +566,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
/* - overrun Init.Overrun */
|
||||
/* - discontinuous mode Init.DiscontinuousConvMode */
|
||||
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
|
||||
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
||||
hadc->Init.Overrun |
|
||||
hadc->Init.DataAlign |
|
||||
hadc->Init.Resolution |
|
||||
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
|
||||
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
||||
hadc->Init.Overrun |
|
||||
hadc->Init.DataAlign |
|
||||
hadc->Init.Resolution |
|
||||
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
|
||||
|
||||
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
||||
{
|
||||
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
|
||||
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
|
||||
}
|
||||
|
||||
/* Enable external trigger if trigger selection is different of software */
|
||||
@ -584,13 +584,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
/* software start. */
|
||||
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
||||
{
|
||||
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
||||
| hadc->Init.ExternalTrigConvEdge
|
||||
);
|
||||
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
||||
| hadc->Init.ExternalTrigConvEdge
|
||||
);
|
||||
}
|
||||
|
||||
/* Update Configuration Register CFGR */
|
||||
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
|
||||
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
|
||||
|
||||
/* Parameters update conditioned to ADC state: */
|
||||
/* Parameters that can be updated when ADC is disabled or enabled without */
|
||||
@ -598,17 +598,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
||||
/* - DMA continuous request Init.DMAContinuousRequests */
|
||||
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
|
||||
/* - Oversampling parameters Init.Oversampling */
|
||||
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
||||
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
||||
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
||||
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
||||
)
|
||||
{
|
||||
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
|
||||
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
||||
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
||||
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
|
||||
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
||||
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
||||
|
||||
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
|
||||
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
|
||||
|
||||
if (hadc->Init.OversamplingMode == ENABLE)
|
||||
{
|
||||
@ -1207,7 +1206,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
const ADC_TypeDef *tmpADC_Master;
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -1241,7 +1240,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Set ADC error code */
|
||||
/* Check if a conversion is on going on ADC group injected */
|
||||
@ -1310,7 +1309,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
||||
|
||||
/* Start ADC group regular conversion */
|
||||
LL_ADC_REG_StartConversion(hadc->Instance);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1398,7 +1397,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
const ADC_TypeDef *tmpADC_Master;
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -1458,7 +1457,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
||||
{
|
||||
tmp_Flag_End = (ADC_FLAG_EOC);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
}
|
||||
|
||||
/* Get tick count */
|
||||
@ -1531,7 +1530,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
||||
#else
|
||||
/* Retrieve handle ADC CFGR register */
|
||||
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Clear polled flag */
|
||||
if (tmp_Flag_End == ADC_FLAG_EOS)
|
||||
@ -1559,9 +1558,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
||||
* @param EventType the ADC event type.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
|
||||
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
|
||||
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
|
||||
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
|
||||
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
|
||||
* all STM32 series)
|
||||
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
|
||||
* all STM32 series)
|
||||
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
|
||||
* all STM32 series)
|
||||
* @arg @ref ADC_OVR_EVENT ADC Overrun event
|
||||
* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
|
||||
* @param Timeout Timeout value in millisecond.
|
||||
@ -1728,7 +1730,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
const ADC_TypeDef *tmpADC_Master;
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -1762,7 +1764,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Set ADC error code */
|
||||
/* Check if a conversion is on going on ADC group injected */
|
||||
@ -1904,7 +1906,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
||||
|
||||
/* Start ADC group regular conversion */
|
||||
LL_ADC_REG_StartConversion(hadc->Instance);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1987,7 +1989,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
|
||||
HAL_StatusTypeDef tmp_hal_status;
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -2031,7 +2033,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
|
||||
{
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check if a conversion is on going on ADC group injected */
|
||||
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
|
||||
@ -2100,7 +2102,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -2209,7 +2211,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
|
||||
* @param hadc ADC handle
|
||||
* @retval ADC group regular conversion data
|
||||
*/
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
|
||||
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -2237,7 +2239,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
const ADC_TypeDef *tmpADC_Master;
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -2301,7 +2303,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
||||
}
|
||||
#else
|
||||
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Carry on if continuous mode is disabled */
|
||||
if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
|
||||
@ -2391,7 +2393,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
||||
}
|
||||
#else
|
||||
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Disable interruption if no further conversion upcoming by injected */
|
||||
/* external trigger or by automatic injected conversion with regular */
|
||||
@ -2537,7 +2539,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
{
|
||||
/* Multimode not set or feature not available or ADC independent */
|
||||
if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
|
||||
@ -2693,10 +2695,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
|
||||
* The setting of these parameters is conditioned to ADC state:
|
||||
* Refer to comments of structure "ADC_ChannelConfTypeDef".
|
||||
* @param hadc ADC handle
|
||||
* @param sConfig Structure of ADC channel assigned to ADC group regular.
|
||||
* @param pConfig Structure of ADC channel assigned to ADC group regular.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmpOffsetShifted;
|
||||
@ -2707,24 +2709,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
||||
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
|
||||
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
|
||||
assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
|
||||
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
|
||||
assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
|
||||
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
|
||||
assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
|
||||
|
||||
/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
|
||||
ignored (considered as reset) */
|
||||
assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
|
||||
assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
|
||||
|
||||
/* Verification of channel number */
|
||||
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
|
||||
if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
|
||||
{
|
||||
assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
|
||||
assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
|
||||
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
@ -2738,37 +2740,40 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
#if !defined (USE_FULL_ASSERT)
|
||||
uint32_t config_rank = pConfig->Rank;
|
||||
/* Correspondence for compatibility with legacy definition of */
|
||||
/* sequencer ranks in direct number format. This correspondence can */
|
||||
/* be done only on ranks 1 to 5 due to literal values. */
|
||||
/* Note: Sequencer ranks in direct number format are no more used */
|
||||
/* and are detected by activating USE_FULL_ASSERT feature. */
|
||||
if (sConfig->Rank <= 5U)
|
||||
if (pConfig->Rank <= 5U)
|
||||
{
|
||||
switch (sConfig->Rank)
|
||||
switch (pConfig->Rank)
|
||||
{
|
||||
case 2U:
|
||||
sConfig->Rank = ADC_REGULAR_RANK_2;
|
||||
config_rank = ADC_REGULAR_RANK_2;
|
||||
break;
|
||||
case 3U:
|
||||
sConfig->Rank = ADC_REGULAR_RANK_3;
|
||||
config_rank = ADC_REGULAR_RANK_3;
|
||||
break;
|
||||
case 4U:
|
||||
sConfig->Rank = ADC_REGULAR_RANK_4;
|
||||
config_rank = ADC_REGULAR_RANK_4;
|
||||
break;
|
||||
case 5U:
|
||||
sConfig->Rank = ADC_REGULAR_RANK_5;
|
||||
config_rank = ADC_REGULAR_RANK_5;
|
||||
break;
|
||||
/* case 1U */
|
||||
default:
|
||||
sConfig->Rank = ADC_REGULAR_RANK_1;
|
||||
config_rank = ADC_REGULAR_RANK_1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, config_rank, pConfig->Channel);
|
||||
#else
|
||||
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
|
||||
#endif/* USE_FULL_ASSERT */
|
||||
|
||||
/* Parameters update conditioned to ADC state: */
|
||||
/* Parameters that can be updated when ADC is disabled or enabled without */
|
||||
@ -2783,10 +2788,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
{
|
||||
#if defined(ADC_SMPR1_SMPPLUS)
|
||||
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
|
||||
if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
|
||||
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
|
||||
|
||||
/* Set ADC sampling time common configuration */
|
||||
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
|
||||
@ -2794,26 +2799,26 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
else
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
|
||||
|
||||
/* Set ADC sampling time common configuration */
|
||||
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
|
||||
}
|
||||
#else
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
|
||||
#endif
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
|
||||
#endif /* ADC_SMPR1_SMPPLUS */
|
||||
|
||||
/* Configure the offset: offset enable/disable, channel, offset value */
|
||||
|
||||
/* Shift the offset with respect to the selected ADC resolution. */
|
||||
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
|
||||
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
|
||||
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
|
||||
|
||||
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
|
||||
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
|
||||
{
|
||||
/* Set ADC selected offset number */
|
||||
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
|
||||
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
|
||||
|
||||
}
|
||||
else
|
||||
@ -2821,22 +2826,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
/* Scan each offset register to check if the selected channel is targeted. */
|
||||
/* If this is the case, the corresponding offset number is disabled. */
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
@ -2849,16 +2854,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Set mode single-ended or differential input of the selected ADC channel */
|
||||
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
|
||||
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
|
||||
|
||||
/* Configuration of differential mode */
|
||||
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
|
||||
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
||||
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
|
||||
sConfig->SamplingTime);
|
||||
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
|
||||
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
|
||||
+ 1UL) & 0x1FUL)),
|
||||
pConfig->SamplingTime);
|
||||
}
|
||||
|
||||
}
|
||||
@ -2869,13 +2876,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
/* Note: these internal measurement paths can be disabled using */
|
||||
/* HAL_ADC_DeInit(). */
|
||||
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
|
||||
{
|
||||
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
|
||||
/* If the requested internal measurement path has already been enabled, */
|
||||
/* bypass the configuration processing. */
|
||||
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
||||
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
||||
{
|
||||
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
||||
@ -2895,7 +2902,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
||||
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
||||
{
|
||||
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
||||
{
|
||||
@ -2903,7 +2911,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
||||
}
|
||||
}
|
||||
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
|
||||
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
||||
{
|
||||
if (ADC_VREFINT_INSTANCE(hadc))
|
||||
@ -2950,28 +2958,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
||||
* @note On this STM32 series, analog watchdog thresholds cannot be modified
|
||||
* while ADC conversion is on going.
|
||||
* @param hadc ADC handle
|
||||
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
|
||||
* @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmpAWDHighThresholdShifted;
|
||||
uint32_t tmpAWDLowThresholdShifted;
|
||||
uint32_t tmp_awd_high_threshold_shifted;
|
||||
uint32_t tmp_awd_low_threshold_shifted;
|
||||
uint32_t tmp_adc_is_conversion_on_going_regular;
|
||||
uint32_t tmp_adc_is_conversion_on_going_injected;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
|
||||
|
||||
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
|
||||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
|
||||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
|
||||
if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
|
||||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
|
||||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
|
||||
{
|
||||
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
|
||||
assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
|
||||
}
|
||||
|
||||
/* Verify thresholds range */
|
||||
@ -2980,14 +2988,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
/* Case of oversampling enabled: depending on ratio and shift configuration,
|
||||
analog watchdog thresholds can be higher than ADC resolution.
|
||||
Verify if thresholds are within maximum thresholds range. */
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Verify if thresholds are within the selected ADC resolution */
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
@ -3005,26 +3013,29 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
)
|
||||
{
|
||||
/* Analog watchdog configuration */
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
{
|
||||
/* Configuration of analog watchdog: */
|
||||
/* - Set the analog watchdog enable mode: one or overall group of */
|
||||
/* channels, on groups regular and-or injected. */
|
||||
switch (AnalogWDGConfig->WatchdogMode)
|
||||
switch (pAnalogWDGConfig->WatchdogMode)
|
||||
{
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REG:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_REGULAR));
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
|
||||
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_REGULAR));
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_INJECTED));
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
|
||||
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_INJECTED));
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_REGULAR_INJECTED));
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
|
||||
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
|
||||
LL_ADC_GROUP_REGULAR_INJECTED));
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_ALL_REG:
|
||||
@ -3047,12 +3058,12 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
/* Shift the offset in function of the selected ADC resolution: */
|
||||
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
|
||||
/* are set to 0 */
|
||||
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
|
||||
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
|
||||
tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
|
||||
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
|
||||
|
||||
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
|
||||
tmpAWDLowThresholdShifted);
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
|
||||
tmp_awd_low_threshold_shifted);
|
||||
|
||||
/* Update state, clear previous result related to AWD1 */
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
|
||||
@ -3064,7 +3075,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
LL_ADC_ClearFlag_AWD1(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD1(hadc->Instance);
|
||||
}
|
||||
@ -3076,44 +3087,47 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
|
||||
else
|
||||
{
|
||||
switch (AnalogWDGConfig->WatchdogMode)
|
||||
switch (pAnalogWDGConfig->WatchdogMode)
|
||||
{
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REG:
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
|
||||
/* Update AWD by bitfield to keep the possibility to monitor */
|
||||
/* several channels by successive calls of this function. */
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
{
|
||||
SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
|
||||
SET_BIT(hadc->Instance->AWD2CR,
|
||||
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
|
||||
SET_BIT(hadc->Instance->AWD3CR,
|
||||
(1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
|
||||
}
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_ALL_REG:
|
||||
case ADC_ANALOGWATCHDOG_ALL_INJEC:
|
||||
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
|
||||
pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
|
||||
break;
|
||||
|
||||
default: /* ADC_ANALOGWATCHDOG_NONE */
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Shift the thresholds in function of the selected ADC resolution */
|
||||
/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
|
||||
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
|
||||
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
|
||||
tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
|
||||
tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
|
||||
|
||||
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
|
||||
tmpAWDLowThresholdShifted);
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
|
||||
tmp_awd_low_threshold_shifted);
|
||||
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
{
|
||||
/* Update state, clear previous result related to AWD2 */
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
|
||||
@ -3125,7 +3139,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
LL_ADC_ClearFlag_AWD2(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD2(hadc->Instance);
|
||||
}
|
||||
@ -3134,7 +3148,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
LL_ADC_DisableIT_AWD2(hadc->Instance);
|
||||
}
|
||||
}
|
||||
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
|
||||
/* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
|
||||
else
|
||||
{
|
||||
/* Update state, clear previous result related to AWD3 */
|
||||
@ -3147,7 +3161,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
LL_ADC_ClearFlag_AWD3(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD3(hadc->Instance);
|
||||
}
|
||||
@ -3207,7 +3221,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
||||
* @param hadc ADC handle
|
||||
* @retval ADC handle state (bitfield on 32 bits)
|
||||
*/
|
||||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
|
||||
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -3221,7 +3235,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
|
||||
* @param hadc ADC handle
|
||||
* @retval ADC error code (bitfield on 32 bits)
|
||||
*/
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
|
||||
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -3410,7 +3424,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
||||
/* Enable the ADC peripheral */
|
||||
LL_ADC_Enable(hadc->Instance);
|
||||
|
||||
if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
|
||||
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
|
||||
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
|
||||
{
|
||||
/* Delay for temperature sensor buffer stabilization time */
|
||||
/* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
|
||||
@ -3423,7 +3438,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while(wait_loop_index != 0UL)
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
||||
@ -50,9 +50,10 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
|
||||
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
|
||||
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
|
||||
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
|
||||
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
|
||||
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
|
||||
be updated anytime once the ADC is enabled */
|
||||
|
||||
/* Fixed timeout value for ADC calibration. */
|
||||
/* Values defined to be higher than worst cases: maximum ratio between ADC */
|
||||
@ -189,7 +190,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
|
||||
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
|
||||
* @retval Calibration value.
|
||||
*/
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -272,7 +273,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
|
||||
uint32_t tmp_config_injected_queue;
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -338,7 +339,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Clear ADC group injected group conversion flag */
|
||||
/* (To ensure of no unknown state from potential previous ADC operations) */
|
||||
@ -385,7 +386,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
|
||||
/* Start ADC group injected conversion */
|
||||
LL_ADC_INJ_StartConversion(hadc->Instance);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
}
|
||||
else
|
||||
@ -473,14 +474,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t tmp_Flag_End;
|
||||
uint32_t tmp_flag_end;
|
||||
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
|
||||
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
|
||||
uint32_t tmp_cfgr;
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
const ADC_TypeDef *tmpADC_Master;
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -488,18 +489,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
|
||||
/* If end of sequence selected */
|
||||
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
|
||||
{
|
||||
tmp_Flag_End = ADC_FLAG_JEOS;
|
||||
tmp_flag_end = ADC_FLAG_JEOS;
|
||||
}
|
||||
else /* end of conversion selected */
|
||||
{
|
||||
tmp_Flag_End = ADC_FLAG_JEOC;
|
||||
tmp_flag_end = ADC_FLAG_JEOC;
|
||||
}
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until End of Conversion or Sequence flag is raised */
|
||||
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
||||
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
|
||||
{
|
||||
/* Check if timeout is disabled (set to infinite wait) */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
@ -507,7 +508,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
||||
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
@ -543,7 +544,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
|
||||
}
|
||||
#else
|
||||
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Update ADC state machine */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
|
||||
@ -579,7 +580,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
|
||||
}
|
||||
|
||||
/* Clear polled flag */
|
||||
if (tmp_Flag_End == ADC_FLAG_JEOS)
|
||||
if (tmp_flag_end == ADC_FLAG_JEOS)
|
||||
{
|
||||
/* Clear end of sequence JEOS flag of injected group if low power feature */
|
||||
/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
|
||||
@ -617,7 +618,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
|
||||
uint32_t tmp_config_injected_queue;
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
@ -683,7 +684,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Clear ADC group injected group conversion flag */
|
||||
/* (To ensure of no unknown state from potential previous ADC operations) */
|
||||
@ -751,7 +752,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
|
||||
/* Start ADC group injected conversion */
|
||||
LL_ADC_INJ_StartConversion(hadc->Instance);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
}
|
||||
else
|
||||
@ -854,7 +855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status;
|
||||
ADC_HandleTypeDef tmphadcSlave;
|
||||
ADC_HandleTypeDef tmp_hadc_slave;
|
||||
ADC_Common_TypeDef *tmpADC_Common;
|
||||
|
||||
/* Check the parameters */
|
||||
@ -873,13 +874,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Temporary handle minimum initialization */
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
|
||||
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
|
||||
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
|
||||
|
||||
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
if (tmp_hadc_slave.Instance == NULL)
|
||||
{
|
||||
/* Set ADC state */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
@ -895,7 +896,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
|
||||
tmp_hal_status = ADC_Enable(hadc);
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
tmp_hal_status = ADC_Enable(&tmphadcSlave);
|
||||
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
|
||||
}
|
||||
|
||||
/* Start multimode conversion of ADCs pair */
|
||||
@ -974,9 +975,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status;
|
||||
uint32_t tickstart;
|
||||
ADC_HandleTypeDef tmphadcSlave;
|
||||
uint32_t tmphadcSlave_conversion_on_going;
|
||||
HAL_StatusTypeDef tmphadcSlave_disable_status;
|
||||
ADC_HandleTypeDef tmp_hadc_slave;
|
||||
uint32_t tmp_hadc_slave_conversion_on_going;
|
||||
HAL_StatusTypeDef tmp_hadc_slave_disable_status;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
||||
@ -984,7 +985,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
|
||||
/* 1. Stop potential multimode conversion on going, on regular and injected groups */
|
||||
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
|
||||
|
||||
@ -992,13 +992,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
/* Temporary handle minimum initialization */
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
|
||||
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
|
||||
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
|
||||
|
||||
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
if (tmp_hadc_slave.Instance == NULL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
@ -1015,17 +1015,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
||||
|| (tmphadcSlave_conversion_on_going == 1UL)
|
||||
|| (tmp_hadc_slave_conversion_on_going == 1UL)
|
||||
)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
||||
|| (tmphadcSlave_conversion_on_going == 1UL)
|
||||
|| (tmp_hadc_slave_conversion_on_going == 1UL)
|
||||
)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
@ -1038,7 +1038,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
}
|
||||
}
|
||||
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
}
|
||||
|
||||
/* Disable the DMA channel (in case of DMA in circular mode or stop */
|
||||
@ -1062,9 +1062,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
/* memory a potential failing status. */
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
|
||||
tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
|
||||
if ((ADC_Disable(hadc) == HAL_OK) &&
|
||||
(tmphadcSlave_disable_status == HAL_OK))
|
||||
(tmp_hadc_slave_disable_status == HAL_OK))
|
||||
{
|
||||
tmp_hal_status = HAL_OK;
|
||||
}
|
||||
@ -1073,7 +1073,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* In case of error, attempt to disable ADC master and slave without status assert */
|
||||
(void) ADC_Disable(hadc);
|
||||
(void) ADC_Disable(&tmphadcSlave);
|
||||
(void) ADC_Disable(&tmp_hadc_slave);
|
||||
}
|
||||
|
||||
/* Set ADC state (ADC master) */
|
||||
@ -1094,7 +1094,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
|
||||
* @retval The converted data values.
|
||||
*/
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
const ADC_Common_TypeDef *tmpADC_Common;
|
||||
|
||||
@ -1127,7 +1127,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
|
||||
* both flags JEOC and EOS are raised.
|
||||
* Flag JEOS must not be cleared by this function because
|
||||
* it would not be compliant with low power features
|
||||
* (feature low power auto-wait, not available on all STM32 families).
|
||||
* (feature low power auto-wait, not available on all STM32 series).
|
||||
* To clear this flag, either use function:
|
||||
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
|
||||
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
|
||||
@ -1141,7 +1141,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
|
||||
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
|
||||
* @retval ADC group injected conversion data
|
||||
*/
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
|
||||
{
|
||||
uint32_t tmp_jdr;
|
||||
|
||||
@ -1451,7 +1451,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
|
||||
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
|
||||
* conversion is on-going.
|
||||
* @note Multimode is kept enabled after this function. Multimode DMA bits
|
||||
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
|
||||
* multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
|
||||
@ -1467,8 +1468,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status;
|
||||
uint32_t tickstart;
|
||||
ADC_HandleTypeDef tmphadcSlave;
|
||||
uint32_t tmphadcSlave_conversion_on_going;
|
||||
ADC_HandleTypeDef tmp_hadc_slave;
|
||||
uint32_t tmp_hadc_slave_conversion_on_going;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
||||
@ -1487,13 +1488,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
||||
|
||||
/* Temporary handle minimum initialization */
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
|
||||
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
|
||||
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
|
||||
|
||||
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
if (tmp_hadc_slave.Instance == NULL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
@ -1510,17 +1511,17 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
||||
|| (tmphadcSlave_conversion_on_going == 1UL)
|
||||
|| (tmp_hadc_slave_conversion_on_going == 1UL)
|
||||
)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
||||
|| (tmphadcSlave_conversion_on_going == 1UL)
|
||||
|| (tmp_hadc_slave_conversion_on_going == 1UL)
|
||||
)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
@ -1533,7 +1534,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
}
|
||||
}
|
||||
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
}
|
||||
|
||||
/* Disable the DMA channel (in case of DMA in circular mode or stop */
|
||||
@ -1563,9 +1564,9 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
tmp_hal_status = ADC_Disable(hadc);
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
|
||||
if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
|
||||
{
|
||||
tmp_hal_status = ADC_Disable(&tmphadcSlave);
|
||||
tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1644,59 +1645,62 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
||||
* start once the 1st context is set, that is after the first three
|
||||
* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
|
||||
* @param hadc ADC handle
|
||||
* @param sConfigInjected Structure of ADC injected group and ADC channel for
|
||||
* @param pConfigInjected Structure of ADC injected group and ADC channel for
|
||||
* injected group.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
|
||||
const ADC_InjectionConfTypeDef *pConfigInjected)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmpOffsetShifted;
|
||||
uint32_t tmp_offset_shifted;
|
||||
uint32_t tmp_config_internal_channel;
|
||||
uint32_t tmp_adc_is_conversion_on_going_regular;
|
||||
uint32_t tmp_adc_is_conversion_on_going_injected;
|
||||
__IO uint32_t wait_loop_index = 0;
|
||||
|
||||
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
|
||||
uint32_t tmp_jsqr_context_queue_being_built = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
|
||||
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
|
||||
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
|
||||
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
|
||||
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
|
||||
assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
|
||||
assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
|
||||
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
|
||||
assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
|
||||
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
|
||||
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
|
||||
assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
|
||||
assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
|
||||
|
||||
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
||||
{
|
||||
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
|
||||
assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
|
||||
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
|
||||
assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
|
||||
assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
|
||||
}
|
||||
|
||||
|
||||
/* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
|
||||
ignored (considered as reset) */
|
||||
assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
|
||||
assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
|
||||
&& (pConfigInjected->InjecOversamplingMode == ENABLE)));
|
||||
|
||||
/* JDISCEN and JAUTO bits can't be set at the same time */
|
||||
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
|
||||
assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
|
||||
&& (pConfigInjected->AutoInjectedConv == ENABLE)));
|
||||
|
||||
/* DISCEN and JAUTO bits can't be set at the same time */
|
||||
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
|
||||
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
|
||||
|
||||
/* Verification of channel number */
|
||||
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
|
||||
if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
|
||||
{
|
||||
assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
|
||||
assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
|
||||
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
@ -1724,7 +1728,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* by software for alignment over all STM32 devices. */
|
||||
|
||||
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
|
||||
(sConfigInjected->InjectedNbrOfConversion == 1U))
|
||||
(pConfigInjected->InjectedNbrOfConversion == 1U))
|
||||
{
|
||||
/* Configuration of context register JSQR: */
|
||||
/* - number of ranks in injected group sequencer: fixed to 1st rank */
|
||||
@ -1733,28 +1737,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* - external trigger polarity */
|
||||
/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
|
||||
|
||||
if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
|
||||
if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
|
||||
{
|
||||
/* Enable external trigger if trigger selection is different of */
|
||||
/* software start. */
|
||||
/* Note: This configuration keeps the hardware feature of parameter */
|
||||
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
|
||||
/* software start. */
|
||||
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
||||
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
||||
{
|
||||
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
|
||||
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
||||
| sConfigInjected->ExternalTrigInjecConvEdge
|
||||
);
|
||||
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
|
||||
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
||||
| pConfigInjected->ExternalTrigInjecConvEdge
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
|
||||
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
|
||||
}
|
||||
|
||||
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
|
||||
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
|
||||
/* For debug and informative reasons, hadc handle saves JSQR setting */
|
||||
hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
|
||||
hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
|
||||
|
||||
}
|
||||
}
|
||||
@ -1774,7 +1778,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
{
|
||||
/* Initialize number of channels that will be configured on the context */
|
||||
/* being built */
|
||||
hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
|
||||
hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
|
||||
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
|
||||
call, this context will be written in JSQR register at the last call.
|
||||
At this point, the context is merely reset */
|
||||
@ -1790,16 +1794,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* Note: This configuration keeps the hardware feature of parameter */
|
||||
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
|
||||
/* software start. */
|
||||
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
||||
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
||||
{
|
||||
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
|
||||
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
||||
| sConfigInjected->ExternalTrigInjecConvEdge
|
||||
);
|
||||
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
|
||||
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
||||
| pConfigInjected->ExternalTrigInjecConvEdge
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
|
||||
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
|
||||
}
|
||||
|
||||
}
|
||||
@ -1807,18 +1811,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* 2. Continue setting of context under definition with parameter */
|
||||
/* related to each channel: channel rank sequence */
|
||||
/* Clear the old JSQx bits for the selected rank */
|
||||
tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
|
||||
tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
|
||||
|
||||
/* Set the JSQx bits for the selected rank */
|
||||
tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
|
||||
tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
|
||||
|
||||
/* Decrease channel count */
|
||||
hadc->InjectionConfig.ChannelCount--;
|
||||
|
||||
/* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
|
||||
/* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
|
||||
call, aggregate the setting to those already built during the previous
|
||||
HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
|
||||
hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
|
||||
hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
|
||||
|
||||
/* 4. End of context setting: if this is the last channel set, then write context
|
||||
into register JSQR and make it enter into queue */
|
||||
@ -1838,12 +1842,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* If auto-injected mode is disabled: no constraint */
|
||||
if (sConfigInjected->AutoInjectedConv == DISABLE)
|
||||
if (pConfigInjected->AutoInjectedConv == DISABLE)
|
||||
{
|
||||
MODIFY_REG(hadc->Instance->CFGR,
|
||||
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
|
||||
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
|
||||
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
|
||||
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
|
||||
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
|
||||
}
|
||||
/* If auto-injected mode is enabled: Injected discontinuous setting is */
|
||||
/* discarded. */
|
||||
@ -1851,7 +1855,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
{
|
||||
MODIFY_REG(hadc->Instance->CFGR,
|
||||
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
|
||||
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
|
||||
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
|
||||
}
|
||||
|
||||
}
|
||||
@ -1872,10 +1876,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
{
|
||||
/* If injected group external triggers are disabled (set to injected */
|
||||
/* software start): no constraint */
|
||||
if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|
||||
|| (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
|
||||
if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|
||||
|| (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
|
||||
{
|
||||
if (sConfigInjected->AutoInjectedConv == ENABLE)
|
||||
if (pConfigInjected->AutoInjectedConv == ENABLE)
|
||||
{
|
||||
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
|
||||
}
|
||||
@ -1888,7 +1892,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* due to injected group external triggers enabled, error is reported. */
|
||||
else
|
||||
{
|
||||
if (sConfigInjected->AutoInjectedConv == ENABLE)
|
||||
if (pConfigInjected->AutoInjectedConv == ENABLE)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
@ -1901,13 +1905,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
}
|
||||
}
|
||||
|
||||
if (sConfigInjected->InjecOversamplingMode == ENABLE)
|
||||
if (pConfigInjected->InjecOversamplingMode == ENABLE)
|
||||
{
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
|
||||
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
|
||||
assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
|
||||
|
||||
/* JOVSE must be reset in case of triggered regular mode */
|
||||
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
|
||||
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
|
||||
== (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
|
||||
|
||||
/* Configuration of Injected Oversampler: */
|
||||
/* - Oversampling Ratio */
|
||||
@ -1919,8 +1924,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
ADC_CFGR2_OVSR |
|
||||
ADC_CFGR2_OVSS,
|
||||
ADC_CFGR2_JOVSE |
|
||||
sConfigInjected->InjecOversampling.Ratio |
|
||||
sConfigInjected->InjecOversampling.RightBitShift
|
||||
pConfigInjected->InjecOversampling.Ratio |
|
||||
pConfigInjected->InjecOversampling.RightBitShift
|
||||
);
|
||||
}
|
||||
else
|
||||
@ -1931,10 +1936,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
|
||||
#if defined(ADC_SMPR1_SMPPLUS)
|
||||
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
|
||||
if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
|
||||
if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
|
||||
|
||||
/* Set ADC sampling time common configuration */
|
||||
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
|
||||
@ -1942,27 +1947,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
else
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
|
||||
pConfigInjected->InjectedSamplingTime);
|
||||
|
||||
/* Set ADC sampling time common configuration */
|
||||
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
|
||||
}
|
||||
#else
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
|
||||
#endif
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
|
||||
pConfigInjected->InjectedSamplingTime);
|
||||
#endif /* ADC_SMPR1_SMPPLUS */
|
||||
|
||||
/* Configure the offset: offset enable/disable, channel, offset value */
|
||||
|
||||
/* Shift the offset with respect to the selected ADC resolution. */
|
||||
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
|
||||
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
|
||||
tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
|
||||
|
||||
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
|
||||
if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
|
||||
{
|
||||
/* Set ADC selected offset number */
|
||||
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
|
||||
tmpOffsetShifted);
|
||||
LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
|
||||
tmp_offset_shifted);
|
||||
|
||||
}
|
||||
else
|
||||
@ -1970,22 +1977,22 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* Scan each offset register to check if the selected channel is targeted. */
|
||||
/* If this is the case, the corresponding offset number is disabled. */
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
||||
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
|
||||
{
|
||||
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
|
||||
}
|
||||
@ -1999,16 +2006,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Set mode single-ended or differential input of the selected ADC channel */
|
||||
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
|
||||
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
|
||||
|
||||
/* Configuration of differential mode */
|
||||
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
|
||||
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
|
||||
if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
|
||||
{
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
||||
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
|
||||
+ 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
|
||||
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
|
||||
(__LL_ADC_CHANNEL_TO_DECIMAL_NB(
|
||||
(uint32_t)pConfigInjected->InjectedChannel)
|
||||
+ 1UL) & 0x1FUL)),
|
||||
pConfigInjected->InjectedSamplingTime);
|
||||
}
|
||||
|
||||
}
|
||||
@ -2019,13 +2029,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* Note: these internal measurement paths can be disabled using */
|
||||
/* HAL_ADC_DeInit(). */
|
||||
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
|
||||
{
|
||||
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
|
||||
/* If the requested internal measurement path has already been enabled, */
|
||||
/* bypass the configuration processing. */
|
||||
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
|
||||
if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
||||
{
|
||||
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
||||
@ -2038,14 +2048,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
|
||||
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
|
||||
* (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
|
||||
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
||||
{
|
||||
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
||||
@ -2054,7 +2065,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
||||
}
|
||||
}
|
||||
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
|
||||
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
|
||||
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
||||
{
|
||||
if (ADC_VREFINT_INSTANCE(hadc))
|
||||
@ -2090,35 +2101,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
||||
* @note To move back configuration from multimode to single mode, ADC must
|
||||
* be reset (using function HAL_ADC_Init() ).
|
||||
* @param hadc Master ADC handle
|
||||
* @param multimode Structure of ADC multimode configuration
|
||||
* @param pMultimode Structure of ADC multimode configuration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
ADC_Common_TypeDef *tmpADC_Common;
|
||||
ADC_HandleTypeDef tmphadcSlave;
|
||||
uint32_t tmphadcSlave_conversion_on_going;
|
||||
ADC_HandleTypeDef tmp_hadc_slave;
|
||||
uint32_t tmp_hadc_slave_conversion_on_going;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_MULTIMODE(multimode->Mode));
|
||||
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
|
||||
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
{
|
||||
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
|
||||
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
||||
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
|
||||
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Temporary handle minimum initialization */
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
|
||||
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
|
||||
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
|
||||
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
|
||||
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
if (tmp_hadc_slave.Instance == NULL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
@ -2134,9 +2145,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
|
||||
/* conversion on going on regular group: */
|
||||
/* - Multimode DMA configuration */
|
||||
/* - Multimode DMA mode */
|
||||
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
||||
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
||||
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
&& (tmphadcSlave_conversion_on_going == 0UL))
|
||||
&& (tmp_hadc_slave_conversion_on_going == 0UL))
|
||||
{
|
||||
/* Pointer to the common control register */
|
||||
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
||||
@ -2144,10 +2155,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
|
||||
/* If multimode is selected, configure all multimode parameters. */
|
||||
/* Otherwise, reset multimode parameters (can be used in case of */
|
||||
/* transition from multimode to independent mode). */
|
||||
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
{
|
||||
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
|
||||
multimode->DMAAccessMode |
|
||||
pMultimode->DMAAccessMode |
|
||||
ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
||||
|
||||
/* Parameters that can be updated only when ADC is disabled: */
|
||||
@ -2165,8 +2176,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
|
||||
MODIFY_REG(tmpADC_Common->CCR,
|
||||
ADC_CCR_DUAL |
|
||||
ADC_CCR_DELAY,
|
||||
multimode->Mode |
|
||||
multimode->TwoSamplingDelay
|
||||
pMultimode->Mode |
|
||||
pMultimode->TwoSamplingDelay
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
|
||||
(++) Configure CAN pins
|
||||
(+++) Enable the clock for the CAN GPIOs
|
||||
(+++) Configure CAN pins as alternate function open-drain
|
||||
(+++) Configure CAN pins as alternate function
|
||||
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
|
||||
(+++) Configure the CAN interrupt priority using
|
||||
HAL_NVIC_SetPriority()
|
||||
@ -235,6 +235,7 @@
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TIMEOUT_VALUE 10U
|
||||
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -248,8 +249,8 @@
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
|
||||
/* Init the low level hardware: CLOCK, NVIC */
|
||||
HAL_CAN_MspInit(hcan);
|
||||
}
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
|
||||
/* Request initialisation */
|
||||
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
|
||||
@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
|
||||
#else
|
||||
/* DeInit the low level hardware: CLOCK, NVIC */
|
||||
HAL_CAN_MspDeInit(hcan);
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
|
||||
/* Reset the CAN peripheral */
|
||||
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
|
||||
@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
|
||||
* @brief Configuration functions.
|
||||
*
|
||||
* @brief Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Configuration functions #####
|
||||
@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
|
||||
#endif
|
||||
#endif /* CAN3 */
|
||||
|
||||
/* Initialisation mode for the filter */
|
||||
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
|
||||
@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
|
||||
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
|
||||
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
|
||||
|
||||
#endif
|
||||
#endif /* CAN3 */
|
||||
/* Convert filter number into bit position */
|
||||
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
|
||||
|
||||
@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group3 Control functions
|
||||
* @brief Control functions
|
||||
*
|
||||
* @brief Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Control functions #####
|
||||
@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
|
||||
{
|
||||
__IO uint32_t count = 0;
|
||||
uint32_t timeout = 1000000U;
|
||||
HAL_CAN_StateTypeDef state = hcan->State;
|
||||
|
||||
if ((state == HAL_CAN_STATE_READY) ||
|
||||
@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
|
||||
count++;
|
||||
|
||||
/* Check if timeout is reached */
|
||||
if (count > timeout)
|
||||
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
|
||||
{
|
||||
/* Update error code */
|
||||
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
|
||||
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
@ -1524,7 +1523,15 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
|
||||
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
|
||||
}
|
||||
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
|
||||
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
|
||||
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
|
||||
{
|
||||
/* Truncate DLC to 8 if received field is over range */
|
||||
pHeader->DLC = 8U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
|
||||
}
|
||||
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
|
||||
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
|
||||
|
||||
@ -1600,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
|
||||
* @brief Interrupts management
|
||||
*
|
||||
* @brief Interrupts management
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts management #####
|
||||
@ -2066,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
|
||||
* @brief CAN Callback functions
|
||||
*
|
||||
* @brief CAN Callback functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Callback functions #####
|
||||
@ -2316,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
|
||||
* @brief CAN Peripheral State functions
|
||||
*
|
||||
* @brief CAN Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State and Error functions #####
|
||||
|
||||
@ -451,6 +451,37 @@ void HAL_MPU_Disable(void)
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Enable the Region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize and configure the Region and the memory to be protected.
|
||||
@ -463,38 +494,31 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != RESET)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
/* Apply configuration */
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
|
||||
@ -199,9 +199,15 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
/* Reset CRC calculation unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
#if defined(CRC_IDR32BITSLENGTH_SUPPORT)
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
|
||||
__HAL_CRC_SET_IDR(hcrc, 0);
|
||||
|
||||
#else
|
||||
/* Reset IDR register content */
|
||||
CLEAR_REG(hcrc->Instance->IDR);
|
||||
|
||||
#endif /* CRC_IDR32BITSLENGTH_SUPPORT */
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
@ -403,7 +409,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Return CRC handle state */
|
||||
return hcrc->State;
|
||||
|
||||
@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
/* Ensure that the generating polynomial is odd */
|
||||
if ((Pol & (uint32_t)(0x1U)) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
switch (PolyLength)
|
||||
else
|
||||
{
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
{
|
||||
}
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
switch (PolyLength)
|
||||
{
|
||||
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
@ -201,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -171,14 +171,14 @@
|
||||
A DMA1 request can be generated when an external trigger (but not a software trigger)
|
||||
occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
|
||||
DMA requests are mapped as following:
|
||||
(#) When DMAMUX is NOT present:
|
||||
(#) When DMAMUX is NOT present:
|
||||
DMA1 requests are mapped as following:
|
||||
(+) DAC channel1 mapped on DMA1 request 6 / channel3
|
||||
(+) DAC channel2 mapped on DMA1 request 5 / channel4
|
||||
DMA2 requests are mapped as following:
|
||||
(+) DAC channel1 mapped on DMA2 request 3 / channel4
|
||||
(+) DAC channel2 mapped on DMA2 request 3 / channel5
|
||||
(#) When DMAMUX is present:
|
||||
(#) When DMAMUX is present:
|
||||
(+) DAC channel1 mapped on DMA1/DMA2 request 6 (can be any DMA channel)
|
||||
(+) DAC channel2 mapped on DMA1/DMA2 request 7 (can be any DMA channel)
|
||||
|
||||
@ -264,7 +264,7 @@
|
||||
and a pointer to the user callback function.
|
||||
|
||||
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function. It allows to reset following callbacks:
|
||||
weak (overridden) function. It allows to reset following callbacks:
|
||||
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
|
||||
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
|
||||
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
|
||||
@ -279,9 +279,9 @@
|
||||
This function) takes as parameters the HAL peripheral handle and the Callback ID.
|
||||
|
||||
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
|
||||
all callbacks are reset to the corresponding legacy weak (overridden) functions.
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
|
||||
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
|
||||
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
|
||||
@ -296,7 +296,7 @@
|
||||
|
||||
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak (overridden) callbacks are used.
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
|
||||
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
|
||||
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
|
||||
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
|
||||
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
|
||||
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
|
||||
@ -405,7 +405,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
|
||||
/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
|
||||
/* STM32L4P5xx STM32L4Q5xx */
|
||||
/* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
|
||||
|
||||
|
||||
if (hdac->MspInitCallback == NULL)
|
||||
{
|
||||
hdac->MspInitCallback = HAL_DAC_MspInit;
|
||||
@ -1249,13 +1249,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
HAL_Delay(1);
|
||||
@ -1271,13 +1275,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
HAL_Delay(1U);
|
||||
@ -1437,7 +1445,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User DAC Callback
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* To be used instead of the weak (overridden) predefined callback
|
||||
* @param hdac DAC handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
@ -1546,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
||||
|
||||
/**
|
||||
* @brief Unregister a User DAC Callback
|
||||
* DAC Callback is redirected to the weak (surcharged) predefined callback
|
||||
* DAC Callback is redirected to the weak (overridden) predefined callback
|
||||
* @param hdac DAC handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
||||
@ -425,10 +425,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
||||
|
||||
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvalue++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
||||
/* Check trimming value below maximum */
|
||||
if (trimmingvalue < 0x1FU)
|
||||
{
|
||||
/* Trimming is actually one value more */
|
||||
trimmingvalue++;
|
||||
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the selected DAC channel calibration */
|
||||
|
||||
@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
if (hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
*/
|
||||
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
||||
|
||||
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
/* if memory to memory force the request to 0*/
|
||||
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
|
||||
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
||||
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
||||
{
|
||||
/* Initialize parameters for DMAMUX request generator :
|
||||
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
|
||||
@ -249,7 +249,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
#if !defined (DMAMUX1)
|
||||
|
||||
/* Set request selection */
|
||||
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
|
||||
if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
/* Write to DMA channel selection register */
|
||||
if (DMA1 == hdma->DmaBaseAddress)
|
||||
@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Configure request selection for DMA1 Channelx */
|
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
|
||||
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
|
||||
}
|
||||
else /* DMA2 */
|
||||
{
|
||||
@ -266,13 +266,13 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
|
||||
|
||||
/* Configure request selection for DMA2 Channelx */
|
||||
DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
|
||||
DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
|
||||
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
|
||||
/* STM32L496xx || STM32L4A6xx */
|
||||
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
|
||||
/* STM32L496xx || STM32L4A6xx */
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
@ -296,7 +296,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma )
|
||||
if (NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
@ -341,8 +341,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
|
||||
}
|
||||
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
|
||||
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
|
||||
/* STM32L496xx || STM32L4A6xx */
|
||||
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
|
||||
/* STM32L496xx || STM32L4A6xx */
|
||||
|
||||
#if defined(DMAMUX1)
|
||||
|
||||
@ -358,7 +358,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
/* Reset Request generator parameters if any */
|
||||
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
||||
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
||||
{
|
||||
/* Initialize parameters for DMAMUX request generator :
|
||||
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
|
||||
@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
/* Enable the transfer Error interrupt */
|
||||
if(NULL != hdma->XferHalfCpltCallback )
|
||||
if (NULL != hdma->XferHalfCpltCallback)
|
||||
{
|
||||
/* Enable the Half transfer complete interrupt as well */
|
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
@ -509,13 +509,13 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
|
||||
#ifdef DMAMUX1
|
||||
|
||||
/* Check if DMAMUX Synchronization is enabled*/
|
||||
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
||||
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
||||
{
|
||||
/* Enable DMAMUX sync overrun IT*/
|
||||
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
||||
}
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
|
||||
/* enable the request gen overrun IT*/
|
||||
@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State != HAL_DMA_STATE_BUSY)
|
||||
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
||||
/* disable the request gen overrun IT*/
|
||||
@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
||||
/* disable the request gen overrun IT*/
|
||||
@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
if (hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
uint32_t temp;
|
||||
uint32_t tickstart;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
@ -708,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while((hdma->DmaBaseAddress->ISR & temp) == 0U)
|
||||
while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
|
||||
{
|
||||
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
|
||||
if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_READY;
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
@ -729,9 +729,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
@ -749,10 +749,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
|
||||
#if defined(DMAMUX1)
|
||||
/*Check for DMAMUX Request generator (if used) overrun status */
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
|
||||
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the request gen overrun interrupt */
|
||||
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
||||
@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
}
|
||||
|
||||
/* Check for DMAMUX Synchronization overrun */
|
||||
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
{
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
@ -776,10 +776,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
||||
}
|
||||
#endif /* DMAMUX1 */
|
||||
|
||||
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
@ -811,29 +811,29 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* but in Transfer Complete case */
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* but in Transfer Complete case */
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
if (hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
|
||||
{
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
||||
/* Disable the transfer complete and error interrupt */
|
||||
@ -849,7 +849,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
if (hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
@ -895,40 +895,40 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callbacsk function which has pointer to
|
||||
* @param pCallback pointer to private callback function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -954,39 +954,39 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -1072,7 +1072,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* Clear the DMAMUX request generator overrun flag */
|
||||
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||||
@ -1086,7 +1086,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
@ -114,17 +114,17 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
|
||||
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
|
||||
|
||||
/*Check if the DMA state is ready */
|
||||
if(hdma->State == HAL_DMA_STATE_READY)
|
||||
if (hdma->State == HAL_DMA_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
|
||||
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
|
||||
(~DMAMUX_CxCR_DMAREQ_ID) , \
|
||||
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
|
||||
(~DMAMUX_CxCR_DMAREQ_ID), \
|
||||
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
|
||||
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
|
||||
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
|
||||
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
|
||||
|
||||
/* Process UnLocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
@ -160,24 +160,24 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
|
||||
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Set the request generator new parameters */
|
||||
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
|
||||
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
|
||||
pRequestGeneratorConfig->Polarity;
|
||||
/* Process UnLocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
|
||||
pRequestGeneratorConfig->Polarity;
|
||||
/* Process UnLocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
@ -194,18 +194,18 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
|
||||
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
|
||||
{
|
||||
|
||||
/* Enable the request generator*/
|
||||
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
@ -222,7 +222,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
|
||||
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
|
||||
{
|
||||
|
||||
/* Disable the request generator*/
|
||||
@ -245,7 +245,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check for DMAMUX Synchronization overrun */
|
||||
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the synchro overrun interrupt */
|
||||
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
||||
@ -256,17 +256,17 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0)
|
||||
if (hdma->DMAmuxRequestGen != 0)
|
||||
{
|
||||
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
|
||||
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
|
||||
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the request gen overrun interrupt */
|
||||
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
||||
@ -277,7 +277,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
|
||||
@ -64,7 +64,7 @@
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
@ -75,7 +75,7 @@
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@ -346,7 +346,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -538,6 +538,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
@ -572,6 +575,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
* @brief Read the specified input port pin.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
*
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -126,7 +126,8 @@
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds.
|
||||
LSI startup time is also considered here by adding LSI_STARTUP_TIME
|
||||
converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
|
||||
((LSI_STARTUP_TIME / 1000UL) + 1UL))
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void)
|
||||
=========================================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
|
||||
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
|
||||
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
|
||||
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
|
||||
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
|
||||
@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void)
|
||||
===============================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
|
||||
The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
|
||||
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
|
||||
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
|
||||
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
|
||||
@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void)
|
||||
and Standby circuitry.
|
||||
|
||||
(++) Entry:
|
||||
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
|
||||
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
|
||||
SRAM1 and register contents are lost except for registers in the Backup domain and
|
||||
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
|
||||
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
|
||||
@ -264,7 +264,7 @@ void HAL_PWR_DisableBkUpAccess(void)
|
||||
SRAM and registers contents are lost except for backup domain registers.
|
||||
|
||||
(+) Entry:
|
||||
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
|
||||
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
|
||||
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
|
||||
|
||||
@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
||||
|
||||
/**
|
||||
* @brief Enable battery charging.
|
||||
* When VDD is present, charge the external battery on VBAT thru an internal resistor.
|
||||
* When VDD is present, charge the external battery on VBAT through an internal resistor.
|
||||
* @param ResistorSelection specifies the resistor impedance.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
|
||||
@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
|
||||
|
||||
|
||||
/* Configure EXTI 35 to 38 interrupts if so required:
|
||||
scan thru PVMType to detect which PVMx is set and
|
||||
scan through PVMType to detect which PVMx is set and
|
||||
configure the corresponding EXTI line accordingly. */
|
||||
switch (sConfigPVM->PVMType)
|
||||
{
|
||||
|
||||
@ -398,6 +398,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
|
||||
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
||||
* supported by this macro. User should request a transition to HSE Off
|
||||
* first and then HSE On or HSE Bypass.
|
||||
* @note If HSE failed to start, HSE should be disabled before recalling
|
||||
HAL_RCC_OscConfig().
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||
@ -1318,7 +1320,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
||||
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
||||
@ -1852,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
||||
/* MSI 8Mhz */
|
||||
latency = FLASH_LATENCY_1; /* 1WS */
|
||||
}
|
||||
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
||||
else
|
||||
{
|
||||
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
||||
/* nothing to do */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
||||
status = ret;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
|
||||
|
||||
@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
|
||||
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
|
||||
and also HSI48 oscillator smooth trimming.
|
||||
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
|
||||
directly reload value with target and sychronization frequencies values
|
||||
directly reload value with target and synchronization frequencies values
|
||||
(##) Call function HAL_RCCEx_CRSConfig which
|
||||
(+++) Resets CRS registers to their default values.
|
||||
(+++) Configures CRS registers with synchronization configuration
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -76,7 +76,7 @@
|
||||
* the configuration information for the specified SPI module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
uint8_t count = 0U;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,86 +1,70 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
|
||||
** File : LinkerScript.ld
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by System Workbench for STM32
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32L432KBUx series
|
||||
** 128Kbytes FLASH and 80Kbytes RAM
|
||||
** @brief : Linker script for STM32L432KBUx Device from STM32L4 series
|
||||
** 256KBytes FLASH
|
||||
** 48KBytes RAM
|
||||
** 16KBytes RAM2
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed <EFBFBD>as is,<EFBFBD> without any warranty
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
** Copyright (c) 2025 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20010000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 16K
|
||||
FLASH (rx) : ORIGIN = 0x8002800, LENGTH = 128K - 10K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
|
||||
RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 16K
|
||||
FLASH (rx) : ORIGIN = 0x8002800, LENGTH = 128K - 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
@ -90,82 +74,87 @@ SECTIONS
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
|
||||
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
|
||||
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
|
||||
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
@ -177,7 +166,7 @@ SECTIONS
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
@ -188,9 +177,7 @@ SECTIONS
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
@ -200,5 +187,3 @@ SECTIONS
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
||||
|
||||
13
tecware.ioc
13
tecware.ioc
@ -26,8 +26,8 @@ ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5
|
||||
ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5
|
||||
ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5
|
||||
ADC1.master=1
|
||||
CAD.formats=
|
||||
CAD.pinconfig=
|
||||
CAD.formats=[]
|
||||
CAD.pinconfig=Dual
|
||||
CAD.provider=
|
||||
CAN1.BS1=CAN_BS1_13TQ
|
||||
CAN1.BS2=CAN_BS2_6TQ
|
||||
@ -76,7 +76,7 @@ FREERTOS.configUSE_NEWLIB_REENTRANT=1
|
||||
File.Version=6
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
I2C1.IPParameters=Timing
|
||||
I2C1.Timing=0x10909CEC
|
||||
I2C1.Timing=0x10D19CE4
|
||||
IWDG.IPParameters=Prescaler,Window,Reload
|
||||
IWDG.Prescaler=IWDG_PRESCALER_256
|
||||
IWDG.Reload=150
|
||||
@ -131,8 +131,8 @@ Mcu.PinsNb=28
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32L432KBUx
|
||||
MxCube.Version=6.10.0
|
||||
MxDb.Version=DB.6.0.100
|
||||
MxCube.Version=6.14.0
|
||||
MxDb.Version=DB.6.0.140
|
||||
NVIC.ADC1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.CAN1_RX0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
@ -227,6 +227,7 @@ PC15-OSC32_OUT\ (PC15).Signal=GPIO_Input
|
||||
PinOutPanel.RotationAngle=0
|
||||
ProjectManager.AskForMigrate=true
|
||||
ProjectManager.BackupPrevious=false
|
||||
ProjectManager.CompilerLinker=GCC
|
||||
ProjectManager.CompilerOptimize=6
|
||||
ProjectManager.ComputerToolchain=false
|
||||
ProjectManager.CoupleFile=false
|
||||
@ -234,7 +235,7 @@ ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32L432KBUx
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.17.2
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.18.1
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x200
|
||||
|
||||
2759
tecware_v11.srec
Normal file
2759
tecware_v11.srec
Normal file
File diff suppressed because it is too large
Load Diff
2759
tecware_v12.srec
Normal file
2759
tecware_v12.srec
Normal file
File diff suppressed because it is too large
Load Diff
2759
tecware_v13.srec
Normal file
2759
tecware_v13.srec
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user