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01de9bd1a9
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Add register to control caching behavior on AXI link that performs the dma transfer
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2024-08-08 11:53:32 +02:00 |
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12c010fe45
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Add timeout control bits and logic to ignore timeout or configure framebased timeout in input logic.
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2023-09-19 16:09:12 +02:00 |
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7de31cc946
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DOC: Fixed documentation (WINCNTw is in samples, not bytes)
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2019-11-12 14:39:54 +01:00 |
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2838d1e3e9
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DOC: Fixed documentation (use strHandle instead of ipHandle in example code)
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2019-11-12 14:38:42 +01:00 |
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d455112276
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DEVEL: First open source release
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2019-08-02 10:03:58 +02:00 |
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