Commit Graph

18 Commits

Author SHA1 Message Date
12c010fe45 Add timeout control bits and logic to ignore timeout or configure framebased timeout in input logic. 2023-09-19 16:09:12 +02:00
f6178e9dbd Refactoring and compliant with 3.0.0 release psi_common 2.0.0 2023-04-14 17:36:50 +02:00
28b79e93a9 DOC: Updated Changelog.md 1.2.3 2020-09-30 14:28:16 +02:00
7a45fa8df8 DOC: Updated Readme.md 2020-04-02 10:47:05 +02:00
Oliver Bründler
a0464c6a9d DOC: Updated Readme.md 2019-12-19 07:57:00 +01:00
Oliver Bruendler
5390c0c3c0 BUGFIX: Workaround for ISE tools implementing memory as FFs in case of 1 stream 1.2.2 2019-11-25 10:23:36 +01:00
Oliver Bruendler
cec193edca DEVEL: Updated documentation for release 1.2.1 2019-11-19 10:58:25 +01:00
Oliver Bruendler
141d54dd4f DEVEL: Fix testbench (tolerate additional IRQs on stream2) 2019-11-15 13:57:05 +01:00
Oliver Bruendler
8b2211d07a FEATURE: Added claring of the maximum level FIFO to the driver 2019-11-14 07:56:38 +01:00
Oliver Bruendler
7de31cc946 DOC: Fixed documentation (WINCNTw is in samples, not bytes) 2019-11-12 14:39:54 +01:00
Oliver Bruendler
2838d1e3e9 DOC: Fixed documentation (use strHandle instead of ipHandle in example code) 2019-11-12 14:38:42 +01:00
Oliver Bruendler
404af6d979 BUGFIX: Fix data unwrapping (bug found in HIPA LLRF bringup) 2019-11-12 14:37:39 +01:00
Oliver Bruendler
df29e19f6d TIMING: Optimized timing on critical path between input FIFO and DMA
Added pipeline stage after FIFO to reduce requirements of fall-through interface
2019-11-07 07:46:37 +01:00
Oliver Bruendler
7f22ec9050 BUGFIX: Made design working for 1 stream 2019-10-30 11:02:11 +01:00
Oliver Bruendler
3efc256530 Merge branch 'master' of https://github.com/paulscherrerinstitute/psi_multi_stream_daq 2019-10-30 08:06:15 +01:00
Oliver Bruendler
be272f611c DEVEL: Made driver C++ tolerant 2019-10-21 17:41:29 +02:00
Oliver Bruendler
9ad003bc41 DEVEL: Made driver C++ compatible 2019-10-21 17:39:21 +02:00
Oliver Bruendler
d455112276 DEVEL: First open source release 1.2.0 2019-08-02 10:03:58 +02:00