107 lines
5.2 KiB
C++
107 lines
5.2 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "hls_jfjoch.h"
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// Loads calibration from host memory based on 64-bit memory addresses loaded in in_mem_location
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// Expected structure in in_mem_location array:
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//
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// * gain factors for module m at location: 2 + gain level * NMODULES + m
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// * pedestal factors for module m and storage cell s at location: 2 + 3 * NMODULES + (gain level * 16 + s ) * NMODULES + m
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void read_module(ap_uint<256> *d_hbm_p0,
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ap_uint<256> *d_hbm_p1,
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hls::stream<ap_axiu<512,1,1,1> > &host_memory_in,
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size_t offset_hbm_0,
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size_t offset_hbm_1) {
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#pragma HLS INLINE OFF
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
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#pragma HLS PIPELINE II=1
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ap_axiu<512, 1, 1, 1> data_packet;
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host_memory_in >> data_packet;
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d_hbm_p0[offset_hbm_0 + i] = data_packet.data(255, 0);
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d_hbm_p1[offset_hbm_1 + i] = data_packet.data(511, 256);
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}
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}
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void load_calibration(ap_uint<256> *d_hbm_p0,
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ap_uint<256> *d_hbm_p1,
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ap_uint<8> modules,
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ap_uint<5> storage_cells,
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ap_uint<32> hbm_size_bytes,
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ap_uint<8> destination,
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hls::stream<axis_datamover_ctrl> &datamover_in_cmd,
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hls::stream<ap_axiu<512,1,1,1> > &host_memory_in,
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uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) {
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#pragma HLS INTERFACE mode=s_axilite port=return
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#pragma HLS INTERFACE mode=s_axilite port=in_mem_location
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#pragma HLS INTERFACE register both axis port=datamover_in_cmd
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#pragma HLS INTERFACE register both axis port=host_memory_in
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#pragma HLS INTERFACE mode=s_axilite port=modules
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#pragma HLS INTERFACE mode=s_axilite port=storage_cells
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#pragma HLS INTERFACE mode=s_axilite port=destination
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#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
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#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
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if (modules > MAX_MODULES_FPGA)
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return;
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if (destination == LOAD_CALIBRATION_DEST_CALIB) {
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if (storage_cells > 16)
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return;
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for (int c = 0; c < 3; c++) {
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for (int m = 0; m < modules; m++) {
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#pragma HLS PIPELINE OFF
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setup_datamover(datamover_in_cmd, in_mem_location[c * modules + m], RAW_MODULE_SIZE * sizeof(int16_t));
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size_t offset_hbm_0 = (2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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size_t offset_hbm_1 = (2 * c + 1) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
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}
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}
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for (int c = 0; c < 3; c++) {
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for (int m = 0; m < modules * storage_cells; m++) {
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#pragma HLS PIPELINE OFF
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setup_datamover(datamover_in_cmd, in_mem_location[3 * modules + c * modules * storage_cells + m],
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RAW_MODULE_SIZE * sizeof(int16_t));
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size_t offset_hbm_0 = (6 + 2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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size_t offset_hbm_1 =
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(6 + 2 * c + 1) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
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}
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}
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} else if (destination == LOAD_CALIBRATION_DEST_INTEGRATION) {
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// load maps
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for (int m = 0; m < modules; m++) {
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#pragma HLS PIPELINE OFF
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setup_datamover(datamover_in_cmd, in_mem_location[m], RAW_MODULE_SIZE * sizeof(int16_t));
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size_t offset_hbm_0 = 16 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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size_t offset_hbm_1 = 17 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
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}
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// load weights
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for (int m = 0; m < modules; m++) {
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#pragma HLS PIPELINE OFF
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setup_datamover(datamover_in_cmd, in_mem_location[modules + m], RAW_MODULE_SIZE * sizeof(int16_t));
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size_t offset_hbm_0 = 18 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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size_t offset_hbm_1 = 19 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
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}
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} else if (destination == LOAD_CALIBRATION_DEST_FRAME_GEN) {
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for (int m = 0; m < modules; m++) {
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#pragma HLS PIPELINE OFF
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setup_datamover(datamover_in_cmd, in_mem_location[m], RAW_MODULE_SIZE * sizeof(int16_t));
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size_t offset_hbm_0 = 20 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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size_t offset_hbm_1 = 21 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
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read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
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}
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}
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}
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