Logo
Explore Help
Sign In
mx/Jungfraujoch
Watch 1
Star 1
Fork 0
Code Issues Pull Requests 1 Actions Packages Projects Releases 53 Wiki Activity
Files
aee9d0e6fc048252111afa47a5dc366bb14204af
Jungfraujoch/fpga/scripts
T
History
leonarski_f f3e85deb31 FPGA: Increase PCIe BAR size to 16 MB
2023-09-13 20:55:10 +02:00
..
bd_pcie.tcl
FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
2023-09-13 20:06:09 +02:00
build_pcie_design.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
check_hls.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
hbm_u55c.tcl
FPGA: load calibration operates directly on HBM
2023-09-11 21:47:29 +02:00
jfjoch.tcl
FPGA: Some clean-up of frame generator
2023-09-13 20:53:55 +02:00
mac_100g_pcie.tcl
FPGA: Increase FIFO size to improve buffering capability
2023-09-07 12:23:38 +02:00
network_stack.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
pcie_dma.tcl
FPGA: Increase PCIe BAR size to 16 MB
2023-09-13 20:55:10 +02:00
setup_action.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_and_impl.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_hls_function.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
Powered by Gitea Version: 1.27.0+dev-210-g67f86bc3fe Page: 30ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API