v1.0.0-rc.150 #60

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leonarski_f merged 2 commits from 2606-force-cpu-azint into main 2026-06-15 20:24:15 +02:00

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leonarski_f commented 2026-06-15 20:24:04 +02:00

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• jfjoch_broker: When in FPGA workflow (with PSI detectors) azimuthal integration might be forced to CPU - this will require more computational power, but it enables more integration bins and reports standard deviation of each bin.
• jfjoch_broker: Raise error if one is in FPGA flow and there are too many azimuthal integration bins.

* jfjoch_broker: When in FPGA workflow (with PSI detectors) azimuthal integration might be forced to CPU - this will require more computational power, but it enables more integration bins and reports standard deviation of each bin. * jfjoch_broker: Raise error if one is in FPGA flow and there are too many azimuthal integration bins.

leonarski_f added 2 commits 2026-06-15 20:24:04 +02:00

Force CPU azimuthal integration in FPGA workflow ... 51451f167b

Add AzimuthalIntegrationSettings::ForceCPUinFPGAWorkflow so the FPGA
data-acquisition path can compute azimuthal integration on the CPU instead
of the FPGA. This removes the FPGA bin-count limit (FPGA_INTEGRATION_BIN_COUNT)
and adds per-bin standard deviation.

- MXAnalysisAfterFPGA runs AzIntEngineCPU on the assembled image; the FPGA
  integration-map load and per-module read-back are skipped when forced.
- JFJochReceiverFPGA rejects bin counts above the FPGA limit at acquisition
  start (unless CPU is forced) with an actionable error.
- Wire force_cpu through the broker (both directions) and the frontend.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

VERSION: 1.0.0-rc.150 04db106bd0

leonarski_f merged commit 90e804acd7 into main 2026-06-15 20:24:15 +02:00

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Reference: mx/Jungfraujoch#60