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c67337cfe1
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v1.0.0-rc.72
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2025-09-08 20:28:59 +02:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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9630c06b02
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Modifications necessary for the EIGER test
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2024-04-18 15:36:52 +02:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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31304553be
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FPGA: sls_detector had hardcoded max module number -> fixed
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2023-11-01 13:28:17 +01:00 |
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4011c4541d
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HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1
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2023-10-26 19:42:15 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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