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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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e812918e2e
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version 1.0.0-rc.13
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2024-10-05 13:14:49 +02:00 |
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9630c06b02
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Modifications necessary for the EIGER test
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2024-04-18 15:36:52 +02:00 |
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30e775d8a2
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Improve plotting
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2024-03-31 23:08:19 +02:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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41985b6c29
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FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly.
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2023-11-07 19:11:37 +01:00 |
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9f110f3c1a
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FPGA: nmodules is actually module - 1 (there will be never 0 modules, while it can encode 32)
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2023-11-01 14:28:32 +01:00 |
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4011c4541d
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HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1
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2023-10-26 19:42:15 +02:00 |
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5bb92aed61
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FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer
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2023-09-29 14:44:08 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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f98b5fe389
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FPGA: use only two HBM channels to write calibration in JF conversion
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2023-09-11 20:30:46 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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929f6c6544
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FPGA: Handle HBM offsets internally in Jungfraujoch logic
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2023-09-09 20:50:41 +02:00 |
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e8c0500ea8
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FPGA: Use HBM switch to access full HBM
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2023-09-08 17:09:33 +02:00 |
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3f7c2600d0
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FPGA: Allow any storage cell number from 1 to 16
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2023-07-04 21:16:25 +02:00 |
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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