FPGA: Small rewrite of the internal_packet_generator

2023-06-02 21:59:24 +02:00
parent 62ce464fb9
commit 9497d84f3c
1 changed files with 2 additions and 4 deletions
@@ -57,10 +57,9 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
    if (internal_packet_generator) {
        uint32_t frame_number = 1;
        uint8_t module_number = 0;
-        ap_uint<1> cancel = in_cancel;

-    generate_frames:
-        while (!cancel && (frame_number <= nframes)) {
+        generate_frames:
+        while (!in_cancel.read() && (frame_number <= nframes)) {
            for (uint32_t i = 0; i < RAW_MODULE_SIZE * 2 / 64; i++) {
 #pragma HLS PIPELINE II=1
                uint32_t eth_packet = i / 128;
@@ -79,7 +78,6 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
                module_number = 0;
            } else
                module_number++;
-            cancel = in_cancel;
        }
    }