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FPGA: Fix frame generator empty/full signal

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This commit is contained in:
leonarski_f
2023-09-19 19:46:48 +02:00
parent 62bb0c9e98
commit 67473bcac1
1 changed files with 2 additions and 2 deletions
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4
fpga/hdl/action_config.v
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@@ -582,8 +582,8 @@ always @(posedge clk) begin
reg_fifo_status[21] <= h2c_data_fifo_full;
reg_fifo_status[22] <= h2c_cmd_fifo_empty;
reg_fifo_status[23] <= h2c_cmd_fifo_full;
reg_fifo_status[24] <= frame_generator_fifo_full;
reg_fifo_status[25] <= frame_generator_fifo_empty;
reg_fifo_status[24] <= frame_generator_fifo_empty;
reg_fifo_status[25] <= frame_generator_fifo_full;
reg_fifo_status[26] <= eth_in_fifo_full;
reg_fifo_status[27] <= eth_in_fifo_empty;
end