lin-epics-modules/sinqDAQ
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corrects the handling of clearing bits in the simulation
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wall_e
2026-02-17 09:52:54 +01:00
parent 4801dc3279
commit f69356d7ca
1 changed files with 13 additions and 3 deletions
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16
sim/daq_sim.py
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@@ -261,10 +261,20 @@ with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s:
elif re.fullmatch(r'CC (\d+)', data): elif re.fullmatch(r'CC (\d+)', data):
counter = int(re.fullmatch(r'CC (\d+)', data).group(1)) counter = int(re.fullmatch(r'CC (\d+)', data).group(1))
num_bits = daq.total_channels num_bits = daq.total_channels
bits = [(counter >> bit) & 1 for bit in range(num_bits - 1, -1, -1)] # We add 1, as it also includes the time
bits = [(counter >> bit) & 1 for bit in range(0, num_bits + 1)]
for ch, bit in enumerate(bits): for ch, bit in enumerate(bits):
if bit: if ch < 4:
daq.clearCount(ch) if bit:
daq.clearCount(ch)
if ch == 4:
if bit:
daq.clearTime()
if ch > 4:
if bit:
daq.clearCount(ch - 1)
send('') send('')
elif re.fullmatch(r'TP (\d+(\.\d+)?)', data): elif re.fullmatch(r'TP (\d+(\.\d+)?)', data):